Messages from 129575

Article: 129575
Subject: Re: Preventing optimization in cross clock domain logic
From: rickman <gnuarm@gmail.com>
Date: Wed, 27 Feb 2008 18:42:18 -0800 (PST)
Links: << >> << T >> << A >>

On Feb 27, 9:06 pm, Tom <tom.der...@gmail.com> wrote:
>
> Thanks very much for the code. I've interpreted it a bit for my case,
> which seems to work (using numeric_std):
>
> signal t1, t2, t3 : std_logic;
> -----
> process (in_clk_in, rst_in) -- on input clock
> begin
> if rst_in = '1' then
> t1 <= '0';
> elsif rising_edge(in_clk_in) then
> if pulse_in = '1' then
> t1 <= not(t2); -- when detect input pulse, set t1 to inverse of t2
> end if;
> end if;
> end process;
>
> process (out_clk_in, rst_in) -- on output clock
> begin
> if rst_in = '1' then
> t2 <= '0';
> t3 <= '0';
> pulse_out <= '0';
> elsif rising_edge(out_clk_in) then
> t2 <= t1;
> t3 <= t2;
> if ((t3 xor t2)='1') then
> pulse_out <= '1';
> else
> pulse_out <= '0';
> end if;
> end if;
> end process;
>
> I had forgotten about the use of the xor gate - it is explained a bit
> here too:http://www.chipdesignmag.com/print.php?articleId=32?issueId=5
> The loopback of t2 between the two domains seems to avoid the issue of
> reading the same variable at different times on an asynchronous clock.
> As long as the second process is not replicated for some reason (which
> could cause t1 to have different values in each replication), this
> would seem to work fine.
> If out_clk_in is fast, an additional register (e.g. t4) could be added
> and then do xor between t4 and t3 if it were felt necessary to extend
> the allowable metastability settling time further, but in general this
> version would seem ok if the t2 path length is short to the xor gate.
>
> Any further comments appreciated.
>
> Tom

I think you've got it.  I don't see why you have the inner-most if
statement conditioned on the XOR.  That could be a simple assignment,
if pulse_out <= t3 xor t2;

Keep in mind that putting this in the process creates an extra FF.
This FF is only needed if the clock is fast compared to the settling
time of the FFs.  Peter Alfke has posted here many times that with
current technology the settling time is very short, pretty much a
couple of nano-secs.  So unless you are running over 100 MHz clocks
(or just didn't have any slack time), the extra FF is not needed
giving you one clock less delay.  I can't imagine that you would need
a fourth FF in any event.

Rick

Article: 129576
Subject: Re: sd card slave interface
From: MikeShepherd564@btinternet.com
Date: Thu, 28 Feb 2008 02:48:28 +0000
Links: << >> << T >> << A >>

>Now I want to design a SD card,for special use,I must use fpga to
>implement the interface between host controller and NAND flash,can
>someone give me some advice if it is easy to implement it?And where I
>can get the controller source files for free,3X.

You want to design an SD card???

You want to implement the interface between a host controller and NAND
flash?  Well, that could make sense, if you're designing an SD card.

If you're designing an interface between the host controller and the
NAND flash, why do you need the source files for the controller?
Surely the interface specification is enough?

Maybe you should slow down a little and say carefully what you're
trying to do.

Mike

Article: 129577
Subject: Making changes to custom IP in EDK
From: etorkild@gmail.com
Date: Wed, 27 Feb 2008 19:30:48 -0800 (PST)
Links: << >> << T >> << A >>

I'm using EDK 9.1i. I have created custom IP using "Create or Import
Peripheral", modified the VHDL files, and then imported it into my
project using "Create or Import Peripheral" once more.

If I make changes to the VHDL files associated with my peripheral,
what must I do to get these changes into my project?

Do I need to delete the instance of my peripheral and import it again
from the CIP wizard, or is there another way?

Thanks.

Article: 129578
Subject: Re: Preventing optimization in cross clock domain logic
From: Tom <tom.derham@gmail.com>
Date: Wed, 27 Feb 2008 20:13:57 -0800 (PST)
Links: << >> << T >> << A >>

On Feb 28, 11:42=A0am, rickman <gnu...@gmail.com> wrote:
> I think you've got it. =A0I don't see why you have the inner-most if
> statement conditioned on the XOR. =A0That could be a simple assignment,
> if pulse_out <=3D t3 xor t2;

Good point: pulse_out <=3D t3 xor t2 is the same.

Also, in relation to my last point, I think if you add the attribute:

attribute MAX_FANOUT of t1 : signal is "1";

that would make certain that the second process cannot be replicated.
That may be overkill as it is unlikely the synthesizer would replicate
logic in this case anyway, but I guess you can never be sure.

Many thanks.

-Tom

Article: 129579
Subject: DSP newbie
From: FPGA <FPGA.unknown@gmail.com>
Date: Wed, 27 Feb 2008 20:38:02 -0800 (PST)
Links: << >> << T >> << A >>

I have written a process to generate sin wave as below.

-- sine wave constants
			   amp_sin : real := 10.0;
			   phase_sin : real := 0.0		  -- phase in radians
			   samples_sin : integer := 1000;                   -- number of
samples
			   incr_sin : real := 0.001;		  -- 1/samples
			   period_sin : time := 0.001 ns;	                  -- period of
sine wave/samples

two : process
variable phase_temp,result : real ;
begin
	phase_temp := phase_sin; --phase_sin;
	l1 : for i in 1 to samples_sin loop --number_of_samples loop

		sine_real <= ((amp_sin*sin(phase_temp)));
		phase_temp := phase_temp + incr_sin;
		wait for period_sin;
	end loop l1;
end process two;

The problem I am facing is, I get sine wave for some values and for
some I just get triangulr wave. Is there any limitation to the sin
function in math_real. Should I be able to generate any type of
frequencies with this function. Please help

Article: 129580
Subject: DSP newbie
From: FPGA <FPGA.unknown@gmail.com>
Date: Wed, 27 Feb 2008 20:38:59 -0800 (PST)
Links: << >> << T >> << A >>

I have written a process to generate sin wave as below.

-- sine wave constants
                           amp_sin : real := 10.0;
                           phase_sin : real := 0.0                --
phase in radians
                           samples_sin : integer :=
1000;                   -- number of
samples
                           incr_sin : real := 0.001;              -- 1/
samples
                           period_sin : time := 0.001
ns;                         -- period of
sine wave/samples


two : process
variable phase_temp,result : real ;
begin
        phase_temp := phase_sin; --phase_sin;
        l1 : for i in 1 to samples_sin loop --number_of_samples loop


                sine_real <= ((amp_sin*sin(phase_temp)));
                phase_temp := phase_temp + incr_sin;
                wait for period_sin;
        end loop l1;
end process two;


The problem I am facing is, I get sine wave for some values and for
some I just get triangulr wave. Is there any limitation to the sin
function in math_real. Should I be able to generate any type of
frequencies with this function. Please help

Article: 129581
Subject: Re: DSP newbie
From: FPGA <FPGA.unknown@gmail.com>
Date: Wed, 27 Feb 2008 20:50:09 -0800 (PST)
Links: << >> << T >> << A >>

On Feb 27, 11:38=A0pm, FPGA <FPGA.unkn...@gmail.com> wrote:
> I have written a process to generate sin wave as below.
>
> -- sine wave constants
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0amp_sin : real :=3D=
 10.0;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0phase_sin : real :=
=3D 0.0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0--
> phase in radians
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0samples_sin : integ=
er :=3D
> 1000; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 -- number of
> samples
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0incr_sin : real :=
=3D 0.001; =A0 =A0 =A0 =A0 =A0 =A0 =A0-- 1/
> samples
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0period_sin : time :=
=3D 0.001
> ns; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 -- period of
> sine wave/samples
>
> two : process
> variable phase_temp,result : real ;
> begin
> =A0 =A0 =A0 =A0 phase_temp :=3D phase_sin; --phase_sin;
> =A0 =A0 =A0 =A0 l1 : for i in 1 to samples_sin loop --number_of_samples lo=
op
>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 sine_real <=3D ((amp_sin*sin(phase_temp)))=
;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 phase_temp :=3D phase_temp + incr_sin;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 wait for period_sin;
> =A0 =A0 =A0 =A0 end loop l1;
> end process two;
>
> The problem I am facing is, I get sine wave for some values and for
> some I just get triangulr wave. Is there any limitation to the sin
> function in math_real. Should I be able to generate any type of
> frequencies with this function. Please help

Also, the sine wave does not stop after it takes all the samles, I
keep getting a continous sine wave. Would like to add the option of
generating wave from 0 tp 2pi or 4 pi, etc. I want to make this as
generic as possible

Article: 129582
Subject: Re: Making changes to custom IP in EDK
From: chakra <narashimanc@gmail.com>
Date: Wed, 27 Feb 2008 21:13:04 -0800 (PST)
Links: << >> << T >> << A >>

once you have added the peripheral to the main project in EDK along
with other sub-systems. you can directly edit the vhdl files by right
click on the added peripheral and open source files. save them before
you generate bitstream in EDK

On Feb 27, 10:30=A0pm, etork...@gmail.com wrote:
> I'm using EDK 9.1i. I have created custom IP using "Create or Import
> Peripheral", modified the VHDL files, and then imported it into my
> project using "Create or Import Peripheral" once more.
>
> If I make changes to the VHDL files associated with my peripheral,
> what must I do to get these changes into my project?
>
> Do I need to delete the instance of my peripheral and import it again
> from the CIP wizard, or is there another way?
>
> Thanks.

Article: 129583
Subject: Re: sd card slave interface
From: Antti <Antti.Lukats@googlemail.com>
Date: Wed, 27 Feb 2008 22:05:34 -0800 (PST)
Links: << >> << T >> << A >>

On 28 Feb., 02:13, "bjzhan...@gmail.com" <bjzhan...@gmail.com> wrote:
> Now I want to design a SD card,for special use,I must use fpga to
> implement the interface between host controller and NAND flash,can
> someone give me some advice if it is easy to implement it?And where I
> can get the controller source files for free,3X.

http://www.truedream.org/smile/MyFirstFlashFpgaCert.pdf

if you look there you see an PFGA emulating SD-Card.

but to my knowledge there is NO FREE IP-Core for SD-slave

Antti Lukats

Article: 129584
Subject: Re: Xilinx's microblaze hangs when a timer interrupt occurs after a
From: Remy.thomas.38@gmail.com
Date: Wed, 27 Feb 2008 23:50:10 -0800 (PST)
Links: << >> << T >> << A >>

The Service Pack 2 is already installed and i use the Microblaze
7.00.b

R=E9my

Article: 129585
Subject: DCM Simulation : Input Clock Cycle Jitter
From: moogyd@yahoo.co.uk
Date: Thu, 28 Feb 2008 01:29:47 -0800 (PST)
Links: << >> << T >> << A >>

Hi Group,

Just wondering if anyone has seen this issue. I am simulating a Xilinx
FPGA design (RTL) containging DCMs.
I get the following warning

Warning : Input Clock Cycle Jitter on on instance * exceeds 0.3 ns
Previous CLKIN Period =  0 ns Current CLKIN Period =  13.33333 ns

On the face of it, the meaning of this warning should be clear *but*
there is definitely no jitter on this input clock. It is driven
directly from a testbench. i.e. The warning is completely wrong.

I am using cadence ncsim (mixed VHDL/Verilog). This DCM model is VHDL.

Has anyone seen false messages like this? Did you find a workoround or
good explanation.

Thanks,

Steven

Article: 129586
Subject: Re: DSP newbie
From: "RCIngham" <robert.ingham@gmail.com>
Date: Thu, 28 Feb 2008 04:00:01 -0600
Links: << >> << T >> << A >>

>On Feb 27, 11:38=A0pm, FPGA <FPGA.unkn...@gmail.com> wrote:
>> I have written a process to generate sin wave as below.
>>
>> -- sine wave constants
>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0amp_sin : real
:=3D=
> 10.0;
>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0phase_sin : real
:=
>=3D 0.0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0--
>> phase in radians
>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0samples_sin :
integ=
>er :=3D
>> 1000; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 -- number of
>> samples
>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0incr_sin : real
:=
>=3D 0.001; =A0 =A0 =A0 =A0 =A0 =A0 =A0-- 1/
>> samples
>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0period_sin :
time :=
>=3D 0.001
>> ns; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 -- period of
>> sine wave/samples
>>
>> two : process
>> variable phase_temp,result : real ;
>> begin
>> =A0 =A0 =A0 =A0 phase_temp :=3D phase_sin; --phase_sin;
>> =A0 =A0 =A0 =A0 l1 : for i in 1 to samples_sin loop --number_of_samples
lo=
>op
>>
>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 sine_real <=3D
((amp_sin*sin(phase_temp)))=
>;
>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 phase_temp :=3D phase_temp + incr_sin;
>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 wait for period_sin;
>> =A0 =A0 =A0 =A0 end loop l1;
>> end process two;
>>
>> The problem I am facing is, I get sine wave for some values and for
>> some I just get triangulr wave. Is there any limitation to the sin
>> function in math_real. Should I be able to generate any type of
>> frequencies with this function. Please help
>
>Also, the sine wave does not stop after it takes all the samles, I
>keep getting a continous sine wave. Would like to add the option of
>generating wave from 0 tp 2pi or 4 pi, etc. I want to make this as
>generic as possible
>
To get it to stop after 1 run through the "l1" loop, add "wait;" between
the "end loop" and "end process".

Regarding triangular waves, that could happen be when you do not have
enough samples per period. Does "nyquist theorem" mean anything to you?

Article: 129587
Subject: Re: DSP newbie
From: Tricky <Trickyhead@gmail.com>
Date: Thu, 28 Feb 2008 02:19:40 -0800 (PST)
Links: << >> << T >> << A >>

On Feb 28, 4:50 am, FPGA <FPGA.unkn...@gmail.com> wrote:
> On Feb 27, 11:38 pm, FPGA <FPGA.unkn...@gmail.com> wrote:
>
>
>
> > I have written a process to generate sin wave as below.
>
> > -- sine wave constants
> >                            amp_sin : real := 10.0;
> >                            phase_sin : real := 0.0                --
> > phase in radians
> >                            samples_sin : integer :=
> > 1000;                   -- number of
> > samples
> >                            incr_sin : real := 0.001;              -- 1/
> > samples
> >                            period_sin : time := 0.001
> > ns;                         -- period of
> > sine wave/samples
>
> > two : process
> > variable phase_temp,result : real ;
> > begin
> >         phase_temp := phase_sin; --phase_sin;
> >         l1 : for i in 1 to samples_sin loop --number_of_samples loop
>
> >                 sine_real <= ((amp_sin*sin(phase_temp)));
> >                 phase_temp := phase_temp + incr_sin;
> >                 wait for period_sin;
> >         end loop l1;
> > end process two;
>
> > The problem I am facing is, I get sine wave for some values and for
> > some I just get triangulr wave. Is there any limitation to the sin
> > function in math_real. Should I be able to generate any type of
> > frequencies with this function. Please help
>
> Also, the sine wave does not stop after it takes all the samles, I
> keep getting a continous sine wave. Would like to add the option of
> generating wave from 0 tp 2pi or 4 pi, etc. I want to make this as
> generic as possible

It's repeating because you havent told the process to wait when it
finishes the loop. Currently the loop finishs, and then the process
restarts and does the whole loop again, and this will repeat for ever.
To stop this simply put "wait;" at the end of the process.

Article: 129588
Subject: Re: DCM Simulation : Input Clock Cycle Jitter
From: "Symon" <symon_brewer@hotmail.com>
Date: Thu, 28 Feb 2008 10:57:01 -0000
Links: << >> << T >> << A >>

moogyd@yahoo.co.uk wrote:
> Hi Group,
>
> Just wondering if anyone has seen this issue. I am simulating a Xilinx
> FPGA design (RTL) containging DCMs.
> I get the following warning
>
> Warning : Input Clock Cycle Jitter on on instance * exceeds 0.3 ns
> Previous CLKIN Period =  0 ns Current CLKIN Period =  13.33333 ns
>
> On the face of it, the meaning of this warning should be clear *but*
> there is definitely no jitter on this input clock. It is driven
> directly from a testbench. i.e. The warning is completely wrong.
>
> I am using cadence ncsim (mixed VHDL/Verilog). This DCM model is VHDL.
>
> Has anyone seen false messages like this? Did you find a workoround or
> good explanation.
>
> Thanks,
>
> Steven

Hi Steven,
What's the time resolution of your simulation?
HTH., Syms.

Article: 129589
Subject: Re: How to connect FPGA to a ASIC Board?
From: mk <kal*@dspia.*comdelete>
Date: Thu, 28 Feb 2008 11:27:30 GMT
Links: << >> << T >> << A >>

On Wed, 27 Feb 2008 11:18:25 +0000, Jonathan Bromley
<jonathan.bromley@MYCOMPANY.com> wrote:

>On Wed, 27 Feb 2008 02:08:34 -0800 (PST), Antti wrote:
>
>>usually a tool called "soldering iron" must be used.
>
>LOL.
>
>Antti, that's unfair.... In the interests of public 
>safety, you should at least have explained which 
>end of it he should pick up.

The problem with soldering irons is that when they're hot and falling
towards the carpet under the table, it's difficult to judge which side
one actually grabs when one catches it. "Yes, I got it" is quickly
followed by "ahhh, I got it".

Article: 129590
Subject: Re: DCM Simulation : Input Clock Cycle Jitter
From: job@amontec.com
Date: Thu, 28 Feb 2008 04:37:27 -0800 (PST)
Links: << >> << T >> << A >>

On Feb 28, 10:29 am, moo...@yahoo.co.uk wrote:
> Hi Group,
>
> Just wondering if anyone has seen this issue. I am simulating a Xilinx
> FPGA design (RTL) containging DCMs.
> I get the following warning
>
> Warning : Input Clock Cycle Jitter on on instance * exceeds 0.3 ns
> Previous CLKIN Period =  0 ns Current CLKIN Period =  13.33333 ns
>
> On the face of it, the meaning of this warning should be clear *but*
> there is definitely no jitter on this input clock. It is driven
> directly from a testbench. i.e. The warning is completely wrong.
>
> I am using cadence ncsim (mixed VHDL/Verilog). This DCM model is VHDL.
>
> Has anyone seen false messages like this? Did you find a workoround or
> good explanation.
>
> Thanks,
>
> Steven

set the resolution of your simulator to 100ps.

Laurent
 http//:www.amontec.com

Article: 129591
Subject: Re: Making changes to custom IP in EDK
From: Jeff Cunningham <jcc@sover.net>
Date: Thu, 28 Feb 2008 07:57:43 -0500
Links: << >> << T >> << A >>

etorkild@gmail.com wrote:

> If I make changes to the VHDL files associated with my peripheral,
> what must I do to get these changes into my project?

I have found under 9.1 that editing the VHDL files down in pcores is not 
always enough to get the changes in. To be sure to get the changes 
compiled, I go to project -> clean all generated files, and then quit 
the project and delete the "__xps" directory.

-Jeff

Article: 129592
Subject: Re: Making changes to custom IP in EDK
From: Guy Eschemann <Guy.Eschemann@gmail.com>
Date: Thu, 28 Feb 2008 04:59:19 -0800 (PST)
Links: << >> << T >> << A >>

No, you do not need to delete the instance of your peripheral. Just
delete the generated netlists using hardware/clean netlist or hardware/
clean hardware, and re-build the project using generate netlist/
hardware.
Hope this helps,
Guy.

Article: 129593
Subject: Re: DSP newbie
From: FPGA <FPGA.unknown@gmail.com>
Date: Thu, 28 Feb 2008 05:53:04 -0800 (PST)
Links: << >> << T >> << A >>

On Feb 28, 5:19=A0am, Tricky <Trickyh...@gmail.com> wrote:
> On Feb 28, 4:50 am, FPGA <FPGA.unkn...@gmail.com> wrote:
>
>
>
>
>
> > On Feb 27, 11:38 pm, FPGA <FPGA.unkn...@gmail.com> wrote:
>
> > > I have written a process to generate sin wave as below.
>
> > > -- sine wave constants
> > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0amp_sin : real =
:=3D 10.0;
> > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0phase_sin : rea=
l :=3D 0.0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0--
> > > phase in radians
> > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0samples_sin : i=
nteger :=3D
> > > 1000; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 -- number of
> > > samples
> > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0incr_sin : real=
 :=3D 0.001; =A0 =A0 =A0 =A0 =A0 =A0 =A0-- 1/
> > > samples
> > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0period_sin : ti=
me :=3D 0.001
> > > ns; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 -- period of
> > > sine wave/samples
>
> > > two : process
> > > variable phase_temp,result : real ;
> > > begin
> > > =A0 =A0 =A0 =A0 phase_temp :=3D phase_sin; --phase_sin;
> > > =A0 =A0 =A0 =A0 l1 : for i in 1 to samples_sin loop --number_of_sample=
s loop
>
> > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 sine_real <=3D ((amp_sin*sin(phase_tem=
p)));
> > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 phase_temp :=3D phase_temp + incr_sin;=

> > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 wait for period_sin;
> > > =A0 =A0 =A0 =A0 end loop l1;
> > > end process two;
>
> > > The problem I am facing is, I get sine wave for some values and for
> > > some I just get triangulr wave. Is there any limitation to the sin
> > > function in math_real. Should I be able to generate any type of
> > > frequencies with this function. Please help
>
> > Also, the sine wave does not stop after it takes all the samles, I
> > keep getting a continous sine wave. Would like to add the option of
> > generating wave from 0 tp 2pi or 4 pi, etc. I want to make this as
> > generic as possible
>
> It's repeating because you havent told the process to wait when it
> finishes the loop. Currently the loop finishs, and then the process
> restarts and does the whole loop again, and this will repeat for ever.
> To stop this simply put "wait;" at the end of the process.- Hide quoted te=
xt -
>
> - Show quoted text -

I am required to design this using the CORDIC algorithm.

Article: 129594
Subject: Software for FPGA-based PC scope
From: Vagant <vladimir.v.korostelev@rambler.ru>
Date: Thu, 28 Feb 2008 06:07:13 -0800 (PST)
Links: << >> << T >> << A >>

Hello,

Although I am a newbie in FPGA design and have experience only with
some simple designs so far, I am thinking of some more ambitious
project and want to design a FPGA-based PC scope working in Windows
XP.
Let's assume that I know how to program (in VHDL) and implement this
on FPGA. Then I will need to write software for this and I need advice
about it. What software such project will require and what development
tools I will need to write such software? May I write this in C++
Builder or Visual Basic or I will need some lower level programming?
So, my question is very general and I would appreciate your advice
which I need to start up with this since on my own I just feel stuck
about software for my project.

Article: 129595
Subject: Re: CPLD Pad File
From: akshat <mailtoakshat@gmail.com>
Date: Thu, 28 Feb 2008 07:01:34 -0800 (PST)
Links: << >> << T >> << A >>

On Jan 18, 7:33=A0pm, Gabor <ga...@alacron.com> wrote:
> On Jan 18, 3:14 am, akshat <mailtoaks...@gmail.com> wrote:
>
> > I am trying to generate a CPLD pad file using a dummy module and ucf.
>
> > Translate process gives the following error:
>
> > ERROR:NgdBuild:605 - logical root block 'test' with type 'test' is
> > unexpanded.
> > =A0 =A0Symbol 'test' is not supported in target 'xbr'.
>
> > Any idea what might be wrong??
>
> Is your top level module written in Verilog? =A0If this is the
> case and all the module contains is the port list, i.e. no
> "code", the tools assume that it is a black box and look for
> an underlying .ngc or EDIF file. =A0Usually to get through
> ngdbuild ("translate") you need to have at least an assign
> statement in the module.

Hey, thanks Gabor.. that exactly was the problem..
Sorted it out..

Article: 129596
Subject: Re: DSP newbie
From: Dave <dhschetz@gmail.com>
Date: Thu, 28 Feb 2008 07:02:51 -0800 (PST)
Links: << >> << T >> << A >>

On Feb 28, 8:53 am, FPGA <FPGA.unkn...@gmail.com> wrote:
> On Feb 28, 5:19 am, Tricky <Trickyh...@gmail.com> wrote:
>
>
>
> > On Feb 28, 4:50 am, FPGA <FPGA.unkn...@gmail.com> wrote:
>
> > > On Feb 27, 11:38 pm, FPGA <FPGA.unkn...@gmail.com> wrote:
>
> > > > I have written a process to generate sin wave as below.
>
> > > > -- sine wave constants
> > > >                            amp_sin : real := 10.0;
> > > >                            phase_sin : real := 0.0                --
> > > > phase in radians
> > > >                            samples_sin : integer :=
> > > > 1000;                   -- number of
> > > > samples
> > > >                            incr_sin : real := 0.001;              -- 1/
> > > > samples
> > > >                            period_sin : time := 0.001
> > > > ns;                         -- period of
> > > > sine wave/samples
>
> > > > two : process
> > > > variable phase_temp,result : real ;
> > > > begin
> > > >         phase_temp := phase_sin; --phase_sin;
> > > >         l1 : for i in 1 to samples_sin loop --number_of_samples loop
>
> > > >                 sine_real <= ((amp_sin*sin(phase_temp)));
> > > >                 phase_temp := phase_temp + incr_sin;
> > > >                 wait for period_sin;
> > > >         end loop l1;
> > > > end process two;
>
> > > > The problem I am facing is, I get sine wave for some values and for
> > > > some I just get triangulr wave. Is there any limitation to the sin
> > > > function in math_real. Should I be able to generate any type of
> > > > frequencies with this function. Please help
>
> > > Also, the sine wave does not stop after it takes all the samles, I
> > > keep getting a continous sine wave. Would like to add the option of
> > > generating wave from 0 tp 2pi or 4 pi, etc. I want to make this as
> > > generic as possible
>
> > It's repeating because you havent told the process to wait when it
> > finishes the loop. Currently the loop finishs, and then the process
> > restarts and does the whole loop again, and this will repeat for ever.
> > To stop this simply put "wait;" at the end of the process.- Hide quoted text -
>
> > - Show quoted text -
>
> I am required to design this using the CORDIC algorithm.

Then why aren't you using the CORDIC algorithm? Google it.

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From: Phil Hays <invalid@dont.spam>
Subject: Re: Software for FPGA-based PC scope
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Vagant wrote:

> Hello,
> 
> Although I am a newbie in FPGA design and have experience only with some
> simple designs so far, I am thinking of some more ambitious project and
> want to design a FPGA-based PC scope working in Windows XP. Let's assume
> that I know how to program (in VHDL) and implement this on FPGA. Then I
> will need to write software for this and I need advice about it. What
> software such project will require and what development tools I will
> need to write such software? May I write this in C++ Builder or Visual
> Basic or I will need some lower level programming? So, my question is
> very general and I would appreciate your advice which I need to start up
> with this since on my own I just feel stuck about software for my
> project.

I'm not sure what you are trying to get out of this. This sounds like
perhaps a bit too ambitious of project. However, this is how I'd look at
this task:

1) Need to get data from analog to digital. Buy an 8 bit ADC. Or if much
slower or somewhat lower resolution is acceptable, design your own. Think
about protecting the input against too much voltage.

2) Need to handle triggering, timebases, buffering, and such. FPGA.

3) Need to send data to PC. Buy an Ethernet MAC and PHY. Send the commands
to the scope as UDP packets.

http://en.wikipedia.org/wiki/User_Datagram_Protocol

3) Use any programming language that can send and receive packets from
Ethernet (python, C, C++, Tcl, perl, ...). Write a display and control
application.

To debug the software for this, you might want to write a "scope
simulator" that runs on a second PC. This would allow you to develop the
software independently of having working hardware. Capture packets into a
form that can be turned into simulation vectors for your FPGA design, and
use these to debug your FPGA design.

This might be a much bigger project that you think it is. If nothing else,
you will learn a lot by trying. Good luck and have fun.


-- 
Phil Hays

Article: 129597
Subject: Re: DSP newbie
From: FPGA <FPGA.unknown@gmail.com>
Date: Thu, 28 Feb 2008 07:57:43 -0800 (PST)
Links: << >> << T >> << A >>

On Feb 28, 8:53=A0am, FPGA <FPGA.unkn...@gmail.com> wrote:
> On Feb 28, 5:19=A0am, Tricky <Trickyh...@gmail.com> wrote:
>
>
>
>
>
> > On Feb 28, 4:50 am, FPGA <FPGA.unkn...@gmail.com> wrote:
>
> > > On Feb 27, 11:38 pm, FPGA <FPGA.unkn...@gmail.com> wrote:
>
> > > > I have written a process to generate sin wave as below.
>
> > > > -- sine wave constants
> > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0amp_sin : rea=
l :=3D 10.0;
> > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0phase_sin : r=
eal :=3D 0.0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0--
> > > > phase in radians
> > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0samples_sin :=
 integer :=3D
> > > > 1000; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 -- number of
> > > > samples
> > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0incr_sin : re=
al :=3D 0.001; =A0 =A0 =A0 =A0 =A0 =A0 =A0-- 1/
> > > > samples
> > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0period_sin : =
time :=3D 0.001
> > > > ns; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 -- period of
> > > > sine wave/samples
>
> > > > two : process
> > > > variable phase_temp,result : real ;
> > > > begin
> > > > =A0 =A0 =A0 =A0 phase_temp :=3D phase_sin; --phase_sin;
> > > > =A0 =A0 =A0 =A0 l1 : for i in 1 to samples_sin loop --number_of_samp=
les loop
>
> > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 sine_real <=3D ((amp_sin*sin(phase_t=
emp)));
> > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 phase_temp :=3D phase_temp + incr_si=
n;
> > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 wait for period_sin;
> > > > =A0 =A0 =A0 =A0 end loop l1;
> > > > end process two;
>
> > > > The problem I am facing is, I get sine wave for some values and for
> > > > some I just get triangulr wave. Is there any limitation to the sin
> > > > function in math_real. Should I be able to generate any type of
> > > > frequencies with this function. Please help
>
> > > Also, the sine wave does not stop after it takes all the samles, I
> > > keep getting a continous sine wave. Would like to add the option of
> > > generating wave from 0 tp 2pi or 4 pi, etc. I want to make this as
> > > generic as possible
>
> > It's repeating because you havent told the process to wait when it
> > finishes the loop. Currently the loop finishs, and then the process
> > restarts and does the whole loop again, and this will repeat for ever.
> > To stop this simply put "wait;" at the end of the process.- Hide quoted =
text -
>
> > - Show quoted text -
>
> I am required to design this using the CORDIC algorithm.- Hide quoted text=
 -
>
> - Show quoted text -

I was able to add the wait statement and the problem was solved. I
modified some of the things and not I am able to get waveforms at
different frequencies. FYI,
incr_phase_sin : real :=3D (2.0*MATH_PI)/(real(samples_sin));	  -- 2pi/
samples per period
incr_time_sin : time :=3D time(period_sin/samples_sin);	              --
period/samples per period

Article: 129598
Subject: Re: Why must a V4 be configured within 10 minutes of power up?
From: austin <austin@xilinx.com>
Date: Thu, 28 Feb 2008 08:05:02 -0800
Links: << >> << T >> << A >>

Mikhail,

If this is done once: absolutely no problem.

Even if done a 100 times: no problem.

The concern is that you accumulate more than a few hundred hours at
elevated temperature in a static (non-switching) condition.

And, as I said before, we were unable to actually see anything happen to
the DCM.

MGTs are also affected by NBTI powered on but left unconfigured (on the
V4 FX), and there, you will see variations after hundreds of hours of
static "stress."  But, again, it doesn't seem possible to accumulate
such a stress, even for a MGT in your case.

Austin

MM wrote:
> Austin,
> 
> Our freshly manufactured cards go through a test procedure where they are 
> first powered up and all the voltages are manually measured, and then a 
> boundary scan test is run. All of this takes substantially more than 10 
> minutes. Do I understand correctly that it is not really an issue? Or should 
> I enforce some strict rules at the company preventing anyone from having a 
> card powered up for more than 5 min at a time unless it has been configured?
> 
> 
> Thanks,
> /Mikhail 
> 
>

Article: 129599
Subject: Re: Picoblaze enhencement and assembler
From: nico@puntnl.niks (Nico Coesel)
Date: Thu, 28 Feb 2008 18:08:27 GMT
Links: << >> << T >> << A >>

"Sylvain Munaut <SomeOne@SomeDomain.com>" <246tnt@gmail.com> wrote:

>On Feb 27, 9:15 pm, n...@puntnl.niks (Nico Coesel) wrote:
>> "Sylvain Munaut <Some...@SomeDomain.com>" <246...@gmail.com> wrote:
>>
>>
>>
>> >I'm not that interested in HLL because when I uses theses. But a macro
>> >preprocessor would be nice :)
>>
>> You can use plain old cpp for that purpose. A few months ago I wrote a
>> PLC compiler thingy. I used cpp as a preprocessor for it.
>
>Mmm, I hadn't tought of that.
>That's a nice easy way to get a well known syntax.
>
>However for an assembler it's nice to have more 'advanced' things. I'm
>not an expert in the C preprocessor but making a macro that would
>expand :
>
>STACK_PUSH(s0, s1, s2, s3)
>
>into
>
>store s0, (sp)0
>store s1, (sp)1
>store s2, (sp)2
>store s3, (sp)3
>add sp, 4
>
>Seems kinda hard ...

You shouldn't push the limits too far... Your example smells more like
assembler extensions than macro's.



-- 
Programmeren in Almere?
E-mail naar nico@nctdevpuntnl (punt=.)

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