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On Feb 26, 9:47 am, Andrew Greensted <ajg...@ohm.york.ac.uk> wrote: > Sylvain Munaut <Some...@SomeDomain.com> wrote: > > Hi, > > > I wasn't very satisfied with the available assembler, so a few month > > ago I wrote a new compiler for the Picobaze during my spare > > weekends ... > > Hi Sylvain, > > Nothing to add but encouragement really. The software offerings for > picoblaze are limited, especially in the non-windows world. Both picoasm > and kpicosim are very good, but their development seems to have stopped. Yes they did a great job and I used those for a some time. But since they respected the Xilinx 'standard' assembly format, they were limited ... I choose to break compatibility so that I could extend easily. But even without the compatibility, it's pretty easy to convert old software. Mostly a few subsitute with regexp and adding a .text at the start and that should do it :) > If you can get a polished version of your assembler finished, it sounds > like it would be a great tool. Thanks. I'll try to polish things up a little and maybe write some documentation and so forth. But I probably won't do a lot of work on it since I changed job and this new one is not related to fpga (nor hw dev) in any way ... SylvainArticle: 129551
I can't say that I have thoroughly analyzed your code, but I think I
can suggest some better code. It is only slightly different from
yours, but I am sure it does not have any problems as it was given to
me some years ago and has worked for myself and everyone else I know
who has used it.
ClkDtctReg: process (RT, SysReset) begin
if (SysReset ='1') then
RTClkDetect <= FALSE;
else -- Add an IF (strobe) here for your case
RTClkDetect <= not RTClkDetSync;
end if;
end process ClkDtctReg;
ClkSyncReg : process (GenClk, SysReset) begin
if (SysReset = '1') then
BackupClk <= '0';
ClkSel <= '0';
elsif (rising_edge(GenClk)) then
BackupClk <= not BackupClk; -- 24.576 MHz in, 12.288 MHz out
RTClkDetSync <= RTClkDetect;
RTClkDetSync_D <= RTClkDetSync;
if (CTPClkSel = '1') then
ClkSel <= '1'; -- board clock selected
elsif (RTClkDetSync xor RTClkDetSync_D) -- did we see an RT clock?
ClkSel <= '0'; -- RT clock selected
else
ClkSel <= '1'; -- clock failure detected, wait for board reset
end if;
end if;
end process ClkSyncReg;
This is code I am currently writing and have not tested, plus it is
for a slightly different application than yours. So there may be
typos.
In the second clock domain the expression "RTClkDetSync xor
RTClkDetSync_D" generates a pulse in the second clock domain in
response to a pulse in the first clock domain. This can be registered
or used directly if the clock is slow enough (adequate slack in the
path) to resolve the metastability. The basic circuit is one FF on
the first clock side, two more on the second clock side and the loop
is just between the one on the first clock side and the first FF on
the second clock side with a single inverter in the return path.
I think a schematic is simpler to understand, but ascii art doesn't
convey well...
Rick
Tom wrote:
> In a situation where it is necessary to cross between two clock
> domains within an FPGA, I might use logic that produces an output
> toggle (toggle_out) on the 2nd clock in response to a single-cycle
> pulse (pulse_in) on the 1st clock, using two processes and double
> buffering to mitigate metastability. In VHDL, it might look like this:
>
> signal t1, t2, toggle : std_logic;
>
> process(first_clk)
> begin
> if rising_edge(first_clk)
> if pulse_in = '1' then -- detect pulse on first_clk
> t1 <= not(t1); -- toggle signal t1 (on first_clk)
> end if;
> end if;
> end process;
>
> process(second_clk)
> variable t1_old, t2_old : std_logic;
> begin
> if rising_edge(second_clk)
> if t1 = not(t1_old) then -- detect toggle on t1 (domain cross here)
> t2 <= not(t2); -- then toggle t2 (on second_clk)
> end if;
> if t2 = not(t2_old) then -- detect toggle of t2 (double buffer)
> toggle <= not(toggle); -- toggle pulse
> end if;
> t1_old := t1;
> t2_old := t2;
> end if;
> end process;
> toggle_out <= toggle;
>
> The reset logic has been left out for clarity. In the second process,
> t1 is compared to its previous value (t1_old) to see if it has
> toggled. However, since the lines:
> a) if t1 = not(t1_old)
> b) t1_old := t1
> occur sequentially, and t1 is asynchronous to second_clk (since the
> domain crossing occurs here), t1 could change between (a) and (b).
> I could insert an additional variable at the start of the process to
> register t1 so that it is only read once, but even that could be
> removed by the synthesizer during optimization. Alternatively, the
> synthesizer could decide to replicate logic anyway.
> Is there some way to tell the synthesizer (I use Xilinx XST) not to do
> any optimization or replication just on this module, or some other way
> to prevent this potential problem?
>
> Many thanks
>
> Tom
Article: 129552Support is scheduled for 10.1 according to this Answer Record: http://www.xilinx.com/support/answers/25377.htm Bryan Antti wrote: > On 27 Feb., 13:13, kislo <kisl...@student.sdu.dk> wrote: > > Will it be possible to use indirect programming of an SPI flash for > > Spartan 3E in future releases of ISE ? Im using 9.2, and if i choose > > "Enable programming of SPI flash device attached to this FPGA" in the > > assign new configuration file i get a message : "The device selected > > does not support the BPI or SPI external programming option" > > So does anyone know if this feature will be available to Spartan3E in > > the future? > > I think not from Xilinx > I use my own tools for S3e > > AnttiArticle: 129553
On 27 Feb., 19:32, Bryan <bryan.fletc...@avnet.com> wrote: > Support is scheduled for 10.1 according to this Answer Record:http://www.xilinx.com/support/answers/25377.htm > > Bryan > > Antti wrote: > > On 27 Feb., 13:13, kislo <kisl...@student.sdu.dk> wrote: > > > Will it be possible to use indirect programming of an SPI flash for > > > Spartan 3E in future releases of ISE ? Im using 9.2, and if i choose > > > "Enable programming of SPI flash device attached to this FPGA" in the > > > assign new configuration file i get a message : "The device selected > > > does not support the BPI or SPI external programming option" > > > So does anyone know if this feature will be available to Spartan3E in > > > the future? > > > I think not from Xilinx > > I use my own tools for S3e > > > Antti so we need 10.1 positive surprise for change if the s3e indirect programming is added in 10.1 and not in SP4 AnttiArticle: 129554
I was looking at the Virtex4 specs and notices a spec (Tconfig) that says you must configure within 10 minutes of applying Vccint. I don't plan on violating this spec, but it struck me as odd. Just out of curiosity, what happens if you violate this spec? Can you damage the part if you leave power on for hours but don't configure it? -JeffArticle: 129555
"Sylvain Munaut <SomeOne@SomeDomain.com>" <246tnt@gmail.com> wrote: > >I'm not that interested in HLL because when I uses theses. But a macro >preprocessor would be nice :) You can use plain old cpp for that purpose. A few months ago I wrote a PLC compiler thingy. I used cpp as a preprocessor for it. -- Programmeren in Almere? E-mail naar nico@nctdevpuntnl (punt=.)Article: 129556
Does Answer Record #29784 (http://www.xilinx.com/support/answers/ 29784.htm) sound like the problem you're having? If so, looks like updating EDK to Service Pack 2 should solve the problem. -JakeArticle: 129557
Jeff Cunningham wrote: > I was looking at the Virtex4 specs and notices a spec (Tconfig) that > says you must configure within 10 minutes of applying Vccint. I don't > plan on violating this spec, but it struck me as odd. Just out of > curiosity, what happens if you violate this spec? Can you damage the > part if you leave power on for hours but don't configure it? > > -Jeff Hi Jeff, search :- nbti site:xilinx.com HTH., Syms.Article: 129558
On Feb 27, 9:15 pm, n...@puntnl.niks (Nico Coesel) wrote: > "Sylvain Munaut <Some...@SomeDomain.com>" <246...@gmail.com> wrote: > > > > >I'm not that interested in HLL because when I uses theses. But a macro > >preprocessor would be nice :) > > You can use plain old cpp for that purpose. A few months ago I wrote a > PLC compiler thingy. I used cpp as a preprocessor for it. Mmm, I hadn't tought of that. That's a nice easy way to get a well known syntax. However for an assembler it's nice to have more 'advanced' things. I'm not an expert in the C preprocessor but making a macro that would expand : STACK_PUSH(s0, s1, s2, s3) into store s0, (sp)0 store s1, (sp)1 store s2, (sp)2 store s3, (sp)3 add sp, 4 Seems kinda hard ... SylvainArticle: 129559
Hi everybody,
I'm trying to partially reconfigure my device (XC2VP30 on ML310 board)
through ICAP. I have my ICAP attached to OPB which is attached to
Microblaze. In bitgen.ut file I have set the value of mode pins
(M2M1M0) to 1 (PULLUP). So it is not set on 101 which is JTAG mode. As
well the base address and high address of my HWICAP is 0x42000000 and
0x42000fff as mentioned in the datasheet of HWICAP. Initially my OPB
clock frequency was 100 MHz but now I have reduced it to 25MHz. The
system contains a timer, a SysAce, a hwicap, a uartlite and an opb-mdm
(for debugging) all attached to the opb. The microblaze has some local
memory too. I'm also using EDK, ISE 8.2. That's the whole setting
about my system. Now here is the problem:
I just need to measure the delay of reconfiguration through ICAP. The
following is a very simple C code I have implemented to read a frame
and print the content on the screen. Later I want to write something
to a frame and again read it back just to make sure that in fact it
changed the reconfiguration. Firstly I initialize the ICAP module and
then invoke XHwIcap_DeviceReadFrame() and then I read the
configuration through XHwIcap_StorageBufferRead().
XHwIcap my_icap;
XStatus icap_stat;
icap_stat = XHwIcap_Initialize(&my_icap,
XPAR_OPB_HWICAP_0_DEVICE_ID, XHI_READ_DEVICEID_FROM_ICAP);
if(icap_stat != XST_SUCCESS)
print("\n There is something wrong in initializing the ICAP!!
\n");
Xuint32 frame_content;
icap_stat = XHwIcap_DeviceReadFrame(&my_icap, XHI_FAR_CLB_BLOCK,
32, 32);
if(icap_stat != XST_SUCCESS)
print("\n There is something working in reading a frame with col
= 5 and lut_bit = 3!!!!!\n");
for(i = 0; i < my_icap.WordsPerFrame; i++)
{
print("word number");
putnum(i+1);
print(" is equal to: ");
frame_content = XHwIcap_StorageBufferRead(&my_icap, i);
putnum(frame_content);
putchar('\n');
}
The problem is when I read back the frame except for the first 7 words
everything is 0, no matter what frame it is.
I have carefully studied ICAP's driver's functions and their
implementation. I know that the driver writes the first 7 words in the
storage buffer but even the 7 words that I read from the storage
buffer is not the same as the ones that the driver's deviceRead
function writes to the storage buffer. So I don't get what the problem
is.
The seven words that I read are as follows:
30008001
0000000d
ffffffff
ffffffff
30002001
00404000
2800619c
However for example based on the driver's implementation the first
word should be 0xFFFFFFFF which is an XHI_DUMMY_PACKET.
So as I mentioned, my problem is I can't basically read a frame of
configuration correctly. Do you have any idea where I'm doing wrong or
what the problem is?
As well I have some doubts and questions. Firstly why should we first
read a frame, modify it and then write it back to the configuration?
Can't we just write something to the device? I haven't still worked
with difference-based reconfiguration and it might have something to
do with that. But if I just want to write configuration to one frame
that doesn't implement any other part of any other circuit, can't I
just write something to that frame without first reading it and
modifying it?
The second question that I have is about the storage buffer of the
HWICAP module. Firstly I thought that I have to set an opb_bram so
that HWICAP can use it. However later through studying the driver I
realized that the base address for HWICAP is the same as storage
buffer (which is the BRAM) so I concluded that when I use a HWICAP I
implicitly assign a BRAM to it. Is this so? If not please let me know.
The third question is the clock frequency that ICAP operates! I have
read somewhere that the highest is 66MHz. Is it correct or we can set
the clock higher than that?
This message became very long, but I really appreciate it if you could
kindly help me out with it. I have read many of the previous posts
about ICAP but couldn't find enough information to solve my problems.
So perhaps this post can be a complement to them.
Thanks a lot beforehand,
Amir
Article: 129560
"bart" <bart.borosky@latticesemi.com> wrote in message
news:89ebc936-6304-4246-9fa3-a2d88406473b@e23g2000prf.googlegroups.com...
> Lattice is holding a webcast today, "Interfacing High Sample Rate ADCs
> to FPGAs." The presenter will be Shyam Chandra, from our mixed-signal
> marketing group.
>
> If you're interested, the event takes place live at 11am Pacific,
> 18:00 GMT. In addition, you will be able to view this webcast archive
> on-demand, at your convenience, within 24 hours after the live event
> takes place.
>
> You can register by clicking:
> http://www.latticesemi.com/corporate/webcasts/interfacinghighsamplerate.cfm
>
> Bart Borosky, Lattice
Oh Gosh, you hire another Indian again, this is a real proof of why America
is losing ground. I have many years of experience in programming and in all
sort of hardware's....Damn it!
...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et
|
| Analog/Mixed-Signal ASICK's and Discrete Systems | manus |
| Phoenix, Arizona Voice:(480)460-2350 | |
| E-mail Address at Website Fax:(480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |
America: Land of the Freedom Abusers, Because of the Bastards.
Article: 129561I am writing a testbench and one of the clock is a "gated clock" - meaning clock is clocking every time gate goes active. so say that gate pulses at time T. Then clock goes active at T+ 10uS for 200uS. Clock frq. is 25MHz. (clock is inactive after T+210uS) again Gate pulses at T+450uS and clock goes active at T+460uS for 200uS and clock is inactive after T+660uS. I am not sure how to implement this in Quicksim. can someone give me an example please? I don't want to define high and low for each time. I would think there must be a smart way of implementing this. I am not even sure how will I write this in Modelsim?? any suggestions? Thanks in advanceArticle: 129562
On Wed, 27 Feb 2008 13:11:46 -0800 (PST), martstev@gmail.com wrote:
>I am writing a testbench and one of the clock is a "gated clock" -
>meaning clock is clocking every time gate goes active. so say that
>gate pulses at time T. Then clock goes active at T+ 10uS for 200uS.
>Clock frq. is 25MHz. (clock is inactive after T+210uS) again Gate
>pulses at T+450uS and clock goes active at T+460uS for 200uS and clock
>is inactive after T+660uS.
>
>I am not sure how to implement this in Quicksim. can someone give me
>an example please? I don't want to define high and low for each time.
>I would think there must be a smart way of implementing this.
>
>I am not even sure how will I write this in Modelsim??
AAAAAARGH... PLEASE, PLEASE think about the READER when
you're writing something that is intended to convey technical
information.
You speak of a "gate" signal - is it an input to your system?
an output? Why does it pulse - is it some external signal
that's outside your control, or are you trying to generate
this "gate" pulse? What do you mean by "pulse"? Is it
the rising edge of this signal that triggers your 200us of
clock activity? Or do you expect the gate pulse to remain
true for the duration of the 200us clock stream?
And then what about the clock... is the 25MHz clock an input
from an external oscillator, or are you trying to generate
it within your design? What do you mean by "clock goes
active" - is this the time of the first rising edge you
are talking about?
And finally, are you implementing in VHDL? Verilog?
The VHDL code below does something like what I *guess* you want...
but I cannot possibly tell from your description. If people
insist on technical writing as confused and thoughtless as
this, it's little wonder that we engineers have a reputation
for being a bunch of incomprehensible geeks with no
interaction skills.
--- Model a 25MHz clock generator that runs for 200us after
--- each rising edge on signal "gate", with the first rising
--- edge of the clock occurring exactly 10us after the rising
--- edge on "gate"
---
process
constant clock_period: time := 40 ns; --- 25 MHz
constant start_delay : time := 10 us;
constant active_time : time := 200 us;
--- How many complete clock pulses will I generate?
constant clock_cycles : integer := active_time / clock_period;
begin
clock <= '0';
wait until rising_edge(gate);
wait for start_delay;
for cycle_count from 1 to clock_cycles loop
clock <= '1', '0' after clock_period/2;
wait for clock_period;
end loop;
--- and then the process loops around ready for next time
end process;
I'm not familiar with QuickSim - does it have its own
programming language, or does it use VHDL or Verilog?
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Article: 129563Dave, I actually realized that -target mdm was not a problem. Because later on when I did the same thing with -target mdm set it worked again. Previously I used to export my design to ISE and synthesize and place and route it there and then generate the ace file through iMPACT. However this time (that worked) I actually did everything through EDK and used shell commands to generate the ace file. So basically the design through ISE has some problems some where and I have not realized where exactly. I realized that the mode pins (M2M1M0) are set as 101 (boundary-scan) in EDK but the same in ISE were set as 111 (slave serial). I'm not sure but I think 101 is the desired configuration because sysAce is going to reconfigure from compact flash. So there is no external clock to the FPGA configuration unless I'm wrong. In any case I tried changing the configuration mode in ISE but it didn't work. So I'm not sure what exactly the problem is with ISE but obviously generating the ace file from the design in ISE doesn't work but the same in EDK is working. Thanks Dave for the hint on using XPS/EDK shell. Amir On Feb 5, 5:17 pm, D.J.Mulli...@gmail.com wrote: > On Feb 6, 4:13 am, Xesium <amirhossein.gholamip...@gmail.com> wrote: > > > > > Dave, > > Thanks so much. Actually removing -target mdm worked! > > I feel dumb to have spent weeks trying to fix this issue! But at least > > it is working now! > > > Thanks a lot again, > > > Amir > > > On Feb 4, 11:26 pm, David <simianfe...@gmail.com> wrote: > > > > > I actually tried this command: > > > > $ xmd -tcl genace.tcl -jprog -hw implementation/download.bit -board > > > > ml310 -target mdm -elf timer_test/executable.elf -ace system.ace > > > > > My software code is supposed to write something to hyperterminal > > > > through RS232 port and I have in fact populated the local BRAMs with > > > > the data and instructions of my software code and download.bit should > > > > contain that information (I tried commands with and without -elf > > > > timer_test/executable.elf). > > > > Did you try removing the "-target mdm" as well? If your program is in > > > bram it shouldn't be necessary. > > > > > Firstly I don't know why it is so, secondly I know no more convenient > > > > way to make sure that my design is actually loaded and working (the > > > > only way I found convenient is to write something to the output)! > > > > You could try a very simple design in ISE that just flashes a led or > > > something and make an ace file from that. That should at least tell > > > you whether it is a problem with the systemAce or the microblaze. > > > > Also, re-reading your original post - you probably don't need the OPB > > > SysAce controller unless you intend to write to the compact flash - it > > > could be causing some conflict with the sysace chip if it's not set up > > > properly. > > > > Cheers, > > > Dave > > No problem Amir. I suspect that the -target mdm switch was stopping > the mircroblaze, in much the same way as it stops when you connect to > it with xmd. > > DaveArticle: 129564
Hi Ed, Thanks. Actually the problem was solved. But the problem was something else. Previously I used to export my design to ISE and synthesize and place and route it there and then generate the ace file through iMPACT. However this time (that worked) I actually did everything through EDK and used shell commands to generate the ace file. So basically the design through ISE has some problems some where and I have not realized where exactly. I realized that the mode pins (M2M1M0) are set as 101 (boundary-scan) in EDK but the same in ISE were set as 111 (slave serial). I'm not sure but I think 101 is the desired configuration because sysAce is going to reconfigure from compact flash. So there is no external clock to the FPGA configuration unless I'm wrong. (Will you please clarify this issue?) In any case I tried changing the configuration mode in ISE but it didn't work. So I'm not sure what exactly the problem is with ISE but obviously generating the ace file from the design in ISE doesn't work but the same in EDK is working. Thanks for your information on SysAce. Also the problem with EDK9.2i is that it doesn't support ML310 board that I'm currently working on, so that's the reason that I couldn't use it. But I'm considering moving to ISE 9.1 at least. Thanks again, Amir On Feb 4, 11:31 am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > Xesium wrote: > > Hi everybody, > > I have written a very simple code for microblaze on Virtex II-Pro > > (XC2VP30 on ML310 board) which basically writes something to STD-OUT > > (through uart). When I load the design to the FPGA through parallel > > cable IV everything works perfectly which gives me the idea that > > basically there is nothing wrong with the design in general and the > > code. I've been trying to load the design through compact flash for a > > few weeks now but I haven't still been able. I'm using EDK 8.2.02 and > > ISE 8.2.03. If I generate the .ace file using EDK when I switch on the > > board the sysAce Error red LED is turned on meaning that the design is > > not loaded appropriately. However when I generate .ace file using > > iMPACT from ISE then it sounds like the design is loaded because the > > green SysAce Status LED is turned on but it writes nothing to the > > hyperterminal through which I'm getting connected to UART on the > > board. > > > Do you have any clue what the problem is? > > > I appreciate any help beforehand, > > It sounds like you have a working design since you can download through > the PC4 cable and have it run. I am not an EDK expert, but here are my > thoughts. > > The SystemACE error LED is likely being lit as you have not changed your > JTAG chain description to remove the System ACE from the chain. You need > System ACE in the chain description when downloading from a cable, but > when the System ACE is the master and programming the devices it isn't > part of the chain description since it is the master. > > In the case of iMPACT generating a valid ACE file but not a working design, > this is probably due to the software not being initialized in the BlockRAMs. > You should have an ELF file that was generated for your program that was > marked to be the one that is initialized to the BlockRAMs and a BMM file > that defines the memory map to internal/external RAMs. When you do an > "Update Bitstream" these should be combined with the placed/routed BIT file to > create a download.bit file. This is the one that you should be using with > iMPACT to generate the ACE file. > > I hope that this helps. > > BTW, 8.2i is fairly old you might also want to consider moving to 9.2i > > Ed McGettigan > -- > Xilinx Inc.Article: 129565
"Tim (one of many)" <tim@nooospam.roockyloogic.com> writes: > 5l5-pin PBGA Package, 0.5mm Ball Pitch (Top), 0.4mm Ball Pitch (Bottom) It has balls on both the top and bottom?Article: 129566
Jeff, As is pointed out by others, the issue is the worry over NBTI. Negative Bias Temperature Instability: http://en.wikipedia.org/wiki/NBTI Is an old issue, still around, where the pmos threshold voltage changes over time given different bias conditions (full ON, vs full OFF). In V4, the DCM delay lines turned out to be the best ever NBTI shift characterization means ever designed. If you intentionally held the CLKIN high on one, vs. low on another, and didn't ever change it for perhaps three or four hundred hours, when hot, you would get vastly different pulse width out of the two lines. This led to concerns that if you didn't keep the DCM delay lines "busy" they might not be able to operate over all PVT, all frequencies, and all duty cycles. Never proven in the lab (never have ever tested a single part that failed to meet specifications, no matter how stressed), but we decided to specify our way out of ever having to even deal with the issue, hence the strange specification. As well, there is an "autocal" block that is inserted for every DCM, used or not, that keeps them all "busy" so that the NBTI effect occurs evenly, and no performance could be affected by the change in Vt (because the all happen symmetrically). A bake at 150C for 48 hours brings all the Vt's back to normal (almost, not quite), so if you ever suspect something to not work from NBTI, a bake will then provide you with "proof" that it might have been NBTI. Might have been HCI (hot carrier injection), too, so a bake is not conclusive. HCI should never be a problem with our parts, at least, the qualification reports show it isn't an issue... Bottom line, I stopped worrying about NBTI three years ago, and in V5, all the NBTI stuff is completely hidden (and hardened) so there are no worries whatsoever. In V4, we have recommendations that we apply, but even those may be waived under specific circumstances. I have written, and signed official variance letters, allowing customers to violate some of these overly severe NBTI precautions when we are informed of what the real stress can be, and have studied what the worst case NBTI can be (and found it to be no issue). Please address these requests to me directly, as well as file a webcase at the same time (so everything gets tracked and officially recorded). AustinArticle: 129567
In comp.arch.fpga Jim Thompson <To-Email-Use-The-Envelope-Icon@my-web-site.com> wrote: . . >Oh Gosh, you hire another Indian again, this is a real proof of why America >is losing ground. I have many years of experience in programming and in all >sort of hardware's....Damn it! What would you change?Article: 129568
<sky465nm@trline5.org> wrote in message news:fq4qbs$675$1@aioe.org... > In comp.arch.fpga Jim Thompson > <To-Email-Use-The-Envelope-Icon@my-web-site.com> wrote: > . > . >>Oh Gosh, you hire another Indian again, this is a real proof of why >>America >>is losing ground. I have many years of experience in programming and in >>all >>sort of hardware's....Damn it! > > What would you change? I would change the TAX benifits that encourage the offshoring of jobs. Our fellow engineers in other countries are very bright. So are we american engineers, but when faced with the American job benfits and the tax benefits of going global, Larger businesses WILL send the jobs overseas. It is just cost efective. I live with the system becuse that is what is there and I enjoy interacting with my foreign brethren. I don't expect this to change anytime soon.Article: 129569
Hello all, I am writing to one of the software programmable registers (slv_reg0,1,2..) on a OPB slaves in the system using XIO_out32 command. It was working fine for sometime. but recently when i created a couple of other slave peripherals i wasnt able to write to the slv_reg. when looking using chipscope pro, I noticed that instead of iBus2IP_WrCE(0 to 4) going high, iBus2IP_RdCE(0 to4) signal goes high the Xio_out command is executed. anyone has any idea regarding this issue. with warm regards, Chakra.Article: 129570
Hi,
I would like to interface a custom DMA controller to the
user_logic created by "Create or Import Peripheral" in EDK 9.1 tool
and not use the simple DMA controller that can be included as part of
the CIP. Has anyone has any experience in doing this?
In addition I am facing the following issues
I am planning to use the dma_sg_v2_01_a component with some changes.
Has anyone used this component with their design? Can this be used
with components created by CIP? The ports defined in dma_sg_v2_01_a
are very different from the ones in dma_sg_v1_00_e.
Is PLB Master_attachment with local link used by dma_sg_v2_01_a
component is different from the master_attachment in the plb_ipif
created by CIP in EDK?
Regards
-- Rajeev
Article: 129571Austin, Our freshly manufactured cards go through a test procedure where they are first powered up and all the voltages are manually measured, and then a boundary scan test is run. All of this takes substantially more than 10 minutes. Do I understand correctly that it is not really an issue? Or should I enforce some strict rules at the company preventing anyone from having a card powered up for more than 5 min at a time unless it has been configured? Thanks, /MikhailArticle: 129572
Now I want to design a SD card,for special use,I must use fpga to implement the interface between host controller and NAND flash,can someone give me some advice if it is easy to implement it?And where I can get the controller source files for free,3X.Article: 129573
Now I want to design a SD card,for special use,I must use fpga to implement the interface between host controller and NAND flash,can someone give me some advice if it is easy to implement it?And where I can get the controller source files for free,3X.Article: 129574
On Feb 28, 3:22=A0am, rickman <gnu...@gmail.com> wrote: > I can't say that I have thoroughly analyzed your code, but I think I > can suggest some better code. =A0It is only slightly different from > yours, but I am sure it does not have any problems as it was given to > me some years ago and has worked for myself and everyone else I know > who has used it. Thanks very much for the code. I've interpreted it a bit for my case, which seems to work (using numeric_std): signal t1, t2, t3 : std_logic; ----- process (in_clk_in, rst_in) -- on input clock begin if rst_in =3D '1' then t1 <=3D '0'; elsif rising_edge(in_clk_in) then if pulse_in =3D '1' then t1 <=3D not(t2); -- when detect input pulse, set t1 to inverse of t2 end if; end if; end process; process (out_clk_in, rst_in) -- on output clock begin if rst_in =3D '1' then t2 <=3D '0'; t3 <=3D '0'; pulse_out <=3D '0'; elsif rising_edge(out_clk_in) then t2 <=3D t1; t3 <=3D t2; if ((t3 xor t2)=3D'1') then pulse_out <=3D '1'; else pulse_out <=3D '0'; end if; end if; end process; I had forgotten about the use of the xor gate - it is explained a bit here too: http://www.chipdesignmag.com/print.php?articleId=3D32?issueId=3D5 The loopback of t2 between the two domains seems to avoid the issue of reading the same variable at different times on an asynchronous clock. As long as the second process is not replicated for some reason (which could cause t1 to have different values in each replication), this would seem to work fine. If out_clk_in is fast, an additional register (e.g. t4) could be added and then do xor between t4 and t3 if it were felt necessary to extend the allowable metastability settling time further, but in general this version would seem ok if the t2 path length is short to the xor gate. Any further comments appreciated. Tom
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