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FPGA wrote:
> I have a bunch of functions I would like to synthesize on Quartus.
That would be a bunch of design entities.
Functions return values only and are collected in a package.
> These are going to be part of a library. I would like to get resource
> utilization of each function. The functions are generic.
All of the generics must have a default value for synthesis.
-- Mike Treseler
Article: 129501On Feb 26, 12:27=A0pm, Mike Treseler <mike_trese...@comcast.net> wrote: > FPGA wrote: > > I have a bunch of functions I would like to synthesize on Quartus. > > That would be a bunch of design entities. > Functions return values only and are collected in a package. > > > These are going to be part of a library. I would like to get resource > > utilization of each function. The functions are generic. > > All of the generics must have a default value for synthesis. > > =A0 =A0 =A0 =A0-- Mike Treseler I appreciate your help. Thank youArticle: 129502
On Feb 26, 11:34=A0am, Jim Lewis <j...@synthworks.com> wrote: > FPGA, > > > I just commented my signals SEED1,SEED2 in the top level. I > > initialised the values of SEED1, SEED2 within the process (not taking > > as signal inputs as before). Now, I see that I am getting different > > sequence for different values of SEED1, SEED2. Why would this happen? > > Shouldnt it behave the same if I have SEED1, SEED2 as signals and then > > within process I have variable S1,S2 initialised to signal SEED1, > > SEED2 > > I dont understand why it behaves so. > > Your simulator should have reported an error when you declared SEED1 > and SEED2 as signals as uniform requires them to be variables. > > Jim It did not report error. I had assigned the signals to variables within the process and then passed then to uniform. I am not sure if its a good idea to assign signals to variables (is it a big NO ?)Article: 129503
FPGA wrote:
> It did not report error. I had assigned the signals to variables
> within the process and then passed then to uniform. I am not sure if
> its a good idea to assign signals to variables (is it a big NO ?)
This is a matter of style.
If the signal is used for nothing else, I would eliminate it.
-- Mike Treseler
Article: 129504On Feb 26, 10:22=A0am, Philip Potter <p...@doc.ic.ac.uk> wrote: > Symon wrote: > > Philip Potter wrote: > >> Nico Coesel wrote: > >>> "Symon" <symon_bre...@hotmail.com> wrote: > > >>>> Nico Coesel wrote: > >>>>> The best answer to all these questions is a question. > >>>> Is it? > >>> Ofcourse. Interview questions are designed to start a technical > >>> debate in order to reveal the applicant's knowledge (or lack > >>> thereof). > >> Is that the only purpose? > > > What other purpose could there be? > > What are you suggesting? Isn't it obvious?Article: 129505
austin wrote: > Andreas, > > Your question is equivalent to: "If I walk outside, how much noise > will I hear?" > > Austin Hi Andreas, Austin's right! :-) However, the thing to remember is that it is practicable to be able to predict the noise your oscillator will have before you build it. Noise doesn't just appear for no reason, it comes from many sources. With some work, you can make informed predictions of the performance of a circuit. There's no 'magic' or 'guesswork' to it, just because it's noise. It can be modelled, with good accuracy. My main method for doing these calculations invariably involves taking my synthesiser designer mate to the pub, and exchanging beer for calculations. He normally yaps on about Leeson's model, how resistors are evil, and diodes are great! YMMV! But, this is a big, big subject. I've used some stuff in Gardner's PLL book, which I found useful. HTH., Syms.Article: 129506
Hello Folks,
Listed below is a simple NoBL SRAM model that
I use to help me debug. Recently, I've been
getting a ModelSim error numstd_conv_unsigned_nu
Natural arg value is negative. I Googled this
and found it to an issue with the to_unsigned
function and the natural must be from the 'length
attribute? I guess; don't know. please help.
Brad Smallridge
AiVision
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity memory is
port(
clk : in std_logic;
mem_wr : in std_logic; -- active high memory write
mem_addr : in std_logic_vector(17 downto 0); --18 bits 256K
mem_wr_data : in std_logic_vector(35 downto 0);
mem_rd_data : out std_logic_vector(35 downto 0) );
end memory;
architecture beh of memory is
signal mem_wr_1 : std_logic;
signal mem_wr_2 : std_logic;
signal mem_addr_1 : std_logic_vector(17 downto 0);
signal mem_addr_2 : std_logic_vector(17 downto 0);
-- keep the size of the memory small here
-- to keep ModelSim simulation convenient
constant size : integer := 127;
type mem_array_type is array(0 to size) of integer;
signal mem_array : mem_array_type;
begin
memory_proc:process(clk)
variable addr1 : integer;
variable addr2 : integer;
begin
if(clk'event and clk='1')then
mem_wr_1 <= mem_wr;
mem_wr_2 <= mem_wr_1;
mem_addr_1 <= mem_addr;
mem_addr_2 <= mem_addr_1;
addr1 := to_integer(unsigned(mem_addr_1));
addr2 := to_integer(unsigned(mem_addr_2));
if( addr2 <= size and mem_wr_2='1' )then
mem_array(addr2) <= to_integer(unsigned(mem_wr_data));
end if;
if( addr1 <= size )then
if( mem_wr_2='0' )then
mem_rd_data <= std_logic_vector
(to_unsigned(mem_array(addr1),mem_rd_data'length));
else
mem_rd_data <= (others=>'0');
end if;
else
-- 82 for all memory locations greater than size
mem_rd_data <= std_logic_vector(to_unsigned(82,mem_rd_data'length));
end if;
end if;
end process;
end beh;
Article: 129507
I used the ISE tool "Architecture Wizard" to generate the equivalent
DCM block below. You may want to try it out to see if it works any
better.
======================================================
module DCM_Verilog(CLKIN_IN,
RST_IN,
CLKDV_OUT,
CLKFX_OUT,
CLKIN_IBUFG_OUT,
CLK0_OUT,
LOCKED_OUT);
input CLKIN_IN;
input RST_IN;
output CLKDV_OUT;
output CLKFX_OUT;
output CLKIN_IBUFG_OUT;
output CLK0_OUT;
output LOCKED_OUT;
wire CLKDV_BUF;
wire CLKFB_IN;
wire CLKFX_BUF;
wire CLKIN_IBUFG;
wire CLK0_BUF;
wire GND_BIT;
assign GND_BIT = 0;
assign CLKIN_IBUFG_OUT = CLKIN_IBUFG;
assign CLK0_OUT = CLKFB_IN;
BUFG CLKDV_BUFG_INST (.I(CLKDV_BUF),
.O(CLKDV_OUT));
BUFG CLKFX_BUFG_INST (.I(CLKFX_BUF),
.O(CLKFX_OUT));
IBUFG CLKIN_IBUFG_INST (.I(CLKIN_IN),
.O(CLKIN_IBUFG));
BUFG CLK0_BUFG_INST (.I(CLK0_BUF),
.O(CLKFB_IN));
DCM_SP DCM_SP_INST (.CLKFB(CLKFB_IN),
.CLKIN(CLKIN_IBUFG),
.DSSEN(GND_BIT),
.PSCLK(GND_BIT),
.PSEN(GND_BIT),
.PSINCDEC(GND_BIT),
.RST(RST_IN),
.CLKDV(CLKDV_BUF),
.CLKFX(CLKFX_BUF),
.CLKFX180(),
.CLK0(CLK0_BUF),
.CLK2X(),
.CLK2X180(),
.CLK90(),
.CLK180(),
.CLK270(),
.LOCKED(LOCKED_OUT),
.PSDONE(),
.STATUS());
defparam DCM_SP_INST.CLK_FEEDBACK = "1X";
defparam DCM_SP_INST.CLKDV_DIVIDE = 2.0;
defparam DCM_SP_INST.CLKFX_DIVIDE = 25;
defparam DCM_SP_INST.CLKFX_MULTIPLY = 4;
defparam DCM_SP_INST.CLKIN_DIVIDE_BY_2 = "FALSE";
defparam DCM_SP_INST.CLKIN_PERIOD = 20.000;
defparam DCM_SP_INST.CLKOUT_PHASE_SHIFT = "NONE";
defparam DCM_SP_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
defparam DCM_SP_INST.DFS_FREQUENCY_MODE = "LOW";
defparam DCM_SP_INST.DLL_FREQUENCY_MODE = "LOW";
defparam DCM_SP_INST.DUTY_CYCLE_CORRECTION = "FALSE";
defparam DCM_SP_INST.FACTORY_JF = 16'hC080;
defparam DCM_SP_INST.PHASE_SHIFT = 0;
defparam DCM_SP_INST.STARTUP_WAIT = "FALSE";
endmodule
======================================================
Article: 129508On Feb 21, 5:26 pm, Clemens Blank <CBl...@hotmail.com> wrote: > Hi > > I just came across some interview questions for digital design, and > would like to discuss my solutions with you! > > #Design a circuit to divide input frequency by 2 > I could do this with aToggleFlip flop where the inverted output > is connected to the input, then i also divide the clock frequency by two > Last time I looked, a Toggle flip-flop with its output inverted to its input will stop toggling as soon as the output goes high... I think you meant to make a Toggle flip flop using a D flip-flop with the inverted output tied to the D input. > # Design a divide-by-3/divide-by-5 sequential circuit with 50% duty cycle. > I was thinking of having here a statemachine that outputs for 3 cycles > 0, and then it changes the state to output 3 times a 1 at each clock > transition. > You could do that, but it would be tough to synthesize. A lot easier to have only elements switching on one clock edge or the other. By the way, even so you only get 50% duty cycle out if the clock had 50% duty cycle coming in. There was a nice tool posted called: Topweaver Anydivider 1.0 Topweaver Tools Family Copyright (c) 2002-2006, Topweaver Author: Song Tianning Website: http://www.topweaver.com All rights reserved. > # Which one is superior: Asynchronous Reset or Synchronous Reset > > Well, until now I was always using asynchronous resets because u > find it in most textbooks ;) not so sure about the right answer here! Superior for doing what? Resetting sooner whether the clock is running or not? Resetting in a way that doesn't create glitches on the outputs? Good Luck, GaborArticle: 129509
Symon, Glad we agree. I was trying to answer the more general question "how much jitter will my FPGA add to my pcb?" For that, there is no 'Leeson's model'. By the way, Dave Leeson is a "neighbor" of mine in the Santa Cruz mountains (the 123 mph winds this month affected us both!). Interesting that his work at California Microwave to explain PLL's to his designers has been carefully converted from his original code to more useful (and modern) tools today. And, all of his napkin 'lectures' converted into white papers, applications notes, and such. AustinArticle: 129510
Kundan, A simple VHDL example for the Spartan-3A Starter Kit and ST Micro M25P16 is posted on the Avnet Design Resource Center under Support Files for the Spartan-3A Starter Kit. https://www.em.avnet.com/common/filetree/0,2740,RID%253D0%2526CID%253D44394%2526CCD%253DUSA%2526SID%253D32214%2526DID%253DDF2%2526LID%253D32232%2526PVW%253D%2526PNT%253D%2526BID%253DDF2%2526CTP%253DSTA,00.html Bryan kundan...@gmail.com wrote: > Hi everybody, > > I am currently working on the mulitboot feature of xilinx s3a. > I have programmed one of the on-board PROMs with 3 different files at > different locations but there are lots of issues using the ICAP > protocol to reconfigure from those locations as explained in ug332. > Can anyone help me with a detailed (and simple)example explaining how > to use ICAP? > How can an ICAP driver be used?? > > KundanArticle: 129511
I really appreciate if anyone can tell. Thanks George On Feb 26, 12:12 am, "=C9=B5=B9=CF" <whuste...@gmail.com> wrote: > Hi: > Does anyone know whether Altera has some analogous file like XDL of > Xilinx so that we can read the place and route of the circuit of > Altera's FPGA textually? > If not, I wonder whether there is a third tool that can generate an > intermediate file so that it can accomplish this process: Altera FPGA > circuit (Placed and Routed) <-->intermediate file<-->Xilinx FPGA > circuit (Placed and Routed). > > Thanks. > GeorgeArticle: 129512
On Sat, 23 Feb 2008 02:14:31 +0000, "Tim (one of many)" <tim@nooospam.roockyloogic.com> wrote: >leevv wrote: > >> I found that 9.1 is much more stable then 9.2. So I'm skiping 9.2 >> completely and wait for 10.1 which is comming , I guess, in March. > >9.2 P&R is sooooo much faster with big jobs. Yeah... after 30sec the (self-terminated) job is done. LOLArticle: 129513
Hi, this interface is input or output for the FPGA. In the first case (input) you have to put set_input_delay -max A+B wherw A is the time CP_to_Q (clock to Q) + and B the delay of interconnection. this say to the input of FPGA that has clock period -(A+B) to caputred the data. If you don't know this value you could put 60% clk_period about 6ns. In the second case (output), if I understood well it is your, you have to put set_output_delay -min 2ns to be sure that FPGA don't change the databus before 2ns ( and be sure to met the hold time) and set_output_delay -max (clk_period - Tsetup - Tdelayinterconn) is you don't know Tdelay interconn I think that 60% of clk_period is good. have fun. Dolphin ha scritto: > Hello, > > I have some problem understanding the set_input_delay min and max > constraint. > Assume that you have an interface that is connected to an FPGA. > This interface has a clock (Clk) and a databus (DB). > The datavalid window is centered around the rising edge of Clk. Assume > a setup time of 1ns and a hold time of 2 ns. The clk period is 10 ns. > How should I constrain this with the set_input_delay command? > > thanks for helping me, > KarelArticle: 129514
Hi. Let's say, I have big table which is usually suitable to fit it in some ROM. But it's possible to construct some circuit containing only primitive gates that acts just as that ROM. Here is an example of converting tables from DES cipher into gates: http://www.darkside.com.au/bitslice/ I'm interesting, is there any automated way to do so, thus to have on output circuit with the smallest possible primitive gates (AND, OR, NOT, XOR).Article: 129515
There are multiple way of doing this. In college 10 years ago, I wrote a C program to do this based on my engineering coarse at the time. Most synthesizers can do this to some extent. They will optimize it to fit in their target library. If the FPGA has a ram that it fits, The code may not be optimized becuase the fpga can just use the memory. "sdf" <drop669@gmail.com> wrote in message news:b4b095a8-d0a0-42d8-b395-da07408e7474@e60g2000hsh.googlegroups.com... > Hi. > Let's say, I have big table which is usually suitable to fit it in > some ROM. > But it's possible to construct some circuit containing only primitive > gates that acts just as that ROM. > Here is an example of converting tables from DES cipher into gates: > http://www.darkside.com.au/bitslice/ > I'm interesting, is there any automated way to do so, thus to have on > output circuit with the smallest possible primitive gates (AND, OR, > NOT, XOR).Article: 129516
Found the algorithm used. http://www.dei.isep.ipp.pt/~ACC/bfunc/ This is the method I wrote a C program for, but this is NOT my code. careful about implementing this code in your HP calculator. Your Instructor will not give you full credit on the exam if you do not show your work. Mine sure didn't. I think this is the one exam I failed in my engineering coarses. I had the final solution, I just skipped the boring part. Mind numbing to do by hand for a large table. "Dwayne Dilbeck" <ddilbeck@yahoo.com> wrote in message news:13s99in78ja4rbc@corp.supernews.com... > There are multiple way of doing this. In college 10 years ago, I wrote a > C program to do this based on my engineering coarse at the time. Most > synthesizers can do this to some extent. They will optimize it to fit in > their target library. If the FPGA has a ram that it fits, The code may > not be optimized becuase the fpga can just use the memory. > > "sdf" <drop669@gmail.com> wrote in message > news:b4b095a8-d0a0-42d8-b395-da07408e7474@e60g2000hsh.googlegroups.com... >> Hi. >> Let's say, I have big table which is usually suitable to fit it in >> some ROM. >> But it's possible to construct some circuit containing only primitive >> gates that acts just as that ROM. >> Here is an example of converting tables from DES cipher into gates: >> http://www.darkside.com.au/bitslice/ >> I'm interesting, is there any automated way to do so, thus to have on >> output circuit with the smallest possible primitive gates (AND, OR, >> NOT, XOR). > >Article: 129517
On Feb 27, 1:52=A0am, "Dwayne Dilbeck" <ddilb...@yahoo.com> wrote: > There are multiple way of doing this. =A0In college 10 years ago, I wrote = a C > program to do this based on my engineering coarse at the time. =A0Most > synthesizers can do this to some extent. They will optimize it to fit in > their target library. =A0If the FPGA has a ram that it fits, =A0The code m= ay not > be optimized becuase the fpga can just use the memory. Yes, but I still don't know, what will be better in my case: generated logic or just usual RAM blocks in FPGA. It's interesting to see your work too, but is there anything already incorporated into well-known EDA tools? Or, for example, Altera Quartus, do this in automated way so I can free my mind from this?Article: 129518
>It's interesting to see your work too It isn't my work. Can't take the credit. I just happened to do something like it a long time ago. >but is there anything already incorporated into well-known EDA tools? Ah... this is a different question versus what you first posted. The answer is both YES and NO. The comericially available tools do have optimizing routines to save chip area or to map to existing target resources. Will Quartus know that a giant table can be optimized to a small equation? Don't know haven't used that tool. But based on the tools I have used it is IFFY at best. The optimization may map it to a smaller equation but perhaps not the absolute minimum. Or it may map it to RAM and skip the the whole processes becuase the FPGA had the resource. It is YOUR job as the engineer to weight the value of using the built in ram versus optimizing to a logic function. The optimizers available in the tools can do alot, but they also require alot of input from the user to tell it how to do it's job. Do you need speed? Do you need less gates? Do you need to keep the hierachy? Does your design need to make use of a large portion of the available RAM? if so mapping to gates may be a better option. "sdf" <drop669@gmail.com> wrote in message news:c35e4a39-c301-4b22-9b48-f669a16e6982@d21g2000prf.googlegroups.com... On Feb 27, 1:52 am, "Dwayne Dilbeck" <ddilb...@yahoo.com> wrote: > There are multiple way of doing this. In college 10 years ago, I wrote a C > program to do this based on my engineering coarse at the time. Most > synthesizers can do this to some extent. They will optimize it to fit in > their target library. If the FPGA has a ram that it fits, The code may not > be optimized becuase the fpga can just use the memory. Yes, but I still don't know, what will be better in my case: generated logic or just usual RAM blocks in FPGA. It's interesting to see your work too, but is there anything already incorporated into well-known EDA tools? Or, for example, Altera Quartus, do this in automated way so I can free my mind from this?Article: 129519
checo wrote: > On Feb 26, 10:22 am, Philip Potter <p...@doc.ic.ac.uk> wrote: >> Symon wrote: >>> Philip Potter wrote: >>>> Nico Coesel wrote: >>>>> "Symon" <symon_bre...@hotmail.com> wrote: >> >>>>>> Nico Coesel wrote: >>>>>>> The best answer to all these questions is a question. >>>>>> Is it? >>>>> Ofcourse. Interview questions are designed to start a technical >>>>> debate in order to reveal the applicant's knowledge (or lack >>>>> thereof). >>>> Is that the only purpose? >> >>> What other purpose could there be? >> >> What are you suggesting? > > Isn't it obvious? To whom?Article: 129520
Hi Huang, grant0920 wrote: > I have successfully integrated the ICAP driver to our Linux on the PPC > on the ML310 board. But now I had a problem about the ICAP driver. My > combinational circuits, such as the very simple adder design and the > subtractor design, can successfully be partially reconfigured by the > ICAP driver, but the sequential circuit cannot be. Are there any > things that I have to consider, such the hardware design? Thanks! The impact programming tool can download partial bitstreams just like the ICAP driver. So, test your partials there. If they work in impact, but not through ICAP + Linux driver, then it's pretty strange. It's most likely an issue with the bitstreams themselves - double check how you generated them, and try the partial-reconfig mailing list or other sources of help on the subject (this newsgroup!). Since you have problems with sequential but not combinational circuits, my first guess would be a reset or clocking problem in your crossing from fixed -> reconfigurable partitions. Regards, JohnArticle: 129521
Jean-sébastien LEROY wrote: > You can have a see to CentOS distro. > This is a recompiled RedHat without modifying sources (so not like Fedora). > I am using it in a production environment. It is a very powerfull, fast > distro and very stable and reliable. But this is jst a working environment, > no compiz or something else .... :) There is a YUM repo with Beryl RPMs for CentOS 5 - so I have a very powerful workstation and visual bling in one machine :) I must take a minute to rave about my new setup - Dell OptiPlex 755 Core2-Duo @ 3GHz with 4GB RAM, 2x150GB 7200 RPM SATA drives in RAID 1 configuration, CentOS 5, dual widescreen 22" LCD panels all for about AU$2500. Hard to argue with that. Xilinx tool performance is great, and I can do a clean MicroBlaze Linux software platform rebuild in under 5 minutes - kernel, apps, libs, everything. And Beryl/Compiz for desktop eye candy - life is good. JohnArticle: 129522
On Tue, 26 Feb 2008 11:20:39 +0000 (UTC), Andreas Ehliar <ehliar-nospam@isy.liu.se> wrote: >I'm looking for a "rule of thumb" of what I should expect in terms >of jitter on the clock signal. > > >It should be relatively easy to find what jitter an oscillator has >(e.g. one datasheet said 31ps peak-to-peak jitter (typical)). On the >other hand, I have no idea what kind of jitter you could expect from >effects that are caused by for example the PCB as I am not an expert >on high speed PCB design. > >Does anyone on this newsgroup either have any decent numbers or a >good application note or similar resource they can point me to? > >Ideally, I would like a rule of thumb like the following: >"If the timing analyzer says your design can meet timing with a > clock cycle of X ns, subtract Y ns from that to have a reasonable > margin against clock jitter." > >Is Y going to be in the ballpark of 0.05 ns, 0.5 ns, or even >longer? > >/Andreas Using a good but cheap surface-mount crystal oscillator, and with clean single-ended routing to the clock input pin of an fpga, you can get numbers like 2-5 ps RMS jitter, measured cycle-to-cycle, which is what an fpga cares about. Figure that p-p is about 5x RMS. A differential clock, pecl or lvds, is likely to be a bit better, and higher frequency clocks are of course better than slow ones. The clock multipliers unside fpga's, at least in the Spartan 3's, are pretty bad, so use a fast rock and don't multiply if possible. A lot of XOs lately seem to have fast but weak edges, so they don't drive a matched-impedance pcb trace well. So locate them right at the fpga clock pin, or buffer before driving traces any distance. JohnArticle: 129523
John LeVieux wrote: > I used the ISE tool "Architecture Wizard" to generate the equivalent > DCM block below. You may want to try it out to see if it works any > better. Thanks, John. The Spartan User's Guide talked about the clock wizard but it is a Windows only feature so I've not been able to try it since I sit at a Linux box. My original post was wrong in that I said I have a Spartan 3E. In fact it is just a Spartan 3. I removed the "_SP" references to change from a 3E to a 3 and it compiled correctly. Sad to say there's still no output except on the divide-by-32 counter output. I'll try simulating the DCM this weekend when I can spend more time on it. Thanks very much for posting the wizard output. Bob Smith > ====================================================== > module DCM_Verilog(CLKIN_IN, > RST_IN, (snip)Article: 129524
On 2008-02-26, austin <austin@xilinx.com> wrote: > I have seen from 50 ps on a pcb with everything done right, to over > 2,000 picoseconds, on a pcb where "everything went wrong." > > Some typical numbers for "I didn't care, and I would be happy with my > results" come in from 200 to 500 ps (all peak to peak numbers). This is exactly the kind of figures I was interested in. Of course, if I really wanted to design a PCB board myself I would have to worry quite a bit more about this but right now I'm quite happy to have a rough idea of what to expect. Thanks! /Andreas
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