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On 25 Mag, 20:45, austin <aus...@xilinx.com> wrote: > Andrea, > > Since there are no MGT's, you will need to use some IO's from IO banks. > > You can use: some number of LVDS 100 ohm differential drivers to > receivers (one direction only, use two sets of buses), a group of single > ended IOs matched to a ribbon cable (with ground, signal, ground, > dignal, this is close to 50 ohms, and can go perhaps 10 meters at the > speed you need). > > I suggest the single ended groups, perhaps 8 wires for data, and one > forwarded clock (for nine signals), and a bus like this for each direction. > > Clocking these 8 wires at even 10 MHz, would provide 80 Mb/s. At this > slow a rate, you don't really need to clock forward, but I still would > suggest it (along with the data, there is the clock on the ninth wire to > strobe the other end). That way, you don't have to figure out how to > get the clock off of one pcb, and get it to the other one (for a system > synchronous solution). > > Just have registers at each end, and create your own (very simple) > protocol. If a "data valid" or "data waiting" signal is needed, just > use another wire. 20 wire ribbon cables are pretty common (ten signal, > ten grounds). Drive the transmit end with something like LVCMOS 8 mA > FAST, which is very close to 50 ohms, and there should be no overshoot, > or undershoot, and the Signal integrity will be good. If that is still > too strong, 6 mA, and even 4 mA drivers can be selected. > > The only reason a protocol is required with the MGTs (like aurora:http://www.xilinx.com/products/design_resources/conn_central/grouping... > is that designers need huge bandwidth, and in order to re-synchronize > multiple MGTs (channel bonding), a layer is required to manage all that > stuff. > > With a simple parallel interface, you pretty much only need to implement > what you need. > > To connect these buses to the 405PPC, you will either have to interface > to the PLB bus, or create an input and output port that is connected to > the 405PPC. Depending on how fancy you want this to be, it could be as > simple as input and output instructions (you create the protocol in > software), or as fancy as a FIFO buffer with DMA into memory mapped into > the 405PPC data memory (the protocol commonly used here is referred to > as "flags placed under a rock" which is a reference to one processor > just waits for a memory location to change, which tells it that the data > it is waiting for is all there, and ready to be read from memory...the > transmitting processor sends all the data, and sets the flag to tell the > receiving processor to pick up the data. > > Lots of choices here, and not many "standards" as the task is very > simple, and folks tend to use only what logic they need to in order to > do the job. > > Once you pop up to MGTs, there are many more choices, only because there > are more complex interfaces: ethernet, fibre channel, PCIe, etc..... > > If you don't need fibre channel, then you don't need media access > controllers (MAC), etc.http://www.xilinx.com/products/design_resources/conn_central/solution... > > Austin Thank you Austin for your reply, I found it very intresting. I'll search something about your hints over internet and I'll post the results (and surely other questions). Just another little question. Why, in your opinion, even Xilinx in its SPI core doesn't support off-chip Master? SPI peripheral seems to fit well to my design requrements but it has this huge limitation... I don't understand why... Any ideas?Article: 119776
Great. That sucks. You'd think Xilinx would provide a way to send JTAG commands via iMPACT or maybe even Chipscope. Guess not. ---Matthew Hicks > Matthew Hicks schrieb: > >> I read all of the documents I could find about using the JTAG port as >> a communications >> interface to the FPGA and implemented my own JTAG controlled logic. >> The >> problem is, none of the documents that I read gave a decent solution >> as to >> how to get access to the JTAG chain on the PC side of things. I am >> using >> the Virtex II-Pro XUP board which has a USB front end to the JTAG >> interface. >> Is there an existing software solution available that I can use to >> send >> data to the user JTAG registers? If not, then is there a Xilinx API >> that >> I need to use to write a program to do it myself or do I need to use >> a standard >> USB library? Finally, once I am able to send data to the board's USB >> interface, >> is there a protocol that I need to follow to work with the Cypress >> USB chip >> or can I just send raw JTAG commands as the data payload? >> ---Matthew Hicks >> > No. > > you can talk to almst any other interface but not to the xilinx > platform cable as xilinx does not make the protocol info available. > > so, in generic talking to JTAG from PC is piece of cake. > but if the interface is xilinx platform usb, you just cant do it, > unless you load 3rd party firmware into the cypress chip... > Antti >Article: 119777
Matthew Hicks schrieb: > Great. That sucks. You'd think Xilinx would provide a way to send JTAG commands > via iMPACT or maybe even Chipscope. Guess not. > > well, they "kinda" do... in such manner that I never bothered even trying.. 1 you can execute SVF or maybe even STAPL with impact 2 you can send commands in impact debug mode 3 you can start chipscope and use tcl to send commands 4 you can RE the tcpip protocol and send commands to impact cable server 5 you can RE the chipscope server protocol and send commands to chipscope server all those methods work... but you cant talk to platform USB cable, unless you use your own firmware replacement or RE the usb protocol or DLL entry poins to xilinx libraries :( AnttiArticle: 119778
kousta...@gmail.com schrieb: > Hello everybody, > > I m able to access/write DDR memory through a > EDK application. I also want to interface with a ASIC on the FPGA and > for that I need to pass the data read from the DDR SDRAM to specific > BRAMs in FPGA. Does anybody has any idea about how to do this? Any > tips/suggestions will be greatly helpful. > > Thanks, > Koustav you have put an ASIC on top of the FPGA !? if the ASIC is on FPGA then well, is it wireless ASIC, or is the ASIC connected to the FPGA somehow? If the ASIC has connection to the FPGA pins then you need some interface to the ASIC, the question about BRAM seems ir-relevant. What you need is some external interface, that depends on the ASIC you need to communicate with.. as of "specific BRAM" - it usually does not matter what instance of BRAM is used, they BRAMs are LOCed automatically, so you do not need to worry about them usually. Or what you mean by specific BRAM ?? or maybe you wanted to ask something else ? AnttiArticle: 119779
sudhakar...@gmail.com schrieb: > Hi to all > > i am implementing my own DDR 2 @400 controller Dear sudhakar a succesful implementation of highperformance DDR2 400 Memory IP in any FPGA is a task that takes at least 6 man-months. How many of those have you already spent? Do you think somebody can give you "little advice" and you get it working just like that? When you are SHOUTING to the group, you hardly ever get response. AnttiArticle: 119780
> Matthew Hicks schrieb: > >> Great. That sucks. You'd think Xilinx would provide a way to send >> JTAG commands via iMPACT or maybe even Chipscope. Guess not. >> > well, they "kinda" do... > in such manner that I never bothered even trying.. > 1 you can execute SVF or maybe even STAPL with impact > 2 you can send commands in impact debug mode > 3 you can start chipscope and use tcl to send commands > 4 you can RE the tcpip protocol and send commands to impact cable > server > 5 you can RE the chipscope server protocol and send commands to > chipscope server > all those methods work... > > but you cant talk to platform USB cable, unless you use your own > firmware replacement > or RE the usb protocol or DLL entry poins to xilinx libraries :( > Antti > Thanks Antti. I thought of doing 1 and 3, but access to said features in the GUI wasn't apparent to me (I'm using version 9.1). I will dig around in the tools some more to see if I can figure it out. Thanks. ---Matthew HicksArticle: 119781
On May 25, 3:26 pm, Antti <Antti.Luk...@googlemail.com> wrote:
> kousta...@gmail.com schrieb:
>
> > Hello everybody,
>
> > I m able to access/write DDR memory through a
> > EDK application. I also want to interface with a ASIC on the FPGA and
> > for that I need to pass the data read from the DDR SDRAM to specific
> > BRAMs in FPGA. Does anybody has any idea about how to do this? Any
> > tips/suggestions will be greatly helpful.
>
> > Thanks,
> > Koustav
>
> you have put an ASIC on top of the FPGA !?
>
> if the ASIC is on FPGA then well, is it wireless ASIC, or is the ASIC
> connected to the FPGA somehow?
Hello Antii,
I shd have been more clear on that. By ASIC I mean I have
a RTL level code implemented in ISE on the FPGA fabric. Now this RTL
code uses some BRAMs as for data access and this data is provided by
the On-board DDR SDRAM, with the BRAMs acting as buffers. I m
interfacing the DDR memory using the EDK with PPC acting as the IO
processor. What I want to do is to write the data from the DDR memory
to the BRAM and let the RTL code on the FPGA pick up the data from the
"same" BRAM.
Thanks,
Koustav
>
> If the ASIC has connection to the FPGA pins then you need some
> interface to the ASIC, the question about BRAM seems ir-relevant. What
> you need is some external interface, that depends on the ASIC you need
> to communicate with..
>
> as of "specific BRAM" - it usually does not matter what instance of
> BRAM is used, they BRAMs are LOCed automatically, so you do not need
> to worry about them usually. Or what you mean by specific BRAM ??
>
> or maybe you wanted to ask something else ?
>
> Antti
Article: 119782kousta...@gmail.com schrieb: > On May 25, 3:26 pm, Antti <Antti.Luk...@googlemail.com> wrote: > > kousta...@gmail.com schrieb: > > > > > Hello everybody, > > > > > I m able to access/write DDR memory through a > > > EDK application. I also want to interface with a ASIC on the FPGA and > > > for that I need to pass the data read from the DDR SDRAM to specific > > > BRAMs in FPGA. Does anybody has any idea about how to do this? Any > > > tips/suggestions will be greatly helpful. > > > > > Thanks, > > > Koustav > > > > you have put an ASIC on top of the FPGA !? > > > > if the ASIC is on FPGA then well, is it wireless ASIC, or is the ASIC > > connected to the FPGA somehow? > Hello Antii, > > I shd have been more clear on that. By ASIC I mean I have > a RTL level code implemented in ISE on the FPGA fabric. Now this RTL > code uses some BRAMs as for data access and this data is provided by > the On-board DDR SDRAM, with the BRAMs acting as buffers. I m > interfacing the DDR memory using the EDK with PPC acting as the IO > processor. What I want to do is to write the data from the DDR memory > to the BRAM and let the RTL code on the FPGA pick up the data from the > "same" BRAM. > > Thanks, > Koustav just add some BRAM controller and wire the second port to user logic and you are done. anttiArticle: 119783
On 25 May 2007 10:57:53 -0700, Brian Davis <brimdavis@aol.com> wrote: [snip] Thanks for that Brian. This solved a 3 year old bug that I had never been able to explain before. Regards, AllanArticle: 119784
Thanks, I will sit down and read the manual for some deeper insight. But, I did what you said and I have at least the start of something working. Thanks for saving me the hours/days of pain. ---Matthew Hicks > You can definitely send JTAG commands using ChipScope 9.1, look at the > TCL interface in the ChipScope 9.1 user guide, chapter 5: > > http://www.xilinx.com/ise/verification/chipscope_pro_sw_cores_9_1i_ug0 > 29.pdf > > There is also an example tcl script in the ChipScope installation > which should provide you with the basics on how to use it correctly. > ChipScope also provides a tcl interpreter using the script > cs_xtclsh.bat/sh but ActiveTcl can also be used (meaning you can also > use wish and create a simple GUI interface). > > Try it out yourself from the command line: > > 'cd <chipscope install>/bin/<platform>' > > run 'cs_xtclsh csejtag_example1.tcl -usb' > > Matthew Hicks wrote: > >> Great. That sucks. You'd think Xilinx would provide a way to send >> JTAG commands via iMPACT or maybe even Chipscope. Guess not. >> >> ---Matthew Hicks >> >>> Matthew Hicks schrieb: >>> >>>> I read all of the documents I could find about using the JTAG port >>>> as >>>> a communications >>>> interface to the FPGA and implemented my own JTAG controlled logic. >>>> The >>>> problem is, none of the documents that I read gave a decent >>>> solution >>>> as to >>>> how to get access to the JTAG chain on the PC side of things. I am >>>> using >>>> the Virtex II-Pro XUP board which has a USB front end to the JTAG >>>> interface. >>>> Is there an existing software solution available that I can use to >>>> send >>>> data to the user JTAG registers? If not, then is there a Xilinx >>>> API >>>> that >>>> I need to use to write a program to do it myself or do I need to >>>> use >>>> a standard >>>> USB library? Finally, once I am able to send data to the board's >>>> USB >>>> interface, >>>> is there a protocol that I need to follow to work with the Cypress >>>> USB chip >>>> or can I just send raw JTAG commands as the data payload? >>>> ---Matthew Hicks >>> No. >>> >>> you can talk to almst any other interface but not to the xilinx >>> platform cable as xilinx does not make the protocol info available. >>> >>> so, in generic talking to JTAG from PC is piece of cake. >>> but if the interface is xilinx platform usb, you just cant do it, >>> unless you load 3rd party firmware into the cypress chip... >>> AnttiArticle: 119785
Xilinx user,
Welcome to the sunny side. If you sense this is the dark one, you have been
severely brainwashed in the past.
My friend and colleague Karl has covered your question regarding I/O pullups
pretty well, so no need to expand on this.
As to initializing ROMs in Verilog, the Quartus documentation, Volume 1,
page 326 (in my beta docs) give the following simple template:
module ram_with_init(
output reg [7:0] q,
input [7:0] d,
input [4:0] write_address, read_address,
input we, clk
);
reg [7:0] mem [0:31];
integer i;
initial begin
for (i = 0; i < 32; i = i + 1)
mem[i] = i[7:0];
end
always @ (posedge clk) begin
if (we)
mem[write_address] <= d;
q <= mem[read_address];
end
endmodule
or, with $readmemb or $readmemh:
reg [7:0] ram[0:15];
initial
begin
$readmemb("ram.txt", ram);
end
You may want to take a look at www.alteraforum.com/forum for more of this
type of question. alteraforum is a bit of a grassroots effort to set up a
community-driven technical forum for Altera users given the xilinx-oriented
nature of this newsgroup.
Hope this helps.
Best regards,
Ben Twijnstra
Article: 119786"Udo" <WeikEngOff@aol.com> wrote in message news:1180112092.538999.105490@p77g2000hsh.googlegroups.com... > Hello, > > my design consits of a Softcore, a ROM and a RAM. For the RAM I'm > using a Distributed Memory (v7.1) > due to its size of only 256 * 8 bit. But I can't find that RAM in the > ModelSim Workspace/Memories tabsheet. > The ROM is there. Is the reason that the ROM is a block memory, that > would mean a distributed memory isn't > recognized as memory in ModelSim? > As far as I know only generic memory models are recognised, it can't recognise any primitive models. Have a look in the examples/tutorial directory for any examples. Hans www.ht-lab.com > > Thanks for any hint > Udo >Article: 119787
I was part of the team that found the problem, in response to a customer problem, many years after we had shipped the first BRAM. I then documented it and made sure that the appropriate statements got into the datasheet/UserGuide. It is an obscure problem (You have to have CE active nd then violate the Address set-up time, which you would NOT normally do when you want to read consistent data). But I did not think about the DCM losing lock :-( I am convinced that the problem is in all Virtex and Spartan devices (if I learn differently, I will post here. This is a day before a holiday...) I never consider this a fatal flaw, it is really inherent to the BRAM design. And it takes a peculiar set of non-deterministic circumstances to result in an error. And I also do not see any fix that would maintain BRAM access time. That's why I brought this to your attention, in our documentation, as well as in this thread. I will keep you informed about any developments in this area. Peter Alfke, Xilinx Applications On May 25, 1:31 pm, Allan Herriman <allanherri...@hotmail.com> wrote: > On 25 May 2007 10:57:53 -0700, Brian Davis <brimda...@aol.com> wrote: > [snip] > > Thanks for that Brian. This solved a 3 year old bug that I had never > been able to explain before. > > Regards, > AllanArticle: 119788
On May 25, 9:13 am, "Nial Stewart" <n...@nialstewartdevelopments.co.uk> wrote: > > Hi John, > > You're right about the importance of memory sub-system performance -- > > CAD tools have large working sets, so lower memory latency and higher > > caches are quite important. > > Confirmed by an upgrade I did last night from an AMD Althlon 64 3500 > to an Athlon 64 X2 4400. > > Before the change I rebuilt a design I've been working on recently. It's > not that big, Quartus was finished in 4mins 56sec. > > When I ran it with the new processor it took.......4mins 56secs, pretty > much confirming this is memory bound. > > I was a bit disappointed, but at least was able to run Modelsim > at full speed in the background at the same time. > > I also noticed that when my virus scanner kicked off it's weekly scan > I was able to keep working at full speed so I allowed it to finish > for a change :-) > > Nial. Hi Nial, You have to tell Quartus that you want it to use more than one processor. In the GUI, go to Settings | Compilation Process Settings | Maximum processors allowed for parallel compilation and set it to 2. Or you can add the line set_global_assignment -name MAX_PROCESSORS_USED_FOR_MULTITHREADING 2 to your <project>.qsf file. Not sure why you didn't get a speed-up from the higher clock frequency of your processor though. In general, Quartus benefits both from faster processors and from faster memory, since it isn't fully dominated by the speed of either. As for the original posters CPU question, I recommend a system-based on the Core2 Duo processor. It is the fastest uni-processor out there (~30% faster than AMD's best right now), and the second core gives you a noticable (10% to 15%) compile time reduction once you set the assignment above. And as Paul notes above, that compile time reduction with a second CPU is growing with each Quartus release. The quad-core will get you about another 5% compile time reduction now, with more in the future. If you run DSE or multiple Quartus compiles at once you can fully utilize the extra two processors though by simply running another compile (or two) on them. So if you run more than one Quartus at once the quad-core may be worth it, but if not, it isn't worth much more. If you are compiling the largest devices (3S260 and above), then 4 GB is a better bet than 2 GB. Plus it gives you the option of running more than one Quartus at once to use that second processor if you're targeting a smaller device. If you're using Windows, make sure you get a 64-bit version so you can access all that memory from one process (32-bit Windows only lets you at 2 GB per process). Vaughn Betz AlteraArticle: 119789
On 25 mayo, 12:19, cs_post...@hotmail.com wrote: > On May 25, 11:23 am, checo <chec...@gmail.com> wrote: > > I think if you want to try dithering and have a high-bandwidth monitor > or sample-and-hold on an LCD driver, then what you need to do is put a > low-pass filter on the video signal. The idea would be to flatten > your dithering (hopefully at an extremely high rate) out so that from > the perspective of a pixel-timescale, it's relatively flat. > > Of course if you low pass filter it a lot, you'll limit your ability > to display crisp pixel-to-pixel transitions - you can trade off pretty > pictures and blurry text, or ugly pictures and crisp text. That's a very interesting idea. I think it would be kind of tricky to control, since the colors would only soften horizontally and not vertically. But still, it deserves some more research. Regarding your suggestion of soldering components directly on the connector, it sounds great but I don't think I'll be able to find a Hirose FX2 connector down here. I'd have to import it. It would be more cost-effective to import a more "general purpose" module, specially since I am not expecting to make any money out of this project. Anyway, thank you all for your responses! You have been very helpful so far. -checoArticle: 119790
Andrea05 wrote: > Hi everybody, > I have two Virtex4 FX12 Minimodules and I'd like to make them > communicate eachother. > These modules don't have any special transciver (RocketIO, ...) and > are equipped with one PPC. > The communication doesn't require high bandwidth, I need at least 30 > Mbps (more it's better). > The application is designed to implement a special math algorithm so > the communication isn't the focus of the application and thus I cannot > use all the resources for the communication. > I'm using xilinx ISE and XPS to develop the application. > > Any suggestions on what I can I do? Protocols? Cores? Hardware issues > that I should take in account? Design references from where I can > start? How far does this need to travel ? Fibre optic modules perhaps ? Maybe HDLC type protocol, sped up to FPGA speeds. -jgArticle: 119791
[I would have emailed this instead of posting, but <clairemurphs223@hotmail.com> appears to be invalid.] > I've just bought the ML505 and I am looking for some examples of VHDL > code that I can start to play around with and edit. All I can find > are ACE files, which are not that much help to me. I did find the UCF > file that I need, > <http://www.xilinx.com/products/boards/ml505/docs/ml50x_U1_fpga.ucf> > but I am wondering about the other setup parts. From the URL that Antti provided, you can find the Reference Designs link: http://www.xilinx.com/products/boards/ml505/reference_designs.htm The forum has been a little unforgiving of late, as a small number of people have irritated some of the most helpful contributors. As a result, some of the responses have been getting a little more terse ... comp.arch.fpga actually has a bunch of people who are happy to help out when it's clear that the person posting isn't just being lazy, and hasn't just skipped checking google first. Don't be afraid to post in the future, but try to make your questions specific, and try to explain what you have already tried, so that the group takes the questions seriously. > I guess this ML505 board isn't really for people with 0 experience ? Probably not people with 0 experience, but if you have some background with hardware (and you did mention VHDL), it could be a fun place to gain some experience. We all start somewhere. Unfortunately I can't tell you any more about the ML505, as I myself have not used it. Good luck.Article: 119792
Hello Antti,
Can you provide me some example code snippet of the
same? How can I make, sort of, a "global" block ram and let EDK and
ISE refer to the same block ram. The BRAM will act as a FIFO with DDR
controller of EDK being the source and the user logic in ISE being the
consumer but both accessing the "same" BRAM.
Thanks,
Koustav
On May 25, 4:18 pm, Antti <Antti.Luk...@googlemail.com> wrote:
> kousta...@gmail.com schrieb:
>
>
>
> > On May 25, 3:26 pm, Antti <Antti.Luk...@googlemail.com> wrote:
> > > kousta...@gmail.com schrieb:
>
> > > > Hello everybody,
>
> > > > I m able to access/write DDR memory through a
> > > > EDK application. I also want to interface with a ASIC on the FPGA and
> > > > for that I need to pass the data read from the DDR SDRAM to specific
> > > > BRAMs in FPGA. Does anybody has any idea about how to do this? Any
> > > > tips/suggestions will be greatly helpful.
>
> > > > Thanks,
> > > > Koustav
>
> > > you have put an ASIC on top of the FPGA !?
>
> > > if the ASIC is on FPGA then well, is it wireless ASIC, or is the ASIC
> > > connected to the FPGA somehow?
> > Hello Antii,
>
> > I shd have been more clear on that. By ASIC I mean I have
> > a RTL level code implemented in ISE on the FPGA fabric. Now this RTL
> > code uses some BRAMs as for data access and this data is provided by
> > the On-board DDR SDRAM, with the BRAMs acting as buffers. I m
> > interfacing the DDR memory using the EDK with PPC acting as the IO
> > processor. What I want to do is to write the data from the DDR memory
> > to the BRAM and let the RTL code on the FPGA pick up the data from the
> > "same" BRAM.
>
> > Thanks,
> > Koustav
>
> just add some BRAM controller and wire the second port to user logic
> and you are done.
>
> antti
Article: 119793On Fri, 25 May 2007 09:30:58 +0100, "Symon" <symon_brewer@hotmail.com> wrote: >"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message >news:qjkc539kqeipvuab80a6u3ad9vl2aan2sr@4ax.com... >> On Thu, 24 May 2007 12:54:13 -0700, "John_H" >> <newsgroup@johnhandwork.com> wrote: >> >> >> But if the receiver terminates properly, there will be no reflections. >> >> John >> >> >Hi John, >Right. My point exactly. > >Also, many thanks for those links, looks like I found, and posted a link to, >the only manufacturer that shows LVDS outputs including the resistors. >However, if you revisit the pictures in your links, I think you'll see that >they paint a simplified picture. If you go to the National link you posted, >it's clear that the lower MOSFET isn't just a short to ground when it's on. >Otherwise the device would not be meeting the output common mode voltage >spec. There's maybe(?) a resistor in there somewhere, and this provides the >required output impedance. The Analog device links show a current source top >& bottom, which would suggest the Vcm could be anywhere. > >So, I think we need to view these diagrams as not the full picture. However, >I agree with you that it seems most manufacturers aren't all that concerned >with output impedance, which is interesting. >Cheers, Syms. > Yup, the common-mode setting thing is an obvious omission. JohnArticle: 119794
Hello all!
Has anyone had success using LwIP along with some of the xilkernel
functions in a system that is based on the PPC and hard Trimode Ethernet
MAC?
I keep running into a problem where the xtemac driver pulls in some
xilinx header files that collide with unistd.h (pulled in by e.g.
pthread.h).
make -f system.make echo_program started...
powerpc-eabi-gcc -O2 echo/src/socket.c -o echo/executable.elf \
-Wl,-T -Wl,echo_linker_script.ld -g
-I./ppc405_0/include/ -L./
ppc405_0/lib/ \
-lxilkernel -llwip4
In file included from
/home/tools/EDK_9.1/gnu/powerpc-eabi/lin/bin/../lib/gcc/po
werpc-eabi/4.1.1/../../../../powerpc-eabi/include/unistd.h:4,
from echo/src/socket.c:62:
/home/tools/EDK_9.1/gnu/powerpc-eabi/lin/bin/../lib/gcc/powerpc-eabi/4.1.1/../..
/../../powerpc-eabi/include/sys/unistd.h:144: error: conflicting types
for ‘sleep’
./ppc405_0/include/sleep.h:32: error: previous declaration of ‘sleep’
was here
alternately:
make -f system.make echo_program started...
In file included from ./ppc405_0/include/xenv_none.h:60,
from ./ppc405_0/include/xenv.h:73,
from ./ppc405_0/include/xtemac.h:490,
from echo/src/socket.c:61:
./ppc405_0/include/sleep.h:32: error: conflicting types for `sleep'
/home/tools/EDK_9.1/gnu/powerpc-eabi/lin/bin/../lib/gcc/powerpc-eabi/4.1.1/../../../../powerpc-eabi/include/sys/unistd.h:144:
error: previous declaration of `sleep' was here
The above examples were generated by taking the example project
ml403_ppc_lwip_temac_fifo_91i.zip, building it as-is (well, after fixing
the absolute pathnames in the system.xmp). I then opened the "echo"
application and edited its source file echo/src/socket.c. I added
the line
#include <unistd.h>
either between the Xilinx headers and lwip headers (first case) or
before all other headers (second case).
I'm looking to use both lwip and the functions in xilkernel (set thread
priority and mutexes). Unfortunately, the headers needed for the
functions in xilkernel pull in unistd.h.
Note that similar example designs which use xemac (opb_ethernet), such
as xapp434, work fine with and without unistd.h.
I opened a webcase with Xilinx, unfortunately it's the start of a long
weekend so it'll be at least three days before I can get a response. So
I thought I'd try my luck here.
Thanks in advance for any help or suggestions!
ken
Article: 119795On May 25, 3:02 pm, Andrea05 <c...@email.it> wrote: > On 25 Mag, 20:45, austin <aus...@xilinx.com> wrote: > > > > > > > Andrea, > > > Since there are no MGT's, you will need to use some IO's from IO banks. > > > You can use: some number of LVDS 100 ohm differential drivers to > > receivers (one direction only, use two sets of buses), a group of single > > ended IOs matched to a ribbon cable (with ground, signal, ground, > > dignal, this is close to 50 ohms, and can go perhaps 10 meters at the > > speed you need). > > > I suggest the single ended groups, perhaps 8 wires for data, and one > > forwarded clock (for nine signals), and a bus like this for each direction. > > > Clocking these 8 wires at even 10 MHz, would provide 80 Mb/s. At this > > slow a rate, you don't really need to clock forward, but I still would > > suggest it (along with the data, there is the clock on the ninth wire to > > strobe the other end). That way, you don't have to figure out how to > > get the clock off of one pcb, and get it to the other one (for a system > > synchronous solution). > > > Just have registers at each end, and create your own (very simple) > > protocol. If a "data valid" or "data waiting" signal is needed, just > > use another wire. 20 wire ribbon cables are pretty common (ten signal, > > ten grounds). Drive the transmit end with something like LVCMOS 8 mA > > FAST, which is very close to 50 ohms, and there should be no overshoot, > > or undershoot, and the Signal integrity will be good. If that is still > > too strong, 6 mA, and even 4 mA drivers can be selected. > > > The only reason a protocol is required with the MGTs (like aurora:http://www.xilinx.com/products/design_resources/conn_central/grouping... > > is that designers need huge bandwidth, and in order to re-synchronize > > multiple MGTs (channel bonding), a layer is required to manage all that > > stuff. > > > With a simple parallel interface, you pretty much only need to implement > > what you need. > > > To connect these buses to the 405PPC, you will either have to interface > > to the PLB bus, or create an input and output port that is connected to > > the 405PPC. Depending on how fancy you want this to be, it could be as > > simple as input and output instructions (you create the protocol in > > software), or as fancy as a FIFO buffer with DMA into memory mapped into > > the 405PPC data memory (the protocol commonly used here is referred to > > as "flags placed under a rock" which is a reference to one processor > > just waits for a memory location to change, which tells it that the data > > it is waiting for is all there, and ready to be read from memory...the > > transmitting processor sends all the data, and sets the flag to tell the > > receiving processor to pick up the data. > > > Lots of choices here, and not many "standards" as the task is very > > simple, and folks tend to use only what logic they need to in order to > > do the job. > > > Once you pop up to MGTs, there are many more choices, only because there > > are more complex interfaces: ethernet, fibre channel, PCIe, etc..... > > > If you don't need fibre channel, then you don't need media access > > controllers (MAC), etc.http://www.xilinx.com/products/design_resources/conn_central/solution... > > > Austin > > Thank you Austin for your reply, I found it very intresting. > I'll search something about your hints over internet and I'll post the > results (and surely other questions). > > Just another little question. Why, in your opinion, even Xilinx in its > SPI core doesn't support off-chip Master? SPI peripheral seems to fit > well to my design requrements but it has this huge limitation... I > don't understand why... Any ideas?- Hide quoted text - > > - Show quoted text - Andrea, I looked at ds464 OPB SPI interface, and it indicated it supports both master and slave modes. Is slave mode different from off-chip Master mode? -NewmanArticle: 119796
On May 25, 11:55 pm, Newman <newman5...@yahoo.com> wrote: > On May 25, 3:02 pm, Andrea05 <c...@email.it> wrote: > > > > > > > On 25 Mag, 20:45, austin <aus...@xilinx.com> wrote: > > > > Andrea, > > > > Since there are no MGT's, you will need to use some IO's from IO banks. > > > > You can use: some number of LVDS 100 ohm differential drivers to > > > receivers (one direction only, use two sets of buses), a group of single > > > ended IOs matched to a ribbon cable (with ground, signal, ground, > > > dignal, this is close to 50 ohms, and can go perhaps 10 meters at the > > > speed you need). > > > > I suggest the single ended groups, perhaps 8 wires for data, and one > > > forwarded clock (for nine signals), and a bus like this for each direction. > > > > Clocking these 8 wires at even 10 MHz, would provide 80 Mb/s. At this > > > slow a rate, you don't really need to clock forward, but I still would > > > suggest it (along with the data, there is the clock on the ninth wire to > > > strobe the other end). That way, you don't have to figure out how to > > > get the clock off of one pcb, and get it to the other one (for a system > > > synchronous solution). > > > > Just have registers at each end, and create your own (very simple) > > > protocol. If a "data valid" or "data waiting" signal is needed, just > > > use another wire. 20 wire ribbon cables are pretty common (ten signal, > > > ten grounds). Drive the transmit end with something like LVCMOS 8 mA > > > FAST, which is very close to 50 ohms, and there should be no overshoot, > > > or undershoot, and the Signal integrity will be good. If that is still > > > too strong, 6 mA, and even 4 mA drivers can be selected. > > > > The only reason a protocol is required with the MGTs (like aurora:http://www.xilinx.com/products/design_resources/conn_central/grouping... > > > is that designers need huge bandwidth, and in order to re-synchronize > > > multiple MGTs (channel bonding), a layer is required to manage all that > > > stuff. > > > > With a simple parallel interface, you pretty much only need to implement > > > what you need. > > > > To connect these buses to the 405PPC, you will either have to interface > > > to the PLB bus, or create an input and output port that is connected to > > > the 405PPC. Depending on how fancy you want this to be, it could be as > > > simple as input and output instructions (you create the protocol in > > > software), or as fancy as a FIFO buffer with DMA into memory mapped into > > > the 405PPC data memory (the protocol commonly used here is referred to > > > as "flags placed under a rock" which is a reference to one processor > > > just waits for a memory location to change, which tells it that the data > > > it is waiting for is all there, and ready to be read from memory...the > > > transmitting processor sends all the data, and sets the flag to tell the > > > receiving processor to pick up the data. > > > > Lots of choices here, and not many "standards" as the task is very > > > simple, and folks tend to use only what logic they need to in order to > > > do the job. > > > > Once you pop up to MGTs, there are many more choices, only because there > > > are more complex interfaces: ethernet, fibre channel, PCIe, etc..... > > > > If you don't need fibre channel, then you don't need media access > > > controllers (MAC), etc.http://www.xilinx.com/products/design_resources/conn_central/solution... > > > > Austin > > > Thank you Austin for your reply, I found it very intresting. > > I'll search something about your hints over internet and I'll post the > > results (and surely other questions). > > > Just another little question. Why, in your opinion, even Xilinx in its > > SPI core doesn't support off-chip Master? SPI peripheral seems to fit > > well to my design requrements but it has this huge limitation... I > > don't understand why... Any ideas?- Hide quoted text - > > > - Show quoted text - > > Andrea, > I looked at ds464 OPB SPI interface, and it indicated it supports > both master and slave modes. Is slave mode different from off-chip > Master mode? > > -Newman- Hide quoted text - > > - Show quoted text - Andrea, Oh, I see your point. In the features portion, it says it supports master and slave SPI modes, but down in the functional description, it says at this time only off-chip SPI slave devices are allowed. This is because the artifact of software master control arbitration is not guaranteed if off-chip masters were allowed and due to some issue with asynchronous external clocks. I saw a web page where an Altera SPI was connected to an off-chip master as a slave instance. -NewmanArticle: 119797
"Udo" <WeikEngOff@aol.com> wrote in message
news:1180024409.822436.36850@h2g2000hsg.googlegroups.com...
> Hello,
>
> I'm looking for an import utility from Intel Hex to the supported
> formats of ModelSim,
> e. g. MTI or Verilog (Hex).
Well, here's a Systemverilog program to read HEX-80 format into a reg[]
array. Are there different variations of the HEX format? I wrote this
one for Keil's C51 (8051) compiler. You can modify it for your needs:
//
//
// Author: R***** L***
//
// Filename: keil_hex2bin.sv
//
// Date of Creation: Sun May 20 12:14:48 2007
//
// Version: $Revision: 1.1 $
//
// Date of Latest Version: $Date: 2007/05/20 12:14:48 $
//
//
// Description: This is a utility to convert Keil-C51's HEX-80
(*.hex)
// output into a $readmemb compatible ASCII-file.
// For HEX-80 info, see
http://www.keil.com/support/docs/1584.htm
//
// requires Modelsim 6.1g or later (Systemverilog 3.1a)
///////////////////////////////////////////////////////////////////////////////
//
//
// This library is free software; you can redistribute it and/or
//
// modify it under the terms of the GNU Lesser General Public
//
// License as published by the Free Software Foundation; either
//
// version 2.1 of the License, or (at your option) any later version.
//
//
//
// This library is distributed in the hope that it will be useful,
//
// but WITHOUT ANY WARRANTY; without even the implied warranty of
//
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
//
// Lesser General Public License for more details.
//
//
//
// Full details of the license can be found in the file LGPL.TXT.
//
//
//
// You should have received a copy of the GNU Lesser General Public
//
// License along with this library; if not, write to the Free Software
//
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
//
//
//
///////////////////////////////////////////////////////////////////////////////
/*
from http://www.keil.com/support/docs/1584.htm
:10246200464C5549442050524F46494C4500464C33
||||||||||| CC->Checksum
|||||||||DD->Data
|||||||TT->Record Type
|||AAAA->Address
|LL->Record Length
:->Colon
*/
`ifndef INFILENAME
`define INFILENAME "keil.hex"
`endif
module keil_hex2bin();
parameter string infilename = `INFILENAME; // default input filename
localparam int BUFFER_SIZE = 65536; // # address-locations
localparam int LINE_SIZE = 500; // max# bytes per textline
bit [7:0] memory [0:BUFFER_SIZE-1];
typedef struct {
bit flag_eof; // end-of-file
bit flag_colon; // TRUE==valid record, FALSE==no entry
int length; // # bytes in entry
bit [15:0] address;
bit [7:0] checksum;
bit [7:0] record_type;
bit [7:0] data [0:LINE_SIZE-1]; // data
} t_hex80entry;
int fh_in = 0;
int fh_bin_out = 0;
int fh_hex_out = 0; // FILE-pointers
///////////////////////////////////////////////////////////////////////////////
function void open_file( input string name );
// make sure we aren't in the middle of processing another file
assert ( fh_in == 0 ) else
$fatal( 1, "%m(): a file is already open for reading!", name );
fh_in = $fopen( name, "r" );
assert ( fh_in != 0 )
$info( "%m(): initiating read of '%0s'", name ); else
$fatal( 1, "%m(): $fopen( \"%0s\", \"r\" ) failed!", name );
endfunction : open_file
///////////////////////////////////////////////////////////////////////////////
function void close_file( int fhandle );
// make sure we aren't in the middle of processing another file
assert ( fhandle != 0 )
$info( "%m(): closing file-handle 'h%h", fhandle ); else
$error( "%m(): no file was open for reading!" );
$fclose( fhandle );
endfunction : close_file
///////////////////////////////////////////////////////////////////////////////
function t_hex80entry parse_line( input string line );
int error;
int data_byte_count;
bit [7:0] temp_byte, sum;
string phrase; // substring of line[]
int length; // # bytes in entry
bit [15:0] address;
bit [7:0] record_type;
bit [7:0] checksum;
begin
parse_line = '{default:'0};
if ( line.len() < 10 )
return parse_line; // too short, can't possibly be a valid entry
else if ( line[0] !== ":" )
return parse_line; // no starting colon
else if ( line == ":00000001FF\n" )
begin
parse_line.flag_eof = 1'b1; // got end of file!
return parse_line;
end
/* get first few fields
:LLAAAATT
|||||||TT->Record Type
|||AAAA->Address
|LL->Record Length
*/
// if we made it this far, entry appears to be valid!
parse_line.flag_colon = 1'b1;
/*
error = 0;
phrase = line.substr( 1, 2 );
error += $sscanf( phrase, "%02h", parse_line.length );
phrase = line.substr( 3, 6 );
error += $sscanf( phrase, "%04h", parse_line.address );
phrase = line.substr( 7, 8 );
error += $sscanf( phrase, "%02h", parse_line.record_type );
*/
// Modelsim 6.1g workaround - $sscanf can't output to struct/union
error = $sscanf( line, ":%02h%04h%02h", length,
address, record_type );
parse_line.length = length;
parse_line.address = address;
parse_line.record_type = record_type;
// error = $sscanf( line, ":%02h%04h%02h", parse_line.length,
// parse_line.address, parse_line.record_type );
assert ( error == 3 ) else begin
$error("%m(): '%0s' (%0d)", line, error );
parse_line.flag_colon = 1'b0;
end
// now get checksum (last 2 chars of line[])
phrase = line.substr( line.len()-3, line.len()-2 );
// error = $sscanf( phrase, "%02h", parse_line.checksum );
error = $sscanf( phrase, "%02h", checksum );
parse_line.checksum = checksum;
assert ( error == 1 ) else begin
$error("%m(): checksum: '%0s' (%0d)", phrase, error );
parse_line.flag_colon = 1'b0;
end
// now extract the data-payload
error = 0;
for ( int i = 0; i < data_byte_count; ++i ) begin
phrase = line.substr( (i*2)+9, (i*2)+10 );
error += $sscanf( phrase, "%02h", parse_line.data[i] );
end
assert ( error == data_byte_count ) else begin
$error("%m(): DATA: '%0s' (%0d!=%0d)", phrase, error,
data_byte_count );
parse_line.flag_colon = 1'b0;
end
// finally, validate the checksum
sum = 0;
error = 0;
for ( int i = 1; i < (line.len()-1); i=i+2 ) begin
phrase = line.substr( i, i+1 );
error += $sscanf( phrase, "%02h", temp_byte );
sum += temp_byte;
end
assert ( sum == 0 ) else
$error( "%m(): Checksum (%0d bytes) mismatch (%h!=%h)", error, sum,
parse_line.checksum );
end
endfunction : parse_line
///////////////////////////////////////////////////////////////////////////////
task create_file( output int fhandle, input string filename );
assert ( fhandle == 0 ) else begin
$warning( "%m( '%0s' ): fhandle(0x%h) is already in use, overwriting!",
filename, fhandle );
$fclose( fhandle );
end
fhandle = $fopen( filename, "w" );
assert ( fhandle != 0 )
$info( "%m(): creating file '%0s'", filename ); else
$fatal( 1, "%m(): could not create file '%0s'!", filename );
endtask : create_file
initial begin : main
t_hex80entry h;
int n;
string line;
string outfilename_bin, outfilename_hex;
// standalone mode
// assume the last 5-letters of the filename are '.xyz'
// (If that's not the case, then we'll accidentally truncate the
filename!)
outfilename_bin = infilename.substr(0, infilename.len()-5) ;
outfilename_hex = infilename.substr(0, infilename.len()-5) ;
outfilename_bin = {outfilename_bin, ".dua"}; // $readmemb-compat output
outfilename_hex = {outfilename_bin, ".dhx"}; // $readmemh-compat output
open_file( infilename );
n = $fgets( line, fh_in );
while ( n > 0 ) begin
h = parse_line( line );
assert ( n < (LINE_SIZE*2) ) else
$fatal( 1, "Line exceeded internal line-buffer size (%0d chars) !",
LINE_SIZE*2 );
if ( h.flag_colon && (!h.flag_eof) )
$display( "0x%h: %0d bytes, CHK=%h", h.address, h.length,
h.checksum );
n = $fgets( line, fh_in );
// copy entry-data to internal-memory
for ( int j = 0; j < h.length; ++j )
memory[ h.address+j ] = h.data[j];
end
close_file( fh_in );
// Create and dump the contents to $readmemb and readmemh files
create_file( fh_bin_out, outfilename_bin );
create_file( fh_hex_out, outfilename_hex );
for ( int i = 0; i < BUFFER_SIZE; ++i ) begin
$fdisplay( fh_bin_out, "%08b", memory[ i ] );
$fdisplay( fh_hex_out, "%02h", memory[ i ] );
end
$fclose( fh_bin_out );
$fclose( fh_hex_out );
$finish;
end : main
endmodule : keil_hex2bin
Article: 119798possibly, we talked a lot for a while and then .... nothing. He was very interested in Asteroids so I would have expected some response. Possibly the patent lawyers got him ! I should try and get opencores to give me cvs access to the cores, then I could update the ones there. /Mike "Kryten" <kryten_droid_obfusticator@ntlworld.com> wrote in message news:PPo5i.899$lz3.5@newsfe5-win.ntli.net... > "MikeJ" <mikej@fpgaarcade.nospam.com> wrote in message > news:Xqj5i.554$ZA.538@newsb.telia.net... >> on www.fpgaarcade.com you can get the latest version of the T65 core from >> Opencores. >> >> I did a lot of debugging work on the original and still maintain it as >> the original author has vanished. > > Has Daniel Walner been bumped off then? > > > >Article: 119799
On May 25, 5:23 am, futz...@gmail.com wrote: > I think I have a problem with my Cyclone II FPGA and wanted to do a > boundary scan check on the device to see if it is working ok. I looked > for options to perform a boundary scan check using the Quartus > programmer tool and couldn't find anything useful. I have used this > feature on the Xilinx ISE tools and wanted to know if this can be done > on the Altera FPGAs. > > Any suggestions will help. > Thanks > Anup You may try these programs for manual boundary-scan test: Scanseer -- www.scanseer.com UniversalScan -- www.universalscan.com They both allows to monitor and control device's pins in real-time using JTAG. -- SK
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