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Messages from 120100

Article: 120100
Subject: Re: accesing JTAG ports on GPIOs
From: Uwe Bonnes <bon@hertz.ikp.physik.tu-darmstadt.de>
Date: Fri, 1 Jun 2007 08:07:37 +0000 (UTC)
Links: << >>  << T >>  << A >>
maverick <sheikh.m.farhan@gmail.com> wrote:
...
> > > > > > > > > > I have a virtex II board (xc2v1000), unfortunately no jtag signals are

Could you please quote sensibly?

-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 120101
Subject: Re: FIR ON FPGA
From: "Symon" <symon_brewer@hotmail.com>
Date: Fri, 1 Jun 2007 09:10:24 +0100
Links: << >>  << T >>  << A >>
"Bob" <nimby_NEEDSPAM@roadrunner.com> wrote in message 
news:kvWdneJUe7TMD8LbnZ2dnUVZ_qarnZ2d@giganews.com...
>
> "bngguy" <bngguy@gmail.com> wrote in message 
> news:1180492021.200997.137630@i38g2000prf.googlegroups.com...
>> Hi,
>>    I'm working on implementing an FIR Filter on a FPGA (Spartan 3E),
>>
>
> There's an echo in here.
>
> Bob
>
We need an cancelling FIR filter...
Syms. 



Article: 120102
Subject: Re: Can anyone explain the details of the FPGA design flow in ISE
From: Andreas Ehliar <ehliar@lysator.liu.se>
Date: Fri, 1 Jun 2007 08:13:32 +0000 (UTC)
Links: << >>  << T >>  << A >>
On 2007-06-01, subint <subin.82@gmail.com> wrote:
> Hi,
>        I know the the fpga design flow in the ISE tool. But i like to
> know in more details about the process that takes place in each of the
> stages.

In your ISE installation, take a look at the following file:
$XILINX/doc/usenglish/books/docs/dev/dev.pdf


It has a chapter called "Design Flow" which contains what you ask for.
If you want even more details, take a look at the individual chapters
in that document for the tools you are interesting in (e.g. ngdbuild,
map, and par). Also, $XILINX/doc/usenglish/books/docs/xst/xst.pdf contains
information about the Xilinx synthesizer.

/Andreas

Article: 120103
Subject: Re: After PAR simulation, should I assume that it will work on FPGA board?
From: Sandip <sandip.gaikwad@gmail.com>
Date: Fri, 01 Jun 2007 08:26:38 -0000
Links: << >>  << T >>  << A >>
On Jun 1, 10:11 am, Thomas Stanka <usenet...@stanka-web.de> wrote:
> On 1 Jun., 06:52, Sandip <sandip.gaik...@gmail.com> wrote:
>
> > my design on ISE 8.1i. I completed simulation after synthesis then,
> > Translate, Post-map and Post-PAR. I was getting desired results on
> > Simulation using 100Mhz as my clock frequency.
>
> Post-PAR means at least using the netlist instead of rtl code.
> But is useless without timing information. I assume you used timing,
> else start using sdf files.
>
> > Next thing i did was put it on board and verify that design. Input
> > clock was now 8Mhz. But the output I was getting was not desirable.
>
> Identify differences between your testbench and the real world.
> First thing to look: simulate asynchronous inputs switch typically
> with fixed delay to clock, real asynchronous inputs need proper
> handling.
>
> The designflow you described seems to include all necessary steps, so
> I expect the problem to arise from your design.
>
> bye Thomas

Hi Thomas,

I have only two input signals, one is the clock and another is the
reset. All the signals are synchronous to the clock.
Can you please explain in detail how can move ahead using sdf files,
and giving timing constraints. I have presently not used any
constraints other than the clock frequency.

Thanks,
Sandip


Article: 120104
Subject: Re: Problems to simulate (behavioural) in XPS
From: "CTU FEE Jan Krakora" <krakorj@control.felk.cvut.cz>
Date: Fri, 1 Jun 2007 02:48:32 -0700
Links: << >>  << T >>  << A >>
Hi fellows,

no, the problem is not OS specific, because I'm using Windows XP system (due to USB cable, not working under any Linux system). I think the problem is in the simulation IP cores used by ModelSim tool. I think we should inquire of Xilinx corp. after the problem to be solved, as soon as better.

I have also tried to change the OPB core revision to the depricated version 1.10b (older version of 1.10c, the default one), but Modelsim refused me with any warnings and errors. I will analyse it, we will see.

Stay in touch Regards Jan

Article: 120105
Subject: Re: Actel Cortex M1, any info on license fee?
From: Jim Granville <no.spam@designtools.maps.co.nz>
Date: Fri, 01 Jun 2007 22:05:09 +1200
Links: << >>  << T >>  << A >>
Antti wrote:
> Actel is known lying before, they namly claimed that the use of ARM7
> in Actel FPGA is free, actually the FPGA with AES128 that allows the
> use of ARM7 costs 100 USD more then FPGA without the key, and well I
> would not call 100USD "free"
> 
> Now Actel is about to release the smaller Cortex based FPGA (eg
> another key for cortex-enable), again Actel claim its "Free" - I hope
> they are not lying this time, and there extra cost for Cortex is 0.00,
> but if that isnt the case, what is the license fee? is it the same
> 100USD as it is for ARM7 or is it smaller?
> 
> Antti
> 
> PS the 100 USD license fee has been quoted by the distributors for qty
> 1. For 100.000 qty the license fee per chip drops below 2 USD per FPGA
> used.

Hi Antti,
  Of course, they will say they meant 'Separate agreement free',
and 'free' to include on the royalty-paid FPGA.
[ so, you can get FREE into the sentence ]

  You missed one option: Cortex could be MORE than ARM7, it
is after all, newer and smaller FPGA footprint. => likely more $$?

Still, if it is too high a price, you could always either add
an external FLASH uC with ARM, or use an open-source FPGA optimised
CPU.

But I'm sure you alreay knew that, and this was a rhetorical post :)

-jg



Article: 120106
Subject: Can anyone explain the details of the FPGA design flow in ISE
From: subint <subin.82@gmail.com>
Date: Fri, 01 Jun 2007 03:17:00 -0700
Links: << >>  << T >>  << A >>
Hi,
       I know the the fpga design flow in the ISE tool. But i like to
know in more details about the process that takes place in of the
stages.
Thanks in advance
Subin


Article: 120107
Subject: Can anyone explain the details of the FPGA design flow in ISE
From: subint <subin.82@gmail.com>
Date: Fri, 01 Jun 2007 03:17:14 -0700
Links: << >>  << T >>  << A >>
Hi,
       I know the the fpga design flow in the ISE tool. But i like to
know in more details about the process that takes place in each of the
stages.
Thanks in advance
Subin


Article: 120108
Subject: Re: Actel Cortex M1, any info on license fee?
From: Antti <Antti.Lukats@googlemail.com>
Date: Fri, 01 Jun 2007 03:30:16 -0700
Links: << >>  << T >>  << A >>
On 1 Jun., 12:05, Jim Granville <no.s...@designtools.maps.co.nz>
wrote:
> Antti wrote:
> > Actel is known lying before, they namly claimed that the use of ARM7
> > in Actel FPGA is free, actually the FPGA with AES128 that allows the
> > use of ARM7 costs 100 USD more then FPGA without the key, and well I
> > would not call 100USD "free"
>
> > Now Actel is about to release the smaller Cortex based FPGA (eg
> > another key for cortex-enable), again Actel claim its "Free" - I hope
> > they are not lying this time, and there extra cost for Cortex is 0.00,
> > but if that isnt the case, what is the license fee? is it the same
> > 100USD as it is for ARM7 or is it smaller?
>
> > Antti
>
> > PS the 100 USD license fee has been quoted by the distributors for qty
> > 1. For 100.000 qty the license fee per chip drops below 2 USD per FPGA
> > used.
>
> Hi Antti,
>   Of course, they will say they meant 'Separate agreement free',
> and 'free' to include on the royalty-paid FPGA.
> [ so, you can get FREE into the sentence ]
>
>   You missed one option: Cortex could be MORE than ARM7, it
> is after all, newer and smaller FPGA footprint. => likely more $$?
>
> Still, if it is too high a price, you could always either add
> an external FLASH uC with ARM, or use an open-source FPGA optimised
> CPU.
>
> But I'm sure you alreay knew that, and this was a rhetorical post :)
>
> -jg- Zitierten Text ausblenden -
>
> - Zitierten Text anzeigen -

LOL, yes. I guess Actel marketing can brain-wash anybody explaining
how free the free ARM7/Cortex really are.

agreed, the ACTUAL REAL license fee (what customer actually pays, not
what Actel claims) can be even higher than for ARM7 as Cortex is
smaller those the same SoC has more resources free for user design.

And yes, paying 100USD (or even 1USD) for the ARM inside Actel
"license" where a ARM Flash MCUs cost = 1USD, is ridiculous... but
guess its marketing.

Antti












Article: 120109
Subject: Some doubts in the FPGA design flow in the ISE
From: subint <subin.82@gmail.com>
Date: Fri, 01 Jun 2007 03:39:22 -0700
Links: << >>  << T >>  << A >>
Hi,
I am not been able to understand the details of the each stage in the
design flow.
Actually what are the things happening in the mapping stage? During
low-level optimization itself, XST infers specific components (is this
time itself it's checking the available components in the FPGA).
	If I use Synplify tool for synthesis and select v4 fpga  what will
happen if I select the v5 in the ISE during the Mapping. Does it will
select the resource that's available only in the v5?

Thanks in advance
Subin


Article: 120110
Subject: ML402 development board
From: Tomas Davidovic <tomasdavid@centrum.cz>
Date: Fri, 01 Jun 2007 12:48:19 +0200
Links: << >>  << T >>  << A >>
Hello everyone,
I just bought a brand new ML402 development board and found that all 
reference designs are bit streams.
I'd like to start implementing a VGA interface much like the one 
provided as a reference design (ie. load data from CF and show them on 
monitor), so I am searching for either sourcecodes of the reference 
design (in case they are available and I have overlooked them) and/or 
for simulation models for peripherals if these are commonly available.

Any pointers and directions welcome.

Regards,
Tomas

Article: 120111
Subject: Xilinx MIG and verifying UCF files
From: "Simon Heinzle" <sheinzle@inf.ethz.ch>
Date: Fri, 1 Jun 2007 12:58:34 +0200
Links: << >>  << T >>  << A >>
Hi,

I just started to use the Xilinx Memory Interface Generator 1.72 and ran 
into some problems when veryfying the UCF file.

- Target xc4vfx100-ff1517
- DDR II SDRAM is MT47H64M16XX-37E

When doing "Verify my UCF" I always get the errors like
  ERROR: cntrl0_DDR2_A[0] (Address) is not supposed to be allocated in the 
bank 0

My UCF states
  NET "cntrl0_DDR2_A[0]" LOC = G25;

Looking at the Virtex-4 Packaging and Pinout Specification page 265 but 
states that G25 is indeed in bank 5.

Does anybody know what I could be doing wrong?

Thanks in advance!

Cheers,
Simon






Article: 120112
Subject: Virtex-4 troubles after configuration
From: =?utf-8?B?R2FMYUt0SWtVc+KEog==?= <taileb.mehdi@gmail.com>
Date: Fri, 01 Jun 2007 11:07:25 -0000
Links: << >>  << T >>  << A >>
Hi everybody,
After successfull configuration of a Virtex-4 my design has troubles.
But if I reconfigure using the same bitstream the problem is solved.
Did others met this problem? how to solve it?

Thanks in advance


Article: 120113
Subject: Regarding multiple write problem in opencores pci bridge
From: Adnan <madnan.rashid@gmail.com>
Date: Fri, 01 Jun 2007 11:29:19 -0000
Links: << >>  << T >>  << A >>
Hello there, I have been using opencores PCI core and its working very
fine. If someone has already used it please clarify one thing to me.

Before I come to the problem let me explain you the setup I am using,
I have master enabled silicon image Sata controller card on one of the
pci slot and fpga card on the other. I have been successful in using
opencores pci to configure sata card and enabling its DMA mode. I have
attached 1 MB sram at PCI target side. In DMA mode sata controller
reads and writes data in blocks. Basically it is using memory read
multiple multiple command for reading and memory write command (CBE =
7) for writing. For writing sata controller asserts frame and IRDY for
long time and continuously writes data on target.

Now the problem is that sata controllers successfully reads all the
data from memory and transfer it to hard disk but once its writes data
back to sram I get mismatches. I have used chipscope pro and I confirm
that signal terminates properly with exact expected data on PCI bus
but once wishbone master module outputs address and data it contains
few errors. Can you help me with this.

With best regards
Adnan


Article: 120114
Subject: Re: FIR ON FPGA
From: Jon Beniston <jon@beniston.com>
Date: Fri, 01 Jun 2007 04:38:17 -0700
Links: << >>  << T >>  << A >>
> >>    I'm working on implementing an FIR Filter on a FPGA (Spartan 3E),
>
> > There's an echo in here.
>
> > Bob
>
> We need an cancelling FIR filter...
> Syms.

How would I implement that in an FPGA?

Jon


Article: 120115
Subject: Re: FIR ON FPGA
From: "Symon" <symon_brewer@hotmail.com>
Date: Fri, 1 Jun 2007 13:26:10 +0100
Links: << >>  << T >>  << A >>
"Jon Beniston" <jon@beniston.com> wrote in message 
news:1180697897.996367.156200@o5g2000hsb.googlegroups.com...
>> >>    I'm working on implementing an FIR Filter on a FPGA (Spartan 3E),
>>
>> > There's an echo in here.
>>
>> > Bob
>>
>> We need an cancelling FIR filter...
>> Syms.
>
> How would I implement that in an FPGA?
>
> Jon
>
Very carefully...
Syms 



Article: 120116
Subject: Re: Xilinx MIG and verifying UCF files
From: subint <subin.82@gmail.com>
Date: Fri, 01 Jun 2007 12:45:01 -0000
Links: << >>  << T >>  << A >>
Hi,
       I worked with the 1.6 version. That time it had lot of
bugs.Don't worry about the verify UCF.That bug was there in the 1.6
version.They didn't fixed it i think.Go with the model and test it in
the hardware.
regards
subin

On Jun 1, 3:58 pm, "Simon Heinzle" <shein...@inf.ethz.ch> wrote:
> Hi,
>
> I just started to use the Xilinx Memory Interface Generator 1.72 and ran
> into some problems when veryfying the UCF file.
>
> - Target xc4vfx100-ff1517
> - DDR II SDRAM is MT47H64M16XX-37E
>
> When doing "Verify my UCF" I always get the errors like
>   ERROR: cntrl0_DDR2_A[0] (Address) is not supposed to be allocated in the
> bank 0
>
> My UCF states
>   NET "cntrl0_DDR2_A[0]" LOC = G25;
>
> Looking at the Virtex-4 Packaging and Pinout Specification page 265 but
> states that G25 is indeed in bank 5.
>
> Does anybody know what I could be doing wrong?
>
> Thanks in advance!
>
> Cheers,
> Simon



Article: 120117
Subject: using ICAP with the ML310
From: "fabien.goy@gmail.com" <fabien.goy@gmail.com>
Date: Fri, 01 Jun 2007 12:48:47 -0000
Links: << >>  << T >>  << A >>
Hi there,
I am trying to use the ICAP module of my Virtex II Pro. I built a
project with EDK8.1, but when executing the application on the
PowerPC, the ICAP has a strange behaviour.
I can successfully call the XHwIcap_Initialize() function:
here is the XHwIcap structure after initialization

 BaseAdress : 0
 IsReady : 11111111
 DeviceIdCode : 127E093
 DeviceId : 0
 Rows : 50
 Cols : 2E
 BramCols : 8
 BytesPerFrame : 338
 WordsPerFrame : CE
 ClbBlockFrames : 42C
 BramBlockFrames : 200
 BramIntBlockFrames : B0


The problem comes when trying to read a frame:
Status = XHwIcap_DeviceReadFrame(&hwicap, XHI_FAR_CLB_BLOCK, 22, 14);
The value returned is 21, which is "DEVICE IS BUSY"

I read somewhere, there may be a conflict when using ICAP and  JTAG.
Do anybody have any information about this?
I don't use Linux, but a standalone application.

Fabien


Article: 120118
Subject: ise9.1 : partitions with edif flow
From: Tim Morlion <tmorlion@gmail.com>
Date: Fri, 01 Jun 2007 15:03:42 +0200
Links: << >>  << T >>  << A >>
I would like to use partitions with the edif flow. I'm using an older version of
SynplifyPro which does not support partitions. From what I understand, the only
thing Synplify does, is adding a timestamp to the partitions in the edif file.
e.g. (instance or1200_dc_top (viewRef verilog (cellRef or1200_dc_top)) (property
PARTITION (string 1169730682)) )

However after adding this, ngdbuild still reports that no partitions are available.

Does anybody know what exactly has to be added to the edif for the ise tools to
recognize partitions?

Thanks

Article: 120119
Subject: CoreGen Issues ??
From: "Linas Petras" <xx@xx.xx>
Date: Fri, 1 Jun 2007 23:33:51 +1000
Links: << >>  << T >>  << A >>
Has anyone seen an issue with the CoreGenerater that when I try and generate
some of the cores I get a "corrupted" dialog box. By this I mean the "image"
in the left of the dialog box is jumbled so that you can't recognize it as a
image. As I see just "blank" tabs across the top of the dialog box.

I running 9.1SP3. I'm totally at a lose as to what is causing the problem.

Linas



Article: 120120
Subject: Re: Nexys by Digilen xbd file
From: cs_posting@hotmail.com
Date: Fri, 01 Jun 2007 07:14:42 -0700
Links: << >>  << T >>  << A >>
On May 31, 12:41 pm, Stephen Williams <spamt...@icarus.com> wrote:
> I have a demo board of my own that I put together that uses an
> EZ-USB-FX1/2. I've got it to talk USB using the default device
> and sdcc. The source code is really quite simple. I'll put a
> snapshot here:
>
> <ftp://ftp.icarus.com/pub/steve/mmc-20070531.tar.gz>

Steve,

Thank you for posting that.  Could you perhaps provide a little
explanation as to what is there?  In particular, while I see some fx2
code and host code, and can't seem to figure out the relation between
that and the mmc card stuff.  Is there an fx2 interface state machine
or anything like that in the verilog that I'm overlooking?  Also, were
you running the fifo's on the fx2, or did you have the 8051 core
playing middleman?


Article: 120121
Subject: Re: Problems to simulate (behavioural) in XPS
From: ferorcue <le_marq@hotmail.com>
Date: Fri, 01 Jun 2007 14:24:53 -0000
Links: << >>  << T >>  << A >>
On Jun 1, 11:48 am, "CTU FEE Jan Krakora"
<krak...@control.felk.cvut.cz> wrote:
> Hi fellows,
>
> no, the problem is not OS specific, because I'm using Windows XP system (due to USB cable, not working under any Linux system). I think the problem is in the simulation IP cores used by ModelSim tool. I think we should inquire of Xilinx corp. after the problem to be solved, as soon as better.
>
> I have also tried to change the OPB core revision to the depricated version 1.10b (older version of 1.10c, the default one), but Modelsim refused me with any warnings and errors. I will analyse it, we will see.
>
> Stay in touch Regards Jan

Hi friends,

I think that I have the solution, I found it in a xilinx webcase.
in system_setup.do change:
"vsim -novopt -t ps system_conf; set xcmds 1;"





Source:


9.1i EDK ModelSim - Error message: "logic.vhd(359): (vopt-1144) Value
0 is out of std.standard.natural range 1 to 32"
04/24/07 11:14:13

Problem Description:

Keywords: optimization, -vopt, -novopt

I am trying to simulate my EDK system. When I run the simulation in
ModelSim 6.2b, I receive an error message similar to the following
during the optimization phase:

"Error Message:
---------------------------------------

D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_v20_v1_10_c/hdl/vhdl/
opb_v20.
vhd(550): (vopt-1144) Value 0 is out of std.standard.natural range 1
to
32.
# ** Error:
D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_arbiter_v1_02_e/hdl/vhdl/
park
_lock_logic.vhd(359): (vopt-1144) Value 0 is out of
std.standard.natural
range 1 to 32.
# ** Error:
D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_arbiter_v1_02_e/hdl/vhdl/
park
_lock_logic.vhd(429): (vopt-1144) Value 0 is out of
std.standard.natural
range 1 to 32.
# Optimization failed
# Error loading design
# Error: Error loading design
# Pausing macro execution"

I was able to simulate this same design using a previous version of
ModelSim (for example, 6.0a and 6.2a). The previous version of
ModelSim did not include this optimization phase. What could be the
problem?
Solution 1:
The problem is that in the later version of ModelSim, it is
automatically inserting the -vopt command by default, which clashes
with the EDK IP files for the EDK cores. This command performs global
optimization on Verilog and mixed-HDL designs after they are compiled,
which is not necessary for the EDK IP models.

You can work around this issue by inserting the -novopt command in the
"do file" that you are using to run the simulation. Alternatively, you
can work around this issue by setting the "modelsim.ini" variable
"VoptFlow" to 0 (zero). The "modelsim.ini" files are located in the c:
\<modelsim>\, c:\<ise_compiled_libraries> and c:
\<edk_compiled_libraries> directories



Article: 120122
Subject: Re: Cyclone 3 Starter Board Question
From: fpgabuilder <fpgabuilder-groups@yahoo.com>
Date: Fri, 01 Jun 2007 14:34:27 -0000
Links: << >>  << T >>  << A >>
On May 31, 11:36 pm, Antti <Antti.Luk...@googlemail.com> wrote:
> On 1 Jun., 07:41, fpgabuilder <fpgabuilder-gro...@yahoo.com> wrote:
>
>
>
> > On May 31, 4:42 pm, ghel...@lycos.com wrote:
>
> > > On May 31, 3:43 pm, fpgabuilder <fpgabuilder-gro...@yahoo.com> wrote:
>
> > > > Anyone know how the USB Blaster cable loads data to the C3 fpga on the
> > > > board?  The schematic shows a CPLD between the FPGA and the USB port.
> > > > There is a USB to parallel chip between the cpld and the usb port.
> > > > But I do not see any serial or parallel data going to the fpga.
>
> > > > I wish Altera added more details to the starter kit documentation.
> > > > There is all this source code but it is encrypted.  So  cannot even
> > > > look at that.
>
> > > > TIA
> > > > -sanjay
>
> > > That CPLD along with the FT245 is the "embedded USB Blaster".  You
> > > won't see any lines to the FPGA except for the JTAG leads.  (I found
> > > the JTAG lines on the schematic - look again.)
>
> > > The documentation looked pretty complete to me.  For the Xilinx board,
> > > the page of schematic with the USB loader is *missing*, and that area
> > > of the layout is obscured.
>
> > > Both companies used to ship separate dongles with their eval boards.
> > > But the plastic case of the dongle is the most expensive part,
> > > followed by the JTAG leads.  By leaving those out, they can add the
> > > USB programmer for almost nothing.
>
> > > It's possible that both companies contracted out the design of their
> > > USB programming pods, so they can't (legally) distribute the
> > > information on the device.  (Both companies make a ton of money
> > > selling IP; you have to understand that they will respect the IP
> > > rights of others.)
>
> > > Do a web search.  There are a number of people actively tring to
> > > reverse engineer both dongles.  At least until they discover hat
> > > they're spending 100's of hours to duplicate a gizmo that can be had
> > > for $50...
>
> > > G.
>
> > Sorry I wasn't clear.  By data I did not mean the configuration or
> > jtag stream.  Not sure if you are familiar with the C3 starter board.
> > But they have something called control panel, which you use to test
> > the dram access besides other things.  You can read and write to the
> > sdram.  Store entire files, etc.  And the only host interface I see
> > for this is the usb interface.  But I do not see any data lines.  So
> > that is what I mean by data.
>
> > Please let me know where to look if you find that in their
> > documentation.
>
> > Thanks.
> > Best,
> > -sanjay- Zitierten Text ausblenden -
>
> > - Zitierten Text anzeigen -
>
> well, there is no need for more then JTAG lines ;)
> Altera FPGAs can have user logic in fabric connected to the JTAG TAP,
> so the same JTAG pins can be used to talk to the user app as well.
> this is how signaltap works as example
>
> Antti

Thanks Antii.  I had suspected this.  And I think this is a cool
feature for low bandwidth operations such as serial communication.  I
am thinking how can I use this in my application?  Please let me know
if you have any pointers.

TIA.
-sanjay


Article: 120123
Subject: Cyclone 3 Starter Board connector?
From: Philipp Klaus Krause <pkk@spth.de>
Date: Fri, 01 Jun 2007 16:47:38 +0200
Links: << >>  << T >>  << A >>
The Cyclone 3 Starter Board has this strange "High-Speed Mezzanine 
Connector (HSMC)".
I'd prefer something simpler, such as a 0.1" header.  Are there any 
adapters / daughterboards  available?

Philipp

Article: 120124
Subject: Bootloader in BRAM to run a program loaded in the DDR
From: Pablo <pbantunez@gmail.com>
Date: Fri, 01 Jun 2007 08:03:19 -0700
Links: << >>  << T >>  << A >>
Hi, I want to ask if it is possible to load a program in the BRAM able
to run another main program (with PowerPC) in the DDR Sdram. I know
this is done by XMD but I would like another launcher program in bram
instead of running the XMD of Xilinx.

Regards.




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