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Joseph Samson wrote: > > Pouria wrote: > > > >>HI Everybody! > >> > >>I'm having a timing problem interfacing with my SDRAM bank. I'm using > >>256Mb MT48LC16M16 SDRAM from Micron, and want to operate them at 100 Mhz. > >>So far I have only been working at 40 Mhz. > >> > >>I'm using two DLLs (inside my VirtexII) one for clocking the FPGA and one > >>for clocking the SDRAM. The design works if I DON'T use the external > >>feedback from SDRAM_Clk to one of the DLL, but it fails as soon as I use > >>the feedback (Which according to Xilinx should be the correct way to > >>terminate clock Skew). > >> > >>The feedback to the other DLL is taken from clock output of it self, and I > >>have used IBUG/OBUF/BUFG so that is not the problem. > > As Gabor pointed out, register all signals in the IOBs and use fast slew > rate drivers. I highly recommend using the DDR IOB flipflop to generate > the SDRAM clock. That dramatically improved my SDRAM design, and now I > generate all external clocks that way. You might have good luck sending > an inverted clock to the SDRAMs. I don't use the clock feedback. > > Once you get the design running, experiment with lowering the output > drive. The default is 12mA, but my layout allows me to go as low as 4mA. > > --- > Joe Samson > Pixel Velocity That's a good point about using the IOB flip-flop. In Virtex II you can use the DDR flip-flop to output a clock at the same frequency that clocks the flip-flop. The timing will match clock-to-out on other IOB flip-flops that use the single output flip-flop (it's really the same hardware). If you use a single clock in the design you'll have hold-time issues at the SDRAM because your data, address, and control signals will coincide with the rising clock edge (0 hold time). Use a DCM to generate a delayed clock for everything other than the SDRAM clock outputs. If the delay between clocks is small, just enough to meet SDRAM hold time requirements, you shouldn't have hold time issues on your input registers (but don't assign NODELAY to the input nets). Also note that lowering the output drive increases the output clock to Q time. You can use this selectively to intentionally add skew between signals if necessary (but not a lot). I often drive clock outputs with higher current to slightly advance the timing with respect to other signals. Good Luck, GaborArticle: 94451
Hi, I've got a Computer with Phoenix Frame Grabber, whenever i try to program (using IMPACT) the 1800 series serial PROMS on a Xilinx Board the programming fails. But if i use some other computer without the Phoenix board, it works without any problem. Did neone ever came across a similar problem. By the way, Even with the Phoneix card in the computer, the programming works sometimes, like maybe 2/10 times. So at this point i am just clueless as to why i am having trouble programming with a combination of IMPACT, PHOENIX and AMD DUAL PROCESSOR MOTHERBOARD. If neone has ne input, that would be appreciated ... thanks.Article: 94452
Jim Granville wrote:
> I'll see what I can find, and email some to you.
> Such simple examples are not as common as they should be,
> on vendors web sites.
For those interested, I have started a "MyHDL Cookbook",
with a first example:
http://myhdl.jandecaluwe.com/doku.php/cookbook:jc2
--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
From Python to silicon:
http://myhdl.jandecaluwe.com
Article: 94453I'm running Linux on powerpc on the virtex-ii pro. One of my ACE file runs just fine. I was able to login to Linux without any issue. I then created another base system with gpio and generated an ACE file. Everytime I use this new ACE file, Linux boot hangs during partition check. Partition check: xsysacea: then nothing shows up. Does anyone know what error this is? Thanks a lot! -EricArticle: 94454
Run Window Task manager View->Select columns. Select USER and GDI Objects. Now sort on them. If any process is consuming a lot , then it could be problem. There is a limit of 64K on them. One such process is wisptis.exe which get lauched when running acrobat on some WinXP systems. Also you may need this patch forWInXP "MFC applications leak GDI objects on computers that are running Windows XP" http://support.microsoft.com/?id=319740Article: 94455
John_H wrote: > >You're just more effective at pushing his buttons than most. > For me, posting about Cin/ DCI problems is all it takes to set him off. Go read that thread I'd linked to as an example of his posting etiquette, which went something like this: Peter A. : Series DCI has zero additional system power Brian : Except for the 200 mW/bank overhead Austin : ( leap in with guns blazing ) Brian : ( return fire ) > >Along those lines, I love the riddle that leaves most >americans perplexed but non-Americans laughing: > "Q: What does an American do with a question? > A: He answers it." > Some questions are best left un > > Conspiracy theory aside, have you been involved with standards development? > One step removed, working with the guy who's on the committee, to build the T&M equipment needed for verification, or the equipment needed to test the equipment needed for verification. > > I don't doubt that there are compromises made that favor existing > silicon because the owners of that silicon (or those transmission systems) > want to revamp less of their technology. A good compromise is reached when > nobody's happy. > There are certainly politics, but claiming that a basic PCI electrical loading specification is rigged specifically to exclude FPGA vendors is a bit (insert non-offensive adjective of choice here). BrianArticle: 94456
Ray Andraka wrote: > > OK, I wasn't aware of those issues. So far, I haven't used DCI because > of die temperature concerns, so I haven't stumbled across the hidden > issues. > After last checking them in June '05, I summarized the poor state of the DCI Power Answer Records over here: http://groups.google.com/group/comp.arch.fpga/msg/f66ab4d7063f5c3f BrianArticle: 94457
Austin, > > Just when I get serious with you (and treat you like the > experienced designer you purport to be), > You've already called me a novice, no need to repeat yourself. > > you move onto another subject, and pour forth more vehemence. > Check the message timestamps, I posted that response to you about ten minutes BEFORE I replied to Ray. > >http://xgoogle.xilinx.com/search?getfields=*&btnG=Google+Search&outpu... > >is the link to the 117 answers on Virtex II DCI... (to counter your >"poorly documented" comment..." Scattered, incomplete, and inaccurate Answer Records are not proper documentation of such a serious problem as has V2 DCI. We've had that discussion before, too. >I acknowledge you had a less than satisfactory experience (with Virtex >II DCI), and I am unlikely to change your mind about Xilinx, or their >business practices, or Xilinx honesty policy. > >For that, I am truly sorry. I don't want an apology for past documentation problems, I want you (Xilinx) to fix those problems so others don't bang into the same things on old & new parts. It didn't really bother me that I hit those problems in early 2003, three years after the V2 product launch. Or that a months long webcase produced no solid answers. Or that six months later, all the CR's I'd filed hadn't corrected the documentation/Power Estimator/Xpower problems. What really ticked me off is that when I personally took the time and effort to summarize all those problems in that "LVDS_25_DCI Top Ten List" post here in Oct. 2003, you launched the first in a series of attacks on me, when I've mentioned related Cin/DCI Power/FreezeDCI problems here on the newsgroup. BrianArticle: 94458
Hi folks, are there any DSP soft processor cores for fpgas available. I have done a search and only found 32 bit RISCs but no DSP processor cores. Thanks in advance SudhirArticle: 94459
Is it me or has prices for dev boards risen dramatically this last couple of weeks? Specifically, after avnet has now chewed up memec, they have hiked dev board prices ($100+) significantly on all the boards that I watch. I guess, supply and demand...Article: 94460
Austin, > >8 banks, time 200 mW = 1.6 watts. At 1.5 volts that would be one ampere. > A little exageration here? At 3.3 volts, that would be less amperes? > IIRC, 2A extra per board, or about 400 mA extra per chip @2.5V VCCO, for both bank overhead and parallel termination error, five 2V250's, about 20 LVDS_25_DCI per chip. > >This has since been fixed in later families so that freeze is done better. > >The latest family DCI is improved in these areas. > Documentation thereof can be found where? > >Ah, finally we have some facts! > Funny how my facts of yesteryear have become your facts of today. ---------- [Austin_2004]: Freeze DCI has nothing to do with it. [Brian_2004]: Using FreezeDCI in the V2 affects both the behavior and repeatability (config-config & part-part) of static DCI power consumption, both for per-bank overhead, and particularly for per-input parallel terminators [Austin_2006]: Freezing it also stopped the reference resistor search, which could (randomly) increase the ref resistor power (in V2). ---------- [Brian_2004]: As each bank has its' own independent CCLK type oscillator driving the tap adjustments, you end up with a random sampling of the possible DCI adjustment states for each bank. As I understood it, the newer devices having DCIUpdateMode were going to cleanly stop the DCI updates in all banks at a known state rather than randomly halting them as with FreezeDCI. [Austin_2006]: Standards which crossed a bank also had issues, as the controllers were independent (one for each bank, not synchronized). This has since been fixed in later families so that freeze is done better ---------- [Austin_2004]: DCI updating is only an issue when you cross between two banks, and even then only with the parallel interfaces where it adds some small amount of jitter [Brian_2004]: On the other hand, with FreezeDCI on, the resulting random DC offset for the parallel terminators will probably cause problems for the single ended standards with accurate terminator VTT requirements (whether in one or multiple banks). [Austin_2006]: which led to some problems with specific applications (primarily wide buses with extremely critical timing using HSTL or SSTL parallel standards). ---------- Brian References: [Austin_2004]: http://groups.google.com/group/comp.arch.fpga/msg/9c36b288d94edb99 [Brian_2004] : http://groups.google.com/group/comp.arch.fpga/msg/4a7fa8984b3395db [Austin_2006]: http://groups.google.com/group/comp.arch.fpga/msg/46d9b8ff632b6e5fArticle: 94461
thanks for the info. C++ would be good to see. -- ---------------------------------------------- Posted with NewsLeecher v3.5 Beta 2 * Binary Usenet Leeching Made Easy * http://www.newsleecher.com/?usenet ----------------------------------------------Article: 94462
Hi Antti, Thnaks for your reply I checked this excellent site : http://www.ulrichradig.de from Ulrich Radig And there is there a video showing SMD IC soldering : http://www.ulrichradig.de/gfx/video/SMD_einloeten.wmv Some points are unclear for me t : what kind of glue does one put on the IC pads at the beginning ? And how does one put the solder ? directly as it seems from the video ? "Antti Lukats" <antti@openchip.org> wrote in message news:dq3l31$oo8$1@online.de... > "Jerome" <nospam@nospam.fr> schrieb im Newsbeitrag > news:43c54fb6$0$11500$636a15ce@news.free.fr... >> Hi Antti, >> Do you use special tool(s) to solder a BGA pulled IC ? >> Or only a magnifying glass ? >> > no tools and no magnfier either :) > > 1.27mm BGAs are pretty easy to handle, but it balls up > solder the GND at the corners then some VCCINT > and VCCAUX, the JTAG some IO pins and eval board > is ready ! I had some pictures of one such board online > sometimes ago but at the moment I cant find them > > 1mm BGAs are harder, and with 0.8mm is better not > to try it at all. I tried once to solder the PCI interface > pins of the TI's TMS6205 DSP in 0.8mm BGA and > there I failed, maybe was too impatient. > > Antti >Article: 94463
Zara wrote: > BTW, someone from Xilinx told me some time ago that EDK 8.1 will, at > last!, support C++. I hope it will. C++ works for me in 6.3 and 7.1 What doesn't work? I had to add extern "C" to a few header files. I don't use many C++ features, however. Alan NishiokaArticle: 94464
DerekSimmons@FrontierNet.net wrote: > Have you looked at Altera's HardCopy device? It allows you to migrate a > FPGA (Startix/Cyclone) design to a HardCopy device. It is suppose to > have some of the advantages of ASIC device (price was one of them). Stratix/Stratix II, rather. The HardCopy devices are definitely high end. Definitely seems like a nice migration program, though. -hpaArticle: 94465
Christopher Cole schrieb: > I like the new Xilinx Webpack 8.1i interface under Linux, it works great. > I am running the Webpack under Gentoo Linux with a 2.6.14 kernel. AFAIK, the Win32 version of the Webpack contains Modelsim. Does the Linux version contain it too? Bye TomArticle: 94466
Thank you for these answers. <amyler@eircom.net> a écrit dans le message de news: 1136996163.408082.219550@g14g2000cwa.googlegroups.com... sjulhes wrote: > Hello everybody, > > I would like to know if the PLX PCI9656 can support the following PCI modes > upon the slot it is plugged in : > 3.3V 64 bits / 66 Mhz > > 3.3V 32 bits / 33 Mhz > > 5V 32 bits / 33 Mhz > > Thank you for your fast answer. > > Stéphane Hi Stephane, Have you looked at the datasheet for this information? http://www1.plxtech.com/TEMP/57839/9656BA_DataBook_v1.1.pdf The electrical spec' section describes how to use it in a 5V PCI system. So it looks like yes yes and yes are your answers. Best regards, AlanArticle: 94467
Hi,I have a problem that i can't use ISE4.2 download design in CPLD or FPGA with win2000 SP4 system.The iMPACT of ISE4.2 accessories can't find the download cable.I think this is the software problem,because with ISE6.2 all is OK.What is the solution of confict between ISE4.2 and win2000 SP4.Article: 94468
Hi,in my project,i need some bufs to delay some signals,but after synthesising,the code:#20 does't have any affects.Is there some way to keep the delay?For example,some constraint for synthesis or other.Article: 94469
Actually I'd love to get XC4VFX20 support into the webpack. RocketIO looks nice for ideas I have...:-) "johnp" <johnp3+nospam@probo.com> wrote in message news:1137002330.668018.39700@f14g2000cwb.googlegroups.com... > I'm surprised that the Webpack 8.1 only supports one Virtex-II Pro > part. All > of the other families seem to have OK coverage on the lower-end parts, > why > is this family supported so poorly? > > I wonder if Xilinx has any plans to expand support for the V2Pro > family? > > Of course, I'm using the XC2VP7, so I can't try out the new s/w. Sigh. > > > John Providenza >Article: 94470
"Jerome" <nospam@nospam.fr> wrote in message news:43c54fb6$0$11500$636a15ce@news.free.fr... > Hi Antti, > Do you use special tool(s) to solder a BGA pulled IC ? > Or only a magnifying glass ? > Check out the following page for more SMD info/ideas/fun http://www.sparkfun.com/tutorial/SMD_Printing/SMD_Printing.htm and http://www.sparkfun.com/tutorial/ReflowToaster/reflow-hotplate.htmArticle: 94471
On 11 Jan 2006 22:22:55 -0800, "Alan Nishioka" <alan@nishioka.com> wrote: >Zara wrote: >> BTW, someone from Xilinx told me some time ago that EDK 8.1 will, at >> last!, support C++. I hope it will. > >C++ works for me in 6.3 and 7.1 What doesn't work? >I had to add extern "C" to a few header files. I don't use many C++ >features, however. > >Alan Nishioka Whenever I use templates, chaos begins... ZaraArticle: 94472
wuyi316904@gmail.com =E5=86=99=E9=81=93=EF=BC=9A > Hi,in my project,i need some bufs to delay some signals,but after > synthesising,the code:#20 does't have any affects.Is there some way to > keep the delay?For example,some constraint for synthesis or other. if the signal is wide enough u can use flip_flop it will delay the signal one clockArticle: 94473
Xilinx have an updated Impact, which fixes this (sorry, I don't have the URL to hand). Given that, it works fine for me. wuyi316904@gmail.com wrote: > Hi,I have a problem that i can't use ISE4.2 download design in CPLD or > FPGA with win2000 SP4 system.The iMPACT of ISE4.2 accessories can't > find the download cable.I think this is the software problem,because > with ISE6.2 all is OK.What is the solution of confict between ISE4.2 > and win2000 SP4. >Article: 94474
foag@iti.uni-luebeck.de schrieb am 11.01.2006 17:49: > Hi Antti, > if I have a look into the generated "View RTL Schematic" (*.ngr), I can > see the input port "lclk" Removal of signals due to optimization happens at later stages in the flow, so what you see in the schematic view is not really representative. If "lclk" is not used anywhere in your design, it is optimized away. The tools can backtrace something like that several stages, so it doesn't have to be really obvious. As an example: if you clock a single flipflop with "lckl", but the asynchronous reset for the FF is permanently active, some tools may recognize that the clock is not really relevant and remove it. You should check your design for things like this, or maybe post a code snippet here so we can have a look. There's a configuration switch you can set to "Allow unmatched LOC"-attributes which would allow you to finish the flow despite of the error, but that's not what you want since obviously there's something wrong with your design which you otherwise wouldn't notice. cu, Sean
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Compare FPGA features and resources
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