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On a sunny day (10 Jan 2006 14:39:40 -0800) it happened "Leon" <leon_heller@hotmail.com> wrote in <1136932780.443620.83150@g14g2000cwa.googlegroups.com>: >Took me about 30 minutes. I do have 4 Mbit/s broadband, though. > >Leon > I have it now, it speeded up all of the sudden, or must have reported wrong, have the docs as separate pdfs too. Will look at it later, almost midnight now :-)Article: 94376
I haven't been able to use my old testbenches with the new ISE simulator. I get an error saying that the input file was not generated by ISE. True, I used Paint to generate BMP files, and then I use to use ModelSim to simulate the results and output to another BMP file. I put in a case to Xilinx about this and the engineer told me how to switch the ISE simulation to ModelSim, but said that the "future" was with the ISE simulator. This raises some questions: Will ModelSim be distributed free with the webpack? Is there any way to open an input file in the new ISE simulator? And if not, will there ever? Brad Smallridge brad at aivision.com some of the code: type char_file is file of character; -- one byte each file my_file : char_file; file my_file2 : char_file; constant file_name : string := "infile.bmp"; constant file_name2 : string := "outfile.bmp"; begin file_open(my_file, file_name, read_mode); file_open(my_file2, file_name2, write_mode);Article: 94377
Hi, please guide me on two beginner-level questions. A program writes an integer onto BAR0 on the Stratix PCI board. I wish the fpga design to read this value from BAR0, and store it (and display the last 8 bits on the LEDs on the board). 1. How do I trigger my design whenever something is written onto BAR0? 2. How can I read from BAR0 from my verilog design? Thanks a lot, MohitArticle: 94378
Eric wrote: > Hi All, > > I successfully ported Linux to the powerpc on a virtex-ii pro board. > Now I'm having trouble writing sample applications that can test > devices on the board (switches, LEDs, etc). Is there a way that we > can port elf files generated by EDK to run on Linux? I'm able to > cross compile simple programs using standard C libraries, but > things don't work out when I use Xilinx libraries. I've tried cross > compiling a sample program that tests some devices on the board, > but couldn't get libraries to work correctly. Is there any work needs > to be done to the libraries before I can use them? I'm new to this sort > of > embedded environment. Any pointers? Thanks plenty. > I can't think of what you would want to use the Xilinx libraries for. For simple devices, presumably they are located at some memory location determined by your FPGA code. So you mmap the location and then write/read the devices. Or am I misunderstanding something? What in the libraries are you trying to use?Article: 94379
Brad Smallridge wrote: > I haven't been able to use my old testbenches with the new > ISE simulator. I get an error saying that the input file was > not generated by ISE. True, I used Paint to generate BMP > files, and then I use to use ModelSim to simulate the results > and output to another BMP file. > > I put in a case to Xilinx about this and the engineer told me > how to switch the ISE simulation to ModelSim, but said > that the "future" was with the ISE simulator. I hadn't even realized that there WAS an ISE simulator! > This raises some questions: Will ModelSim be distributed > free with the webpack? ModelSim XE III is a download (http://www.xilinx.com/ise/optional_prod/mxe.htm) that's separate from both WebPack and ISE, although the current version is included in the ISE distibution. I never run ModelSim from within the Xilinx tools, and I never allow the Xilinx tools to create a test bench. > Is there any way to open an > input file in the new ISE simulator? And if not, will there > ever? dunno. -aArticle: 94380
robnstef@frontiernet.net wrote: > Ray, > When this happens is there ANY process that is taking an obsurd amount > of CPU processing, like CSRSS.EXE? > Rob > No, that's the weird thing. Both the processors (it is a dual core AMD 64x2) and the memory are showing fairly low utilization...less than 50% for each.Article: 94381
Austin, > > Well, we have agreed to disagree: you have labeled me "absurd" > and I will consider you a "novice." > There you go with the name calling again. I did not say YOU were absurd, I said your POST was absurd. Perhaps some day you will understand the difference. > > And please be so kind to keep us apprised of all of the "facts." > You can't handle the facts; when forced to face them, you resort to childish name calling and tantrums. Oh, and I'm still waiting for your promised apology from this charming post you made in August '04, where you wrote [1]: > >I would appreciate it if you did detail every single omission, >distortion, or mis-representation. > >In fact, I demand it, or an apology. As you know, when I make a >mistake, I own up to it immediately. I expect no less from others > Surely you remember, that's the thread where you attacked and ridiculed me for pointing out that the S3 DCI overhead of up to 2W per chip might be of concern in a small S3 design. Funny to read that thread again now, when you're claiming that a 5W advantage in the biggest, baddest V4 is the greatest thing since sliced bread. Strangely, when I pointed out exactly what you had omitted, distorted, and mis-represented [2], you failed to cough up an apology... Brian [1] http://groups.google.com/group/comp.arch.fpga/msg/dd96995737504055 [2] http://groups.google.com/group/comp.arch.fpga/msg/4a7fa8984b3395dbArticle: 94382
Are you running any anti-virus software? I've heard of AV packages causing system stability problems. Perhaps you can shutdown your AV software and see if the problem disappears. Frankly, I'm all out of ideas. You can try to increase the stack numbers (as viewed in the registry) by a bit to see if that solves your problems. "Ray Andraka" <ray@andraka.com> wrote in message news:DMYwf.44515$Mi5.6758@dukeread07... > robnstef@frontiernet.net wrote: >> Ray, >> When this happens is there ANY process that is taking an obsurd amount >> of CPU processing, like CSRSS.EXE? >> Rob >> > > No, that's the weird thing. Both the processors (it is a dual core AMD > 64x2) and the memory are showing fairly low utilization...less than 50% > for each.Article: 94383
Any issues? -- ---------------------------------------------- Posted with NewsLeecher v3.5 Beta 2 * Binary Usenet Leeching Made Easy * http://www.newsleecher.com/?usenet ----------------------------------------------Article: 94384
"Jan Panteltje" <pNaonStpealmtje@yahoo.com> wrote in message news:dq104s$h0r$1@news.datemas.de... > http://direct.xilinx.com/direct/webpack/81/WebPACK_81i_SFD.sh > > server maxes out at 30 kB / second (= > 7 hours)? > (My DSL can do > 10 x that). > > Should I try some otrher time or leave it overnight? > Or is it so hot that now everybody is at it :-)? Hi guys, I could get it at about 32kB/sec, so it started to download. But I can't say why, since a few hours ago it downloads at variable speed, only up to 12kB/sec. Maybe many people on it now. Regards, JaaCArticle: 94385
"Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message news:11s8gh7mt967846@corp.supernews.com... >I haven't been able to use my old testbenches with the new > ISE simulator. I get an error saying that the input file was > not generated by ISE. True, I used Paint to generate BMP > files, and then I use to use ModelSim to simulate the results > and output to another BMP file. > > I put in a case to Xilinx about this and the engineer told me > how to switch the ISE simulation to ModelSim, but said > that the "future" was with the ISE simulator. I thought it was the other way, instead... Any opinions about it? JaaCArticle: 94386
one it will not work ISE, EDK and ChipsCope must be same major release anttiArticle: 94387
Thank you veru much. Stéphane. "John McCaskill" <junkmail@fastertechnology.com> a écrit dans le message de news: 1136917580.080616.229680@f14g2000cwb.googlegroups.com... sjulhes wrote: > Hello, > > We have a 2VP40 ( 15.5Mbits configuration ) to configure through a 8 bits > 90ns flash by a CPLD. > I try to find what time has the PCI IP to respond to PCI boot board > identification process before been ignored ? > This will give the time I have to configure my FPGA. > > Does someone has information on this allowed time ? > > Thanks. > > Stéphane. For PCI 2.3, and revision 1.0a of the PCI-X spec: 100 ms from power valid to RST# high. For PCI 2^25 clocks from RST# high to first configuration access. For PCI-X 2^26 clocks from RST# high to first configuration access. Regards, John McCaskillArticle: 94388
I just can't find it in the spec ! Can someone give me the right section ? thanks. Stéphane. "John McCaskill" <junkmail@fastertechnology.com> a écrit dans le message de news: 1136917580.080616.229680@f14g2000cwb.googlegroups.com... sjulhes wrote: > Hello, > > We have a 2VP40 ( 15.5Mbits configuration ) to configure through a 8 bits > 90ns flash by a CPLD. > I try to find what time has the PCI IP to respond to PCI boot board > identification process before been ignored ? > This will give the time I have to configure my FPGA. > > Does someone has information on this allowed time ? > > Thanks. > > Stéphane. For PCI 2.3, and revision 1.0a of the PCI-X spec: 100 ms from power valid to RST# high. For PCI 2^25 clocks from RST# high to first configuration access. For PCI-X 2^26 clocks from RST# high to first configuration access. Regards, John McCaskillArticle: 94389
Athena wrote: > Hi all, > > At present, I am using Xilinx SPARTAN XC3S1500 FPGA with Micro MT46V16M16 to do some projects. As my programme is very large, there is not enough space to put them in the bram, so I have to put them in the ddr sdram. However, I found that when the programme is in the ddr sdram, the speed is 20 times lower than in the bram. I couldn't endure it. > > Who knows how to speed up the programming in the ddr sdram? In addition to Antti's suggestion of enabling caches (absolutely essential), try using Xilinx's new mch_opb_ddr controller, and the CacheLink interfaces. These bypass the OPB bus for CPU memory accesses, and also allow wider cachelines than OPB transactions. We see an instant 2X speedup in real terms on uClinux systems with the MCH caches. All the info is in the MicroBlaze reference guide. CacheLink is also supported in Base System Builder, I beleive. There were some issues with the mch_opb_ddr controller in EDK7.1, no doubt fixed in 8.1 but hopefully Xilinx will also release a tactical patch to allow support for 7.1 for the late-adopters - hint hint! JohnArticle: 94390
Ok, I found it ! But what about the PCI express ? I don't have the spec so if someone can tell me if there is the same process and what is the allowed time ? thank you stéphane. "John McCaskill" <junkmail@fastertechnology.com> a écrit dans le message de news: 1136917580.080616.229680@f14g2000cwb.googlegroups.com... sjulhes wrote: > Hello, > > We have a 2VP40 ( 15.5Mbits configuration ) to configure through a 8 bits > 90ns flash by a CPLD. > I try to find what time has the PCI IP to respond to PCI boot board > identification process before been ignored ? > This will give the time I have to configure my FPGA. > > Does someone has information on this allowed time ? > > Thanks. > > Stéphane. For PCI 2.3, and revision 1.0a of the PCI-X spec: 100 ms from power valid to RST# high. For PCI 2^25 clocks from RST# high to first configuration access. For PCI-X 2^26 clocks from RST# high to first configuration access. Regards, John McCaskillArticle: 94391
On 11 Jan 2006 05:22:24 GMT, kd (kdfake@spam.com) wrote: >Any issues? I am also interesetd. I will try today, in a couple of hours I may give you some answer.. Best regards, ZaraArticle: 94392
I downloaded it about 24h ago using the university broadband and it went at about 1200kb/s ;) Definitly nice ... I prefer the look of the 8.1 and on linux it seems to run better ... but I haven't tested it much since I use EDK quite a lot ....Article: 94393
"Brian Davis" <brimdavis@aol.com> schrieb im Newsbeitrag news:1136809595.310126.157170@o13g2000cwo.googlegroups.com... > Antti Lukats wrote: >> >> No, I dont think your board is different of what I have and you can >> not use JP2 for serial config, its not wired to proper pins >> > Oops, you're right; the Rev C. board pictures in the user's guide > label those connector pins "MOSI, MISO" etc so I thought they'd > brought out the serial boot pins. The schematic also labels that > connector as "Alternate Programming", but I hadn't checked the > FPGA pin connections. > > Brian > hm, I only have seen rev D or D.1 schematics, and no MISO/MOSI reference the JP2 is labelled as alternative programming, but that just means nothing first beta of standalone programming and config utility is now downloadable (only Xilinx Cable III support drivers are included) http://xilant.com/component/option,com_remository/Itemid,53/func,fileinfo/id,8/ -- Antti Lukats http://www.xilant.comArticle: 94394
as more and more customers are getting their Sample Packs so I decided to pre release the standalone programming utility for the board, available for immediate download http://xilant.com/component/option,com_remository/Itemid,53/func,fileinfo/id,8/ this has fully working base functionality for FPGA config and Flash programming. both for FPGA and Flash there is no need to worry about startup clock and for flash there is also no need to invoke and promgen or anything same .BIT files can be used for FPGA and Flash, the startup clock is automatically fixed to either JTAG of CCLK and the preparation for flash is also automatic startup clock auto-fix is now also supported in compressed bitstream (CRC is properly recalculated) only Cable III is supported for the moment, next releases may have wider hardware support included I have tried hard to also test out Xilinx suggested Flash programming for the sample pack (EDK, XMD, flashwriter.tcl) - I have failed so far, also completly failed have all attempts to use universal scan for the flash programming. nahitafu is using MITOU JTAG tool for flash programming of the sample pack but as that tool is not free and has no eval so our Flash programming utility for the Sample Pack is the first freely available and proven working solution to reflash the strataflash on the Sample Pack board. the base functionality of the tool is FREE of charge, there is no registration required, just download unzip and get start -- Antti Lukats http://www.xilant.comArticle: 94395
On 11 Jan 2006 05:22:24 GMT, kd (kdfake@spam.com) wrote: >Any issues? Continuing.... Just tested it. I had to make a copy of [EDK]\bin\nt\xps.exe to [EDK]\bin\nt\_xps.exe so that ISE found it. Launched synthesis, and not to my surprise, the _xps process hanged, with 98% CPU usage. I say not to my surprise, because the same happened when changing form 6.2 to 6.3, and form 6.3 to 7.1. It would be nicer from Xilinx, if there appeared apopup window, or a console line, telling us the versions don´t match. Welle, let´s wait fro the new EDK 8.1 release, whenever it comes. BTW, someone from Xilinx told me some time ago that EDK 8.1 will, at last!, support C++. I hope it will. Best regards, ZaraArticle: 94396
sjulhes schrieb: > Ok, I found it ! > > But what about the PCI express ? > I don't have the spec so if someone can tell me if there is the same process > and what is the allowed time ? > PCIe is hot plug capable, so it probably does not matter. Just tell the system that your device is present when you finished configuration. Kolja SulimmaArticle: 94397
mohit.tiwari@gmail.com schrieb: > Hi, please guide me on two beginner-level questions. > > A program writes an integer onto BAR0 on the Stratix PCI board. I wish > the fpga design to read this value from BAR0, and store it (and display > the last 8 bits on the LEDs on the board). > > 1. How do I trigger my design whenever something is written onto BAR0? > > 2. How can I read from BAR0 from my verilog design? The value is allready stored in BAR0 so all you need to do is connect wires from the BAR= register to the LEDs. If you have sourcecode for the PCI core this extremly easy. If you don't it is more or less impossible. Kolja SulimmaArticle: 94398
You are forgetting that, by the very nature of the beast, Patents are designed to be as general as possible without seeming to digress onto other topics... like this thread. Simon "Robert Baer" <robertbaer@earthlink.net> wrote in message news:UV1vf.1123$WY5.129@newsread2.news.pas.earthlink.net... > soar2morrow@yahoo.com wrote: > > > Dirk Bruere at Neopax wrote: > > > >>Robert Baer wrote: > >> > >> > >>>Eric Smith wrote: > >>> > >>> > >>>>wtxwtx@gmail.com writes: > >>>> > >>>> > >>>>>Why 'a plurality of N' or 'the plurality of N' must be used fo 'N' in > >>>>>patent claims? > >>>> > >>>> > >>>> > >>>>Because patents are written to be legal documents, not engineering > >>>>documents. Legal documents are written using traditions that have > >>>>evolved over hundreds of years. Since patent examiners, lawyers, and > >>>>judges all expect patents to be written in a certain way, if you > >>>>submit an application that isn't written that way, you're just wasting > >>>>money. > >>> > >>> Again, that is what i call "patent-ese". > >>> Instead of "many" or "multiple" one sees "a plurality of". > >>> Like i said, follow the terminology and useage that you find in other > >>>patents that are closely related to your particular idea. > >> > >>Legalese is a very precise language, quite comparable to computer languages. > >>If you ever see "...time is of the essence..." in a contract, prepare to run. > > > > > > Legalese is designed to keep lawyers employed. It is not, by itself, > > "precise". Contracts and other legal documents written in "plain > > English" are just as enforceable as the legalese version. Maybe even > > more so, because a jury (non-lawyers) can understand them. > > > > MOOYMMV. > > > > Tom Seim > > > Perhaps, but the question pertains to terminology in patents.Article: 94399
Dear hobbyists, I need some advice on FPGA's. One of my projects involves VGA video generation (with AVR microcontroller). I want to use FPGA's instead of MCU to produce higher resolutions. The FPGA should read data from sram and send it to a D/A converter. Wich FPGA can I use for this? Altera, Xilinx? I suppose I need to write the code in Verilog? Wich of the two has the best free of least expensive software? Thanks in advance Johan
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