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"fahadislam2002" <fahadislam2002@hotmail-dot-com.no-spam.invalid> schrieb im
Newsbeitrag news:d4mdncW_s-FWvQPeRVn_vQ@giganews.com...
> Hi Antti
> as later i told i stated from Reader ... and i am facing
> problem in crc-7 ... i know that serial crc is easy but it will take
> more time so i was trying for table based crc approach ... but its a
> little more complex ...
> whats your suggestion for that ...
> and also I got your code and trying to understand and learn from
> it(as your coding style is much better and professional than me) ...
> but i have some questions about ur code ...
> 1) stream read ?
yes, but this is not available on SD cards only MMC :(
> 2) crc7 is right ?
is calculated from table as for that PLD application it uses less resources
than 7 FF for crc7
> 3) standard 3.1 (7 pin) ?
7 pin MMC yes
> and one more question ...
> Is there any way to avoid crc in command as for
> developing reader i got help from sandisk datasheet and also of
> hitachi ... and in that although I not found any kind of such
> description ... but in one example in datasheet i felt that to ignore
> crc he was puting all crc bits one(1111111) ...is it true ?
>
no, the CRC has to be present in all transmitted commands
some command responses(broadcast) have 1111111 as crc7
and attached is tested correct MMC/SD CRC7 module
-- cut here
--------------------------------------------------------------------------------
-- Company: Xilant Technologies Inc.
-- Engineer: Antti Lukats
--
-- Create Date: 02/08/05
-- Design Name:
-- Module Name: mmc_crc7 - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description: MMC/SD Carc CRC7 module
-- Can be used to 'shift out'
-- the CRC7+stop bit after CALC
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- Silicon(FPGA) tested
-- This module has 7-bit running CRC available on each clock
-- high bit crc(6) will be come output of shift register
-- when crcen goes low shifting the CRC7 and stop-bit(high)
-- serially out
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity xti_mmc_crc7 is Port (
rst : in std_logic;
clk : in std_logic;
din : in std_logic;
crc : out std_logic_vector(6 downto 0);
crcen : in std_logic);
end xti_mmc_crc7;
architecture Behavioral of xti_mmc_crc7 is
signal sr : std_logic_vector(6 downto 0);
begin
crc <= sr;
Process_CLK : process (CLK) is
begin
if RST = '1' then
sr <= "0000000";
else
if CLK'event and CLK = '1' then
if crcen = '1' then
sr(0) <= din xor sr(6);
sr(1) <= sr(0);
sr(2) <= sr(1);
sr(3) <= sr(2) xor sr(6) xor din;
sr(4) <= sr(3);
sr(5) <= sr(4);
sr(6) <= sr(5);
else
sr(6 downto 1) <= sr(5 downto 0);
-- STOP Bit!
sr(0) <= '1';
end if;
end if;
end if;
end process Process_CLK;
end Behavioral;
Article: 93051
johnp schrieb:
> Eilert -
>
> I think your asking the wrong question when you ask
>
> 'How comes that the simpler(?) tool does the better job?'
>
> You should ask 'which tools are doing the correct job?'
>
> What if you were delibrately coding to create latches? Would
> you say it was doing a better job?
>
> Just my $0.02
>
> John Providenza
>
Hi John,
good point.
I posed my question from the FSM designers point of view.
In any other case you are right.
see the next postings...
best regards
Eilert
Article: 93052On Tue, 13 Dec 2005 15:54:27 +0800, "Frank" <Francis.invalid@hotmail.com> wrote: > >"GaLaKtIkUsT" <taileb.mehdi@gmail.com> wrote in message >news:1134403664.635669.155490@f14g2000cwb.googlegroups.com... >> Binary format and secret! >> Good for protecting designs against piracy but too many problems for >> those who want to do dynamic reconf :-( >> >> Mehdi >> > >Yeah I was aware of that, dynamic reconf is a nightmare. Worked on that >thingy before and never again. > > Is not so difficult, is question of patiente and experience and know very well what you are doing. JavierArticle: 93053
While I have only a 40MHz clock connected to a 10 bit ADC, nothing connected to the analog input sockets, the chip is Analog AD9218 (ADC chip) EVM board. On the LA, sampled outputs are 0~16 for one channel, -32~0 for the other channel (400 MHz timing mode). Is my board faulty? According to my simulation in digital design, my sampled inputs (10 bits each) can not have noise higher than 1 LSB (flipping small number of bit 0 causes demodulation error). Is the setup I have workable or croaked?Article: 93054
"GaLaKtIkUsT" <taileb.mehdi@gmail.com> wrote in message news:1134403664.635669.155490@f14g2000cwb.googlegroups.com... > Binary format and secret! > Good for protecting designs against piracy but too many problems for > those who want to do dynamic reconf :-( > > Mehdi > Yeah I was aware of that, dynamic reconf is a nightmare. Worked on that thingy before and never again.Article: 93055
Frank wrote: > While I have only a 40MHz clock connected to a 10 bit ADC, nothing connected > to > the analog input sockets, the chip is Analog AD9218 (ADC chip) EVM board. On > the LA, sampled outputs are 0~16 for one channel, -32~0 for the other > channel (400 MHz > timing mode). Is my board faulty? > > According to my simulation in digital design, my sampled inputs (10 bits > each) can not > have noise higher than 1 LSB (flipping small number of bit 0 causes > demodulation error). > > Is the setup I have workable or croaked? Terminate the inputs (don't leave them open) and try again perhaps? Dave :)Article: 93056
they talked about this producte for more than 3 years ago, now its finally laucnhed * ADC 12bit 600KS/S * MOSFET drivers * user Flash rom * onchip 1% accurate 100MHz oscillator * oscillator for 32KHz watch crhrystal * single 3.3V power supply http://xilant.com/content/view/22/2/ pretty nice features! Well PA3 is just about shipping so we may have to wait to get hands on onto Fusion silicon, but it really looks like cool true single chip. hm,. if I think about it, this the silicon I have been waiting for, for the last 10 years or so AnttiArticle: 93057
"Frank" <Francis.invalid@hotmail.com> wrote in message news:439e7c34@news.starhub.net.sg... > While I have only a 40MHz clock connected to a 10 bit ADC, nothing > connected > to > the analog input sockets, the chip is Analog AD9218 (ADC chip) EVM board. > On > the LA, sampled outputs are 0~16 for one channel, -32~0 for the other > channel (400 MHz > timing mode). Is my board faulty? > > According to my simulation in digital design, my sampled inputs (10 bits > each) can not > have noise higher than 1 LSB (flipping small number of bit 0 causes > demodulation error). > > Is the setup I have workable or croaked? What happens if you tie the inputs to ground rather than leaving them floating? -- GregArticle: 93058
Jan Decaluwe schrieb: > Perhaps it doesn't, unfortunately. It may be that you are seeing a > bug that happens to do the right thing in this particular case. > -- snip-- > > But my guess is that that's not what happening. To test this, > synthesize the combinatorial part on it own. ISE cannot know > how it is used now. Does it now infer latches or issue a > warning? It not, then that's a bug and you were just > lucky in the original case. Otherwise, we would like > to know! > > BTW, the truly intelligent thing to do would be to refuse to > infer latches and issue an error. The latch control logic > will be so glitchy that such a circuit cannot possibly > work reliably in practice. > > Jan > Hi Jan, I did as you proposed (for ISE only) and the good news is that it indeed can create latches when synthesizing the combinatorical part without the defaulting line before the case. Of course the latches will be "welcomed" with a warning in the synthesis report :-) So for FSM designers using ISE the way is free to create crappy code without a warning, which becomes painful for those who want to use that code with other synthesios tools. A little warning in the report would be nice. Something like: "Incomplete specified FSM-feedback detected. Creating latch-free logic." This would give at least a clue that danger is ahead of the road. Your proposal might even be better, since it forces designers to create latchfree, portable sourcecode. Is anyone from Xilinx reading this? Maybe it's worth to put it on the todo-list for ISE8.1 SP1 :-) best regards EilertArticle: 93059
Antti Lukats wrote: > they talked about this producte for more than 3 years ago, now its finally > laucnhed > > * ADC 12bit 600KS/S > * MOSFET drivers > * user Flash rom > * onchip 1% accurate 100MHz oscillator > * oscillator for 32KHz watch crhrystal > * single 3.3V power supply > > http://xilant.com/content/view/22/2/ > > pretty nice features! > > Well PA3 is just about shipping so we may have to wait to get hands on onto > Fusion silicon, but it really looks like cool true single chip. > > hm,. if I think about it, this the silicon I have been waiting for, for the > last 10 years or so > > Antti - and large amounts of code flash, so much that the SRAM looks a bit light..... Key determinant will be the price, as you can get ARM+FLASH+ADC+32KHz+Ethernet, for rather less than the same bundle will be in the Fusion. That means the FPGA aspect has to be very important, to the design, and the single chip more important than a much cheaper CPLD/Small FPGA alongside the ARM+FLASH+ADC+32KHz+Ethernet.... Devices from the uC segment to compare this with, would be the ADuC7xx series : 12 Bit ADC, 12 Bit DAC, ARM CPU, FLASH, in 40-80 pins, and the 'comming' uPSD ARMs from ST, which have 32MC CPLDs, and Ethernet/CAN/USB, 96K Bytes SRAM and 2MBytes FLASH. Seems to me a smaller Fusion device, _and_ a "Well stacked" ARM Flash Microcontroller, will be better value, than trying to roll it all yourself in a bigger Fusion device. Time will tell, I guess. -jgArticle: 93060
Hello all, Environment details FPGA : Xilinx spartan 3(xc3s200-vq100) speed grade 4 ISE : version 7.1.04i Modelsim : verion ModelSim XE III/Starter 6.0a I am Monica from Germany.I am pretty new to FPGA development.Now I am developing a small interface module which generates MPEG 2 stream. I drive mpegSync and mpegData at the same time(same location in VHDL) but however in Place And Route simulation I am observing that mpegData is lagging mpegSync by 7ns.I want both the mpegSync and mpegData to be asserted at the same time. Behaviuoral simulation is fine but PAR simulation is not fine may be because mpegData is routed with longer nets before it reaches I/O pad. Can anybody give me a hint how to drive them nearly the same time?Is there any xilinx constraint i can use? Thanks a lot in advance. Monica DSouza, GermanyArticle: 93061
Hi, This Dallas part does look pretty good, it makes it hard enough to hack; Do you have an idea of small quantity prices...? It's lasered with a unique number, hopefully they have samples with 'not a unique' number for customers that only need to give it a whirl... Thx in advance, -- Ignacio Ulises Hernandez " I'm not normally a praying man, but if you're up there, please save me, Superman!" - Homer Simpson ;O) <jaxato@gmail.com> wrote in message news:1134451285.285119.232390@g43g2000cwa.googlegroups.com... > Thanks, > xapp780 is good food for the mind, and I think we would have to design > our own (Vanilla microcontroller) that would mimic a DS2432 secure > controller-key. > One thing though, would xilinx enhance the security feature of their S3 > line? And finally, in case of a virtex2, can a design gain access to > the registers that hold the encryption keys. > > In response to Thomas, all our products are X based, so we dont have > many choices. And as we dont want to provide our customers access to > the high level code, the only way to give them a usable core is to have > the design in a compiled obfuscated netlist file. > > JA > > Austin Lesea wrote: >> http://www.xilinx.com/bvdocs/appnotes/xapp780.pdf >> >> Austin >> >> Thomas Stanka wrote: >> >> > Why Ngc? >> > And is it necessary to stay on S3? Maybe you should think about Flash >> > based Fpgas (Actel, Lattice,..). >> > >> > bye Thomas >> > >Article: 93062
"I. Ulises Hernandez" <delete@e-vhdl.com> schrieb im Newsbeitrag news:dnm98l$lsm$1@nwrdmz02.dmz.ncs.ea.ibs-infra.bt.com... > Hi, > > This Dallas part does look pretty good, it makes it hard enough to hack; > > Do you have an idea of small quantity prices...? It's lasered with a > unique number, hopefully they have samples with 'not a unique' number for > customers that only need to give it a whirl... > > Thx in advance, all 1-wire products *must* have unique number, it is IMPOSSIBLE to something else AnttiArticle: 93063
On 12 Dec 2005 22:14:02 -0800, "Chloe" <chloe_music2003@yahoo.co.uk> wrote: >Zara: Hi, and thanks for your advice. I did assign package-pin >pre-translate, and I deduced from the Translate Report that all the I/O >pins were assigned and translated properly as there were no errors in >the report. Thus I wonder how Assign Package Pins Post-Translate is >used, if I have already done a pin assignment before I even synthesised >my design. > >I just do not understand how my I/O pins could be translated wrongly. >Could it be that I mis-configured the ISE? > >Thanks. > >~Chloe~ The problem with Postr_translate assignment is that it will be lost if you translate the project again. That is why it is only used for debugging purposes (sending some internal signal to a pin, for instance). The *used* pins should always be LOCed in the UCF file, so they retain their position from one translation to the next. Regards, ZaraArticle: 93064
Hi Monica, Can you place those registers in IOBs? This will give you equal (and faster, if that is ok) clock to output times. Use ISE Help within Project Navigator to show you how to do that. AlanArticle: 93065
Dear Mr.Alan, Thank you very much for your suggestion.But unfortunately,mpegData is not a register,it is only a wire from Block RAM(signal).Where as mpegSync is a register. Is there any other alternative? thank you, MonicaArticle: 93066
"Jim Granville" <no.spam@designtools.co.nz> schrieb im Newsbeitrag news:439ea16a$1@clear.net.nz... > Antti Lukats wrote: >> they talked about this producte for more than 3 years ago, now its >> finally laucnhed >> >> * ADC 12bit 600KS/S >> * MOSFET drivers >> * user Flash rom >> * onchip 1% accurate 100MHz oscillator >> * oscillator for 32KHz watch crhrystal >> * single 3.3V power supply >> >> http://xilant.com/content/view/22/2/ >> >> pretty nice features! >> >> Well PA3 is just about shipping so we may have to wait to get hands on >> onto Fusion silicon, but it really looks like cool true single chip. >> >> hm,. if I think about it, this the silicon I have been waiting for, for >> the last 10 years or so >> >> Antti > > - and large amounts of code flash, so much that the SRAM looks a bit > light..... > > Key determinant will be the price, as you can get > ARM+FLASH+ADC+32KHz+Ethernet, for rather less than the same bundle will be > in the Fusion. That means the FPGA aspect has to be very important, > to the design, and the single chip more important than a much cheaper > CPLD/Small FPGA alongside the ARM+FLASH+ADC+32KHz+Ethernet.... > > Devices from the uC segment to compare this with, would be the > ADuC7xx series : 12 Bit ADC, 12 Bit DAC, ARM CPU, FLASH, in 40-80 pins, > and the 'comming' uPSD ARMs from ST, which have 32MC CPLDs, and > Ethernet/CAN/USB, 96K Bytes SRAM and 2MBytes FLASH. > > Seems to me a smaller Fusion device, _and_ a "Well stacked" ARM Flash > Microcontroller, will be better value, than trying to roll it all > yourself in a bigger Fusion device. Time will tell, I guess. > > -jg > the only PA3 prices I know are 20/55USD for 250/600 devices, so I assume the only currently available fusion (600) is pretty expensive compared to flash-mcu but the fusion chip is nice ALLINONE if you need it all to be inside single chip there is very little that is required outside the chip, so thats what for you pay. for cost effective, yes atmel ARM+flah+usb = 5USD, some small fpga is pretty much less expensive. as of last info the fusion starterkit and 600 samples should available NOW. AnttiArticle: 93067
I'm having some hard time to understand what's wrong with this Xilinx floating-point core included in the last IP update for LogicCORE. My design requires me to acquire data from an ADC and then, after some processing to do a division between a couple floating point numbers every 200ns. The performances of the core aren't big enough to use just one, so I implemented a core which feeds several dividers(made with the Xilinx core) and then I reserialize it all. The design works fine till I pass numbers with a period down to 260ns, going for lower periods the results get weird: the mantissa is correct, the exponent instead is always fixed to 00111111, whatever it's supposed to be instead. If anybody can offer some insight or even suggest a way of debugging, it would be much appreciated because at the moment I don't have any idea of what could be wrong. Thanks in advace, kl31nArticle: 93068
Hi Monica, Could you pipeline the mpegData and mpegSync signals with registers before outputing them? Then you could put the pipeline registers in the IOBs? AlanArticle: 93069
Dear Mr.Alan, I have changed my logic such mpegData is considered as a register instead of combitional logic and kept them in IOBs(through help).The output is not only good but also fast.Thanks a lot for your suggestion. Can you please tell me what is the idea behind keeping these registers in IOBs?What are these IOBs? Thank you very much for your help. Monica DSouza, GermanyArticle: 93070
"Jeff Cunningham" <jcc@sover.net> schrieb im Newsbeitrag news:439975d5$0$8182$6d3edbfc@news.sover.net... > Antti Lukats wrote: > >> where are the boards for Spartan3+PX1011 evaluation? > > I ran across this one. Not exactly cheap. > > http://www.tentmakersystems.com/PXSurfboard.htm possible the only one ever made is offered for sales. http://www.ge-research.com/PCIe.html another sub 1000USD PCIe board AnttiArticle: 93071
Antti Lukats wrote: > all 1-wire products *must* have unique number, it is IMPOSSIBLE to something > else > > Antti > > Well, not impossible. The codes are customized to the customer. IIRC, it is a 48 bit code, and part of that number is a unique number assigned to the customer, and part is a range of numbers assigned to that customer. You can (or at least you used to be able to) get duplicate numbers within your range. The codes, as I understand it, are added after the silicon is manufactured. The problem with using these in attempt to secure a bitstream is that the code is not secure...anyone with a data sheet and an oscilloscope or logic analyzer can extract the serial number easily. Once you have the serial number, it is nearly trivial to create a circuit that will mimic the dallas part using what ever serial number you want to use. These parts are intended for electronic serial numbers, not for secure encryption keys.Article: 93072
Hi Monica, An IOB is an area of logic next to the input/output pad, as opposed to part of the core logic. Constraining the tool to place the register in the IOB thus gives you better clock-to-output times, as the flip-flop is placed next to the output buffer/pad. Glad to have been able to help. AlanArticle: 93073
Javier Castillo wrote: > > Is not so difficult, is question of patiente and experience and know > very well what you are doing. > > Javier > Patience is an understatement. The tools for partial reconfiguration are virtually non-existent. Without suitable tools, using dynamic partial reconfiguration in a design is a lot of painstaking work, and with the size of the devices available today is not economically justified in the vast majority of applications. A comprehensive set of tools for working with partial reconfiguration could easily change that, but I don't expect to see the necessary extensions to the tools any time soon.Article: 93074
Monica wrote: > Dear Mr.Alan, > > I have changed my logic such mpegData is considered as a register > instead of combitional logic and kept them in IOBs(through help).The > output is not only good but also fast.Thanks a lot for your suggestion. > > Can you please tell me what is the idea behind keeping these registers > in IOBs?What are these IOBs? > > Thank you very much for your help. > Monica DSouza, > Germany > Monica, The idea is to normalize the delay from the pin to the first register in the design. Using the flip-flop in the IOB (Input-Output Block) uses only the dedicated routing wire between the device pin and the input or output flip-flop, so the variability due to different routing solutions is removed. Using the IOB registers is also prudent because it isolates the timing inside the FPGA from the timing at the board level, which eliminates problems down the road when you make incremental improvements to the design. Using these registers also tends to make a successful place and route less dependent on the pin assignments.
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