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Hi Can you give some more details of the project am interested to do if there involves only FPGA programming, not PCB design rgds bijoyArticle: 92901
ghelbig@lycos.com wrote: > I'll try to be a little clearer: > > Synthesis is translate and map. After synthesis would be after > translate and map. You can't be after synthesis and before translate > because translate is the 1st step in synthesis. > > It's sort of like saying "After I get there, but before I leave". > > What exactly are you looking for, anyway? > Uh, no. Synthesis is conversion from the HDL to an edif netlist or the equivalent xilinx proprietary. Translation is the first step in the implementation tools, followed by map and then place and route. The boundary between synthesis and translate is a fairly common place to do simulation since it simulates the synthesized netlist without having to do the slower timing model. Translate is also the entry point for designs synthesized (or otherwise produced) from other tool chains.Article: 92902
Hi FPGA : Spartan-3, Xilinx ISE :tools ------------------------------------ have wrote a VHDL code to implement shift registers as shown below type reg_array is array(7 downto 0) of std_logic_vector(7 downto 0); signal reg : reg_array; process(clk) begin if(clk'event and clk = '1')then if(en = '1')then reg <= reg(14 dwonto 0) & din; end if; end if; end process want to map this logic to BLOCK RAM instead of slices. have done this by enablling the option in MAP properties of ISE. But what i observed is it uses BLOCK RAM but occupies slices also. Can anyone help me in this regard whether i am doing anything wrong ? regards bijoyArticle: 92903
Chloe wrote: > Hi there, > > I'm currently using Xilinx ISE 7.1i with the ModelSim XE III/Starter > 6.0a simulator. The FPGA which I am downloading my design onto is a > Spartan IIE (it's on the Spartan IIE LC Development Kit, with an > XC2S300E device). > > I'm very new in FPGAs and hardware design, and if you could help, that > would be great. > > Is there any way for me to run a simulation on the post-synthesis model > of my design? I know that with Xilinx ISE, we can run simulations on > behavioural models, post-translate, post-map and post-PAR models. What > about the synthesised model? > > Please help. > > Thanks very much in advance. > > Regards, > Chloe > You can, but you'll need to get either the mapped HDL output or an edif netlist (and a simulator such as Aldec that will simulate an edif netlist). I think the native XST output is the xilinx proprietary netlist format, so you'll have to figure out the switches to get either the mapped VHDL/Verilog or edif output. I use synplify, and for that you just turn on the mapped vhdl/verilog, and it writes the structural netlist to an output file in the selected language.Article: 92904
Is it possible to read back a xilinx PROM bitstream? I need the Date signature so that I can identify it among 5 of other bitstreams.Article: 92905
"bijoy" <pbijoy@rediffmail.com> schrieb im Newsbeitrag news:ee92e82.-1@webx.sUN8CHnE... > Hi > > FPGA : Spartan-3, Xilinx ISE :tools ------------------------------------ > have wrote a VHDL code to implement shift registers > > as shown below > type reg_array is array(7 downto 0) of std_logic_vector(7 downto 0); > signal reg : reg_array; > process(clk) begin if(clk'event and clk = '1')then if(en = '1')then reg <= > reg(14 dwonto 0) & din; end if; end if; end process > want to map this logic to BLOCK RAM instead of slices. > have done this by enablling the option in MAP properties of ISE. > But what i observed is it uses BLOCK RAM but occupies slices also. > Can anyone help me in this regard > whether i am doing anything wrong ? > regards bijoy the logic is that ISE can auto map to BRAM is ver limited and specific, read the datasheet and manuals it is explained there what type of logic can be auto mapped to BRAM anttiArticle: 92906
"jweissberg" <weissber@NOSPAMusc.edu> schrieb im Newsbeitrag news:dnahm5$i7v$1@gist.usc.edu... > I'm considering these parts for a new design, and the low static power and > small footprint, instant-on features seem nice. In terms of performance > or density, this app is not demanding at all, but we want more headroom > than a CPLD gives. > > I haven't used Actel parts or SW for over 10 years - how have > design/supply/support experiences been on ProAsic3E?? How decent are the > Actel tools for HDL based designs? I'm very familiar with the Xilinx IDE. > I'd be in the 30K device to start with. > > If you want to keep your #$%! answers more private, you can mail me > directly. I can sum up for the group later. > > Thanks in advance! > Actel SW is second worst (frst place is hold by Atmel) - but its maybe matter of taste. There are actually no really issues getting your VHDL into the Actel chip. The toolchain isnt as comfortable but it works and the resulting desings work too. Pricing seems a bit heavy A3P250-VQ100 is 20$ USD in small quantity A3PE600 - 55USD AnttiArticle: 92907
Hi Antti Lukats, > most PCIe PHY datasheets are still under NDA, but Marco Groeneveld has > already made freely available the schematic of the SENDERO board that > includes the PX1011A chip with its connection - downloadable from > > http://www.fpga.nl/ > Actually, I just got word that the Sendero board passed the PCI Plugfest in the US with flying colours this week, with an 85% score, and that the motherboards on which it didn't work well had problems with most other x1 cards too. Ready-made Sendero boards can be ordered from Sascoholz and other Arrow subsidiaries. Best regards, BenArticle: 92908
"Ben Twijnstra" <btwijnstra@gmail.com> schrieb im Newsbeitrag news:cfaf2$43992f17$d52e23a9$6108@news.chello.nl... > Hi Antti Lukats, > >> most PCIe PHY datasheets are still under NDA, but Marco Groeneveld has >> already made freely available the schematic of the SENDERO board that >> includes the PX1011A chip with its connection - downloadable from >> >> http://www.fpga.nl/ >> > > Actually, I just got word that the Sendero board passed the PCI Plugfest > in > the US with flying colours this week, with an 85% score, and that the > motherboards on which it didn't work well had problems with most other x1 > cards too. > > Ready-made Sendero boards can be ordered from Sascoholz and other Arrow > subsidiaries. > > Best regards, > > > Ben > Hi Ben, thats another Altera FPGA Based PCIe board passing plugfest then! I was reading the Sendero stuff and they only say "PCIe physical interface" tested so I assumed it was actually not tested in full. Real cool nice board ! it really seems that Xilinx is behind with PCIe, Stratix-GX passed plugfest looong time ago. And the promised Spartan3E+PhilipsPHY solution well havent seen much pictures of such boards yet. (except the northwest board that can use different phys). There was some notice on Xilinx web that they have it working also (with PX1011) but where are the boards for Spartan3+PX1011 evaluation? I had the impression Avnet was targetting to have them ready by July (this YEAR!) - but nothing there. Ah ok it was possible delayed as the board was supposed to be S3e based. And I guess the Philips PHY delayed also it still says only samples available and DS under NDA. So for those who want lowcost PCIe today its Cyclone-II + PX1011A Go! (or Lattice, they also just advertized low cost PCIe stuff) AnttiArticle: 92909
jamesp wrote:
> Hi,
>
> I am a mature student will be doing some complex VHDL and Verilog design
> work for my course. As well as having to create and test the
> functionality of the design (in both languages) I want to document how
> the design is put together and it's complex hierarchy.
>
> Is there anything out there that will allow me to represent my design in
> some sort of hierarchical functional blocks to use as a documentation
> tool? As I want to use both languages for the design something that
> ideally can accommodate VHDL and Verilog.
>
> I am happy using my normal editing system for the code design so I don't
> want a 'block-to-code' type of system.
>
> Thanks for your help.
>
> James.
Hi James,
We have a tool which we believe will address your questions. There is a
15 day fully functional evaluation download available on the web site so
please feel free to try it out.
www.expressivesystems.com
--
Cheers
Brian
___________________________________
Expressive Systems.
www.expressivesystems.com
Article: 92910jweissberg wrote: > I'm considering these parts for a new design, and the low static power and > small footprint, instant-on features seem nice. In terms of performance or > density, this app is not demanding at all, but we want more headroom than a > CPLD gives. > > I haven't used Actel parts or SW for over 10 years - how have > design/supply/support experiences been on ProAsic3E?? How decent are the > Actel tools for HDL based designs? I'm very familiar with the Xilinx IDE. > I'd be in the 30K device to start with. > > If you want to keep your #$%! answers more private, you can mail me > directly. I can sum up for the group later. > > Thanks in advance! I think that Lattice FPGA merits detailed consideration. It has internal flash for loading with copy protection bit.Article: 92911
Hi I have read that, it says we should not use asynchronous reset The program what i have written is also taken from there and they say it will be mapped to BRAMs I am observing in my p&r report that it is getting mapped to BRAM but the slice count is not getting reduced. regds bijoyArticle: 92912
Frank wrote: > Is it possible to read back a xilinx PROM bitstream? I need the Date > signature so that I can identify it among 5 of other bitstreams. > > Frank, The bitstream file will have a signature (header) when produced by bitgen, however this header is striped out by the config mechanism when beeing programed into the fpga, so is lost, what you can do is to calculate your own CRC (without the header) and keep a map file somewhere. (or save the original bitstreams and perform a diff excluding the header) AurashArticle: 92913
Antti Lukats wrote: > where are the boards for Spartan3+PX1011 evaluation? I ran across this one. Not exactly cheap. http://www.tentmakersystems.com/PXSurfboard.htmArticle: 92914
Hi folks,
I just stumbled over something funny:
I usually write FSMs with registered outputs similar to this example:
--
-- $Id:
--
ARCHITECTURE behavioral OF DEC_Controller_Modi IS
TYPE DCM_state IS (Wait4Activation, Run_ECB, Run_CBC, Run_CFB,
Run_OFB, Run_CTR);
SIGNAL DCM_CurrentState : DCM_state;
SIGNAL DCM_NextState : DCM_state;
BEGIN -- ARCHITECTURE behavioral
-- purpose: StateRegister for DEC_Controller FSM
-- type : sequential
-- inputs : Clock, Reset, DCM_NextState
-- outputs: DCM_CurrentState
DCM_sync : PROCESS (Clock, Reset) IS
BEGIN -- PROCESS DCM_sync
IF Reset = '0' THEN -- asynchronous reset
(active low)
DCM_CurrentState <= Wait4Activation;
ELSIF Clock'event AND Clock = '1' THEN -- rising clock edge
DCM_CurrentState <= DCM_NextState;
END IF;
END PROCESS DCM_sync;
-- purpose: Branch logic for DEC_Controller FSM
-- type : combinational
-- inputs : DCM_CurrentState, all
-- outputs: DCM_NextState
DCM_comb : PROCESS (DCM_CurrentState, ECB_Mode, CTR_Mode,
FeedbackSelect, AES_Ready, Phase1Active) IS
BEGIN -- PROCESS DCM_comb
CASE DCM_CurrentState IS
WHEN Wait4Activation => IF AES_Ready = '1' AND Phase1Active = '0'
THEN
IF ECB_Mode = '0' THEN
IF CTR_Mode = '0' THEN
CASE FeedbackSelect IS
WHEN "001" => DCM_NextState <=
Run_CBC;
WHEN "000" => DCM_NextState <=
Run_CFB;
WHEN "011" => DCM_NextState <=
Run_CFB;
WHEN "100" => DCM_NextState <=
Run_CFB;
WHEN "101" => DCM_NextState <=
Run_CFB;
WHEN "110" => DCM_NextState <=
Run_CFB;
WHEN "111" => DCM_NextState <=
Run_CFB;
WHEN "010" => DCM_NextState <=
Run_OFB;
WHEN OTHERS => NULL;
END CASE;
ELSE
DCM_NextState <= Run_CTR;
END IF;
ELSE
DCM_NextState <= Run_ECB;
END IF;
END IF;
WHEN Run_ECB => IF AES_Ready = '0' THEN
DCM_NextState <= Wait4Activation;
END IF;
WHEN Run_CBC => IF AES_Ready = '0' THEN
DCM_NextState <= Wait4Activation;
END IF;
WHEN Run_CFB => IF AES_Ready = '0' THEN
DCM_NextState <= Wait4Activation;
END IF;
WHEN Run_OFB => IF AES_Ready = '0' THEN
DCM_NextState <= Wait4Activation;
END IF;
WHEN Run_CTR => IF AES_Ready = '0' THEN
DCM_NextState <= Wait4Activation;
END IF;
--WHEN OTHERS => NULL; -- all states covered
END CASE;
END PROCESS DCM_comb;
-- purpose: Registered Outputs for DEC_Controller FSM
-- type : sequential
-- inputs : Clock, Reset, all
-- outputs: all
DCM_regout : PROCESS (Clock, Reset) IS
BEGIN -- PROCESS DCM_regout
IF Reset = '1' THEN -- asynchronous reset (active
high)
Start_ECB <= '0';
Start_CBC <= '0';
Start_CFB <= '0';
Start_OFB <= '0';
Start_CTR <= '0';
Phase2_3Active <= '0'; -- not active in Reset state
ELSIF Clock'event AND Clock = '1' THEN -- rising clock edge
Start_ECB <= '0';
Start_CBC <= '0';
Start_CFB <= '0';
Start_OFB <= '0';
Start_CTR <= '0';
Phase2_3Active <= '1';
CASE DCM_NextState IS
WHEN Wait4Activation => Phase2_3Active <= '0';
WHEN Run_ECB => Start_ECB <= '1';
WHEN Run_CBC => Start_CBC <= '1';
WHEN Run_CFB => Start_CFB <= '1';
WHEN Run_OFB => Start_OFB <= '1';
WHEN Run_CTR => Start_CTR <= '1';
-- WHEN OTHERS => NULL; -- all states
covered
END CASE;
END IF;
END PROCESS DCM_regout;
END ARCHITECTURE behavioral;
---------------------------------------------------------------------
While ISE creates a nice little FSM, Precision RTL and Synopsys Design
Analyser drop in a bunch of latches for the DCM_NextState signal bits.
Well, from an isolated point of view they are right. My case statement
lacks default values (the "when others" has been commented out, because
Precision gives a warning, that all brances are covered).
So, what makes me wonder is that both expensive tools create
latch-loaded garbage while "cheap little" ISE synthesizes as expected by
me. Besides the ugly option of writing defaults into all when-brances,
is there any solution that pushes precision and/or synopsys dc to a
better synthesis?
Enlighten me ;-)
Eilert
Article: 92915A need an asynch. FIFO for a Spartan 3E-design, without CoreGen. On the Xilinx-web-page I only found XAPP258, which I cannot use as I need a "level-indication" for both clock-domains. Is it possible that something basic as this is not available for free, or have I just looked in the wrong places? Do I need to implement this on my own? Thomas www.entner-electronics.comArticle: 92916
"Simon Peacock" <simon$actrix.co.nz> schrieb im Newsbeitrag news:4393e2d9$1@news2.actrix.gen.nz... >I am still waiting for the Xilinx Spartan 3E demo board.. price is right >and > it has Ethernet > > Simon good luck with your waiting! I have the cesys board with 500E chip so my wait is now over :) AnttiArticle: 92917
It is normal, DONE pin is not modified during the partial reconfiguration. In ISE 7.1 partial reconfiguration on Virtex4 is not well supported. It works only with very small designs making some manual work on the FPGA Editor. Regards Javier Castillo On 8 Dec 2005 07:19:46 -0800, "Denaice" <dgalerin@gmail.com> wrote: >Hi, > >I'm trying to dynamically reconfigure a Virtex-4 FPGA, by following the >example of XAPP 290. I'm following the module-based partial reconfig >flow, but since the tools don't support generation of partial >bitstreams, I use difference-based bitstreams to reconfigure the FPGA. >The generation of full and partial bitstreams works perfectly, and I >have no problem when downloading the initial bitstream to the chip. >However, when I try to download a partial bitstream, I have the >following warning message : > >Warning:iMPACT:2218 - Error shows in the status register, release_done >bit is NOT 1. > >The FPGA pauses (it seems that the outputs are 3-stated) until I click >ok "ok". When I read the status register after that, the done pin has >the correct value. > >Does anyone have an idea about the cause of this warning ? > >Thanks, > >Denis > >PS : I'm using a VIRTEX-4 LX25 on an Avnet board, and I'm using a >parallel cable IV in Boundary scan mode. I'm working with ISE 7.1 SP3. >Here are my bitgen -g options : > >-g ActivateGCLK:Yes >-g ReadBack >-g DebugBitstream:No >-g CRC:Enable >-g ConfigRate:4 >-g M0Pin:PullUp >-g M1Pin:PullUp >-g M2Pin:PullUp >-g ProgPin:PullUp >-g DonePin:PullUp >-g DriveDone:No >-g PowerdownPin:PullUp >-g TckPin:PullUp >-g TdiPin:PullUp >-g TdoPin:PullNone >-g TmsPin:PullUp >-g UnusedPin:PullUp >-g UserID:0xFFFFFFFF >-g DCMShutDown:Disable >-g DisableBandgap:No >-g StartUpClk:JtagClk >-g DONE_cycle:4 >-g GTS_cycle:Keep >-g GWE_cycle:Keep >-g LCK_cycle:NoWait >-g Match_cycle:NoWait >-g Security:None >-g Persist:No >-g ActiveReconfig:Yes >-g DonePipe:No >-g Encrypt:NoArticle: 92918
"Ray Andraka" <ray@andraka.com> schrieb im Newsbeitrag news:wmklf.16519$Mi5.14447@dukeread07... > Simon Peacock wrote: >> You may want to check the stockings by the fireplace. >> >> Simon >> >> "Antti Lukats" <antti@openchip.org> wrote in message >> news:dn20o1$t57$1@online.de... >> >>>ISE 8.1 release was planned for mid nov, now its mid december soon, I >> >> wonder... > > > I got 8.1 this morning by electronic delivery. I haven't tried installing > it yet. I'll wait till I have the current projects out of the way before > subjecting myself to being a guinea pig again. I am not asking you to be a guinea pig but could you checkout (in the 8.1 manual?) if jtag indirect programming of serial flash devices for Spartan 3e is supported? Altera and Lattice both support this kind of programming I wonder if Xilinx is getting up to the competitors or not. Or maybe some one from Xilinx could answer my question? please? AnttiArticle: 92919
Thanks for your help. I have one more question : Is there a mean to reconfigure the virtex-4 (with partial bitstreams) without pausing it, or do we have to use full bitstreams ? Thanks in advance, DenisArticle: 92920
"Denaice" <dgalerin@gmail.com> schrieb im Newsbeitrag news:1134138476.071974.187070@g49g2000cwa.googlegroups.com... > Thanks for your help. > > I have one more question : Is there a mean to reconfigure the virtex-4 > (with partial bitstreams) without pausing it, or do we have to use full > bitstreams ? > > Thanks in advance, > > Denis > it should be possible, but may be very tricky anttiArticle: 92921
You can use Metor Graphics's FPGA Advantage. When I was a student I used it to design complex VHDL designs. You have graphical entry of HDL code. The HDL code can also be converted to a graphical representation. See www.mentor.com for more infos on theyr products. A+ MehdiArticle: 92922
The local FAE dropped off a copy of 8.1 yesterday. It exists. Tried it out for a while. No major issues noted. Some issues I was having with Spartan3e are fixed. -- Phil Hays to reply solve: phil.hays at not(coldmail) dot com If not cold then hotArticle: 92923
I'm not sure what you are asking. When you reconfigure the FPGA with a partial bitstream the FPGA is not paused, the not reconfigured part is working during the partial reconfiguration. That is the reason because you can reconfigure one part of the FPGA using the ICAP port. For this type of questions I recommend you to use the partial reconfiguration mailing list. Regards Javier On 9 Dec 2005 06:27:56 -0800, "Denaice" <dgalerin@gmail.com> wrote: >Thanks for your help. > >I have one more question : Is there a mean to reconfigure the virtex-4 >(with partial bitstreams) without pausing it, or do we have to use full >bitstreams ? > >Thanks in advance, > >DenisArticle: 92924
Well, for the moment, I'm not reconfiguring through ICAP with a PPC or Microblaze. I'm only trying to reconfigure in JTAG by the remote PC, but it seems - obviously - that the FPGA pauses when reconfiguring (because in my design, the leds which, should continue to blink, are shut down). I don't know....
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