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Brannon King wrote: >What's the most efficient way to perform an "equal to zero" operation in a >V2 chip? What I've been doing is ANDing all the bits together in a binary >tree and relying on the mapper to put that into LUTs correctly. Is this a >good way to do it? > > > Hi, use a 4 input AND gate (for every 4 inputs you need to instantiate a LUT and don't forget the INIT value to program the LUT to behave as an 4AND) and if you need more inputs chain the LUTs with the dedicated carry chain. using this approach the you'll keep the logic levels down to 1 + carry chain propagation delay. if you have EDK you can check the address decoders in the file pselect.vhd (same tehnique presented above) AurashArticle: 73551
Typically the best way to do a comparison to zero is to use (checkMe==0). The synthesizer is typically aware of the tradeoffs in your target architecture. Most often a simple tree of cascaded elements is simple. Sometimes the carry chain is a better way to go for a very wide comparison but those tradeoffs are hard to know with a pencil and paper. The advantage of leaving it to the synthesizer is that your code is much more readable. Have you ever walked up to code you wrote more than a year ago and wonder what the heck you were trying to do? Imagine what it's like for others. The AND you mention works on the inverted "checkMe" in my example: &(~checkMe) "Brannon King" <bking@starbridgesystems.com> wrote in message news:ciuqo6$b4i@dispatch.concentric.net... > What's the most efficient way to perform an "equal to zero" operation in a > V2 chip? What I've been doing is ANDing all the bits together in a binary > tree and relying on the mapper to put that into LUTs correctly. Is this a > good way to do it? > > -- > Prepend a 'b' to email me. Thanks. > >Article: 73552
I think the mapper doesn't strike much of a difference. I've been using the "O" only for my manually instantiated primitives without complaints from either Synplify or the Xilinx back end tools. "Brannon King" <bking@starbridgesystems.com> wrote in message news:ciuq9l$b4j@dispatch.concentric.net... > I think I finally got a grip on the legal connections for the LO output on > MUXFx primitive objects, but what are the legal connections for the LO > outputs on MUXCY and XORCY primitive objects? Does Xilinx have a document > somewhere discussing this? It seems mapper does not automatically swap the O > to LO to improve timing. Why is that? It seems that XST and Synplify infer > about 90% LO and 10% O. I need to know the rules to make my tool do that. > Thanks for your time. > > -- > Prepend a 'b' to email me. Thanks. > >Article: 73553
"Brian" <br@br.com> wrote in message news:ciugm6$6od$1@news5.svr.pol.co.uk... > > "Brian" <br@br.com> wrote in message > news:cisjee$t3m$1@newsg4.svr.pol.co.uk... > > Someone has said that the 5V PCI bus in modern PC's actually uses 3.3V > signals. If this is the case, then I may not need any level shifting. I'll > measure the PCI voltages later today and post the results here. > Thanks again. > > Measuring the PCI voltages won't give you what you want. There are separate pins for 5V and 3.3V and both may be present. A better indicator would be where the keys are located in the bus connectors. If the key is near the front (connector end) of the board, it is a 3.3V slot. If on the other end of the connect it is a 5V slot. Universal PCI cards have a slot in both locations so it can plug into either type slot. -- Greg readgc.invalid@hotmail.com.invalid (Remove the '.invalid' twice to send Email)Article: 73554
Hi Brian, > I'm using an evaluation board, which I'm going to connect > to the PCI bus via a prototyping card. My budget doesn't > really stretch to getting a new FPGA. The QuickSwitches > seem to be only available in surface mount packages, which > is no good for me. The card I'm making will only be used > by me so using non spec parts is fine. If resistors did > the job they would be great. Quite honestly, if I were you -- I'd sell all the stuff on eBay to generate a downpayment for a PCI development board from http://www.fpga4fun.com which costs less than $300. You have to ask yourself -- what is your time worth? What are the chances you might build something that doesn't work properly? And, if you are unlucky in that regard, what is the cost of failure? > Someone has said that the 5V PCI bus in modern PC's actually > uses 3.3V signals. If this is the case, then I may not need > any level shifting. The switching thresholds are similar to 5.0v TTL, and are compatible with 3.3v CMOS devices. That's why with Virtex and Spartan-II, you can interface to 5.0v PCI using a VCCO (output driver voltage) of 3.3v. When you use those parts, though, there are no clamp diodes to 3.3v in the FPGA I/O. That is not the case with Spartan-IIE. The clamp diodes in the FPGA to 3.3v will be turned on by the pullups on the bus to 5.0v. This is not a good arrangement. > How can I calculate whether or not the 100 ohm resistors > will reduce my clock speeds? This is a lot of work with SPICE. Even when you arrived at a result, "I can only run the bus at 25 MHz" there are few machines that will let you change the bus frequency. So this work won't buy you much if you're on a budget. Good luck, EricArticle: 73555
"Kolja Sulimma" <news@sulimma.de> wrote in message news:b890a7a.0409230709.2c524560@posting.google.com... > Austin, > > you are probably the right person to answer this question: > > I made a mistake and now I have a board with a XC3S200FT that has a > ramp up time for the 2.5V power supply of only about 300us. That is > only about half us much as required by the datasheet. > > One I/O bank uses 2.5V as VCCIO, the others use 3.3V which has a ramp > up time of 600us. > > Apparently the board is working normally. Can anyone comment on what > kind of mishap I could expect because of this? > If there is a bad effect that does not happen on the prototype, how > will it be triggered on future boards: Temperature? Chip to chip > tolerances? > > Or is the safety margin in the datasheet large enough that I can > ignore this? > > Kolja Sulimma If the 2.5V, 300 us ramp is on the VCCAUX supply only, then no problem. However, if one of the VCCO_# supplies also connects to the 2.5V supply, then yes, the design violates the current Tcco specification in the Spartan-3 data sheet (Table 3 of the Spartan-3 data sheet, page 3). http://www.xilinx.com/bvdocs/publications/ds099-3.pdf The Tcco specification for the XC3S200 in the FT256 package is 600 us (0.6 ms). That's a worst-case value. Most devices, but not all under worst-case conditions, should function with a 300 us ramp rate. Your prototype design should be fine, although Xilinx does not guarantee it with a 300 us ramp rate. Can you ignore it for your production design? Not if you want guaranteed success for every board. So what happens if you violate the specification? In the XC3S200, you could potentially trigger the aggressive ESD protection circuit. You will see additional current draw, but only if the VCCO ramps too fast. If the power supply doesn't have enough capacity, then the FPGA may fail to configure. If the supply does have enough capacity, then the FPGA will configure, but may still draw current. If the VCCO supply ramps slower than the Tcco specification, then you will never see this condition. The overly aggressive ESD circuit is tamed in the XC3S50 and XC3S1000 FPGAs available today. There is no ramp limit for these devices. If the ramp-rate is a concern in your design, the XC3S1000 is also available in a pin-compatible FT256 package. --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/II/IIE FPGAs http://www.xilinx.com/spartan3 --------------------------------- Spartan-3: Make it Your ASICArticle: 73556
>> Someone has said that the 5V PCI bus in modern PC's actually uses 3.3V >> signals. If this is the case, then I may not need any level shifting. >I'll >> measure the PCI voltages later today and post the results here. >Measuring the PCI voltages won't give you what you want. There are separate >pins for 5V and 3.3V and both may be present. A better indicator would be >where the keys are located in the bus connectors. If the key is near the >front (connector end) of the board, it is a 3.3V slot. If on the other end >of the connect it is a 5V slot. Universal PCI cards have a slot in both >locations so it can plug into either type slot. There is another possible meaning for "voltage". The levels of the signals on the data/control pins. For a one-off hack, I'd put a scope on the data bus and see if anything goes over 3V. (I did that on one system many years ago. It was a 5V system, but the signals never went above 3V.) Of course, you can shoot yourself in the foot if you add another card that does drive the data bus to 5V. Or didn't test things carefully enough and missed a board in your system that does it. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 73557
gvaglia@gmail.com (Guido) wrote in message news:<44f5f440.0409230231.4e64da8c@posting.google.com>... > Hi all! > My Xilinx Parallel Cable IV was lost during a travel and it needs 5 > weeks to receive another from Memec. You can order one from Xilinx's web site. They ship internationally. They got me mine in a couple of days. Cheers, JonBArticle: 73558
I've added Virtex4 support to HDLmaker. The new version, 7.2.5, is on the web at http://www.polybus.com/hdlmaker/users_guide/ HDLmaker is a free hierarchical Verilog generator licensed under a BSD style license. It generates hierarchical Verilog, simulation and synthesis scripts, pad rings, hyperlinked HTML versions of the Verilog code, schematics, and PADS PCB netlists. It also has a C like language which allows you do complex code generation. It primarily aimed at FPGA and ASIC design but can also be used for PC board design. The VHDL support has been deprecated.Article: 73559
"Hal Murray" <hmurray@suespammers.org> wrote in message news:_NWdnVIqFLodjM7cRVn-ug@megapath.net... > >> Someone has said that the 5V PCI bus in modern PC's actually uses 3.3V > >> signals. If this is the case, then I may not need any level shifting. > >I'll > >> measure the PCI voltages later today and post the results here. > > >Measuring the PCI voltages won't give you what you want. There are separate > >pins for 5V and 3.3V and both may be present. A better indicator would be > >where the keys are located in the bus connectors. If the key is near the > >front (connector end) of the board, it is a 3.3V slot. If on the other end > >of the connect it is a 5V slot. Universal PCI cards have a slot in both > >locations so it can plug into either type slot. > > There is another possible meaning for "voltage". The levels of the > signals on the data/control pins. > > For a one-off hack, I'd put a scope on the data bus and see if > anything goes over 3V. (I did that on one system many years ago. > It was a 5V system, but the signals never went above 3V.) > > Of course, you can shoot yourself in the foot if you add another > card that does drive the data bus to 5V. Or didn't test things > carefully enough and missed a board in your system that does it. > > -- > The suespammers.org mail server is located in California. So are all my > other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited > commercial e-mail to my suespammers.org address or any of my other addresses. > These are my opinions, not necessarily my employer's. I hate spam. > Yes, I hoping the signal levels (data, clock, reset, etc) never go above 3.3V. Even though the PCI system is 5V. I've lost the probes for my scope, so I can't check it until I get some more. The card is only a one off so this quick fix should be okay.Article: 73560
Hi, According to app not XAPP379, fast counters up to 40 bits long can be created. I need a 32 bit or so counter, clocked as fast as possible, so I thought I would start with the technique in the app note. It claims "basic CoolRunner-II CPLD AND gate...is 40 inputs wide". Maybe so, but I don't know how to get XST to recognize my intentions to use it in my VHDL code. Probably I don't know the syntax. Can anybody help me with a simple example? Thanks! -BobArticle: 73561
Hi Bob, It's not difficult at all to create a 40-input AND gate when targetting CoolRunner-II CPLDs. Simply create an equation in VHDL that goes something like: AND_GATE = input1 and input2 and input3 ... and input40; There is one additional step you do need to do - And that is, make sure that the software implementation property for "Collapsing Input Limit" is changed from 32 (default) to 40. (With a default setting of 32, you will be limited to a 32 input AND gate) Hope that helps! Mark Robert S. Grimes wrote: > Hi, > > According to app not XAPP379, fast counters up to 40 bits long can be > created. I need a 32 bit or so counter, clocked as fast as possible, > so I thought I would start with the technique in the app note. It > claims "basic CoolRunner-II CPLD AND gate...is 40 inputs wide". Maybe > so, but I don't know how to get XST to recognize my intentions to use > it in my VHDL code. Probably I don't know the syntax. Can anybody > help me with a simple example? > > Thanks! > -BobArticle: 73562
Now that the dust is starting to settle, I'd like to highlight the guidelines that Altera uses in involvement with this newsgroup. 1) We reactively respond to customer questions on both marketing and technical issues (if it is a marketing response, we may use a marketing person and clearly articulate the title of the poster). 2) We do not proactively start posts about our new products. 3) We respond to competitive commentary on our products, as not doing so implies agreement. 4) We refrain from personal attacks. 5) We refrain from competitive attacks unless provoked. My responses earlier this week addressed points 1, 3, and 5 above. There clearly are additional un-written guidelines with this newsgroup, and if I have offended anyone with my overt rather than covert marketing, I offer my apology. Thank you for the newsgroup etiquette training. Dave Greenfield Sr. Director of Propaganda & Ilk Altera CorporationArticle: 73563
Dave Greenfield wrote: > 2) We do not proactively start posts about our new products. I would rather like to see technical posts on new products. Xilinx used to have a section in their data sheets on how this generation/product differs from the previous generation/product and something along those lines would probably be of interest to a large fraction of the readership of the newsgroup. Maybe of special interest to those of us designing products while trying to keep broadly up to date on the technology...Article: 73564
According to this page http://www.xilinx.com/ise/products/webpack_config.htm, Webpack 6.3 supports both the XC3S1000 and XC3S1500. YAY! Unfortunately, when I go to the download link, the link is only for Webpack 6.2SP3. I just got my ISE 6.3 evaluation CDs (can be used either as a 60-day trial for Foundation ISE 6.3, or a unrestricted Webpack 6.3), and the CD-based Webpack 6.3 installation is limited to the XC3S400. So is the information on Xilinx's page just plain wrong, or are there plans to upgrade BaseX 6.3 and Webpack 6.3 to XC3S1000/1500?Article: 73565
Christoph Loew <christoph@zmp.co.jp> wrote in message news:<2qs9phF13h636U1@uni-berlin.de>... > It sounds as if your best aproach would be to find a sufficiently > documented evaluation board that fits your needs , maybe > http://www.parallax.com/detail.asp?product_id=60004 > (the schematics are downloadable from there) and re-design the PCB > to fit your space requirements as you suggested. I'd recommend > checking available souces for the parts before deciding on which > board to clone, some of the evaluation-board may use components > difficult to obtain for a hobbyist. > > That should save you a lot of headaches compared to doing everything > from scratch. > > Good Luck ! Thanks for the info, I'll definately consider doing so. What are the dimensions of the board you referred to, just so I know how much I would have to reduce it by? I can't check the schematics until I download the software for it. But I wonder if I'll be able to reduce it enough to fit my specifications. Would a double-sided board be the solution? -DarienArticle: 73566
Nicholas Weaver wrote: > > In article <41525983.F7389D7E@yahoo.com>, rickman <john@bluepal.net> wrote: > >I don't need to see the transistors, just a signal that they control. > >That would be in the metal. It may be hard to sort out, but I am sure > >that is orders of magnitude easier than cracking the key by brute > >force. > > However, those signals are still buried under 8 layers of metal, in a > flip-chip package, with live SRAM cells. Please explain this. The outputs from the RAM cells never leave the lowest layer of metal? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 73567
Duncan Entwisle <family*.*entwisle*@*btinternet*.*com> wrote in message news:<family*.*entwisle*-8C0815.14545223092004@newstrial.btopenworld.com>... > In article <8211d046.0409220228.7220a896@posting.google.com>, > abeaujean@gillam-fei.be (A Beaujean) wrote: > > > When trying to get help thru the HELP button and then the "Online > > Documentation' button, Adobe Reader starts and shortly displays a > > window saying "There was an error opening this document. The path does > > not exist", with no other indication whatsoever. > > I think this may be because one of the directories (e.g. "Program > Files") you installed the software in has a space in it. You'd need to > reinstall it somewhere else without any spaces. > > (This is a dim and distant memory - it may not be correct :-) Thank you for your answer. The problem does not appear to be there anyway. I installed under D:\WebPack\ Looking on Adobe Reader Web Site, it seems that this message comes out under Adobe for MAC OS (?) when the file opened has chinese characters in it ??? Very strange, since I run Windows XP and downloaded again Adode Reader free version to be sure, with the same result. Wait and see.Article: 73568
puzzled <puzzled@puzzled.com> wrote: : According to this page : http://www.xilinx.com/ise/products/webpack_config.htm, : Webpack 6.3 supports both the XC3S1000 and XC3S1500. YAY! : Unfortunately, when I go to the download link, the link : is only for Webpack 6.2SP3. : I just got my ISE 6.3 evaluation CDs (can be used : either as a 60-day trial for Foundation ISE 6.3, : or a unrestricted Webpack 6.3), and the CD-based : Webpack 6.3 installation is limited to the XC3S400. : So is the information on Xilinx's page just plain wrong, : or are there plans to upgrade BaseX 6.3 and Webpack 6.3 : to XC3S1000/1500? Wait some more days. There should be a corrected Webpack 6.3 available in some days. Ther was one released about a week ago, but it contained errors and was withdrawn. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 73569
Are you shure you can meet the timing with the single cycle access? With 50 MHz you have 20 ns, you can easily loose perhaps 10ns on tco for the address lines and the setup time for your input registers. I also would not use an input latch, try to use the clocked FFs. About write timing: Some SRAMS need a data hold after rising edge of nwe. Your timing between data out and nwe depends on the routing. To not waste an additional clock cycle on write I've used a neg-edge triggered FF for the nwe signal. In general, I would first try to get the interface running with relaxed timing, i.e. use wait states. For an example you can find the VHDL code I'm using for SRAM interfacing at my website (under download in jop.zip): mem.vhdl is for a simple 8 bit memory, mem32.vhdl (as the name implies) for 32 bit. Just delete the stuff for Flash and NAND access from the code, than it's straight forward to use. Martin ---------------------------------------------- JOP - a Java Processor core for FPGAs: http://www.jopdesign.com/ "mete" <mete@ieee.org> schrieb im Newsbeitrag news:acc68109.0409230527.38ff73f9@posting.google.com... > Hi, > > Thank you for the answers. I am talking about the fast async sram > manufactured by ISSI on the board. > > I have following code to read/write to/from async. sram on spartan-3 > starter kit. However, it is not working correctly. Does it seem to > work ? (then I may trace the bug anywhere else, this code is just a > piece of the whole project) or is there a problem on it ? > > Thanks in advance. > > Mete > > ----------------------------------------------------------------- > > clk is clock input (50Mhz) > ub, lb, oe, ce and we are sram control. > mdata sram bidirectional data. > maddr sram address. > udatain user data input. > udataout user data output. > uaddr user address. > addrvalid indicates the address on the uaddr is valid. > en indicates this address is for sram. > done indicates read or write operation has been completed. > > -- Uncontrolled Pins > lb <= '0'; > ub <= '0'; > > -- Controlled Pins > oe <= ctrl_oe; > ce <= ctrl_ce; > we <= ctrl_we; > > -- Output Tristate > process (ctrl_oe, udatain) > > begin > > if (ctrl_oe = '1') then > > mdata <= udatain; > > else > > mdata <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; > > end if; > > end process; > > -- Input Latch > process (ctrl_oe, mdata) > > begin > > if (ctrl_oe = '0') then > > udataout <= mdata; > > end if; > > end process; > ----------------------------------------------------------------- > > ----------------------------------------------------------------- > process (state, uaddr) > > begin > > case state is > > when init => > ctrl_ce <= '1'; > ctrl_oe <= '1'; > ctrl_we <= '1'; > maddr <= X"00000000"; > > done <= '0'; > > when idle => > ctrl_ce <= '1'; > ctrl_oe <= '1'; > ctrl_we <= '1'; > maddr <= X"00000000"; > > done <= '0'; > > when read => > ctrl_ce <= '0'; > ctrl_oe <= '0'; > ctrl_we <= '1'; > maddr <= uaddr; > > done <= '1'; > > when write => > ctrl_ce <= '0'; > ctrl_oe <= '1'; > ctrl_we <= '0'; > maddr <= uaddr; > > done <= '1'; > > end case; > > end process; > ----------------------------------------------------------------- > > ----------------------------------------------------------------- > process (clk, reset, en, addrvalid, rw) > > begin > > if (reset = '1') then > > state <= init; > > elsif rising_edge(clk) then > > case state is > > when init => state <= idle; > > when idle => if (addrvalid = '1' and en = '0') then > > if (rw = '1') then > > state <= read; > > else > > state <= write; > > end if; > > else > > state <= idle; > > end if; > > when read => state <= idle; > when write => state <= idle; > > end case; > > end if; > > end process; > -----------------------------------------------------------------Article: 73570
I couldn't find a full sample how work with DMA (HAL). I want to
write by DMA from SDRAM to some device with constant address.
I've wrote next source code:
//*********************************************************************
volatile int dma_complete = 0;
int* page1 =(int*)((int) SDRAM_BASE + 0x5E0000);
void DMA_VGA_Done(void*)
{
dma_complete=1;
}
void isr_dma(void* context, alt_u32 id)
{
alt_dma_txchan* tx = (alt_dma_txchan*) context;
if (dma_complete)
{
dma_complete = 0;
alt_dma_txchan_ioctl(tx, ALT_DMA_SET_MODE_32, NULL);
alt_dma_txchan_ioctl(tx, ALT_DMA_TX_STREAM_ON, (int*) VGA_BASE);
alt_dma_txchan_send(*tx, page1, 1024*768, DMA_VGA_Done, NULL);
}
}
int main(void)
{
alt_dma_txchan tx;
tx = alt_dma_txchan_open ("/dev/dma");
.....
alt_irq_register(DMA_IRQ, tx, isr_dma);
alt_dma_txchan_reg(tx);
alt_dma_txchan_ioctl(tx, ALT_DMA_SET_MODE_32, NULL);
alt_dma_txchan_ioctl(tx, ALT_DMA_TX_STREAM_ON, (void*) VGA_BASE);
alt_dma_txchan_send(tx, page1, 1024*768, DMA_VGA_Done, NULL);
while( 1 )
{
.....
}
alt_dma_txchan_close(tx);
fclose(lcd);
return(0);
}
//*********************************************************************
It doesn't work. Please, correct me if you know as.
Article: 73571Uwe Bonnes wrote: > puzzled <puzzled@puzzled.com> wrote: > : According to this page > : http://www.xilinx.com/ise/products/webpack_config.htm, > : Webpack 6.3 supports both the XC3S1000 and XC3S1500. YAY! > > : Unfortunately, when I go to the download link, the link > : is only for Webpack 6.2SP3. > > : I just got my ISE 6.3 evaluation CDs (can be used > : either as a 60-day trial for Foundation ISE 6.3, > : or a unrestricted Webpack 6.3), and the CD-based > : Webpack 6.3 installation is limited to the XC3S400. > > : So is the information on Xilinx's page just plain wrong, > : or are there plans to upgrade BaseX 6.3 and Webpack 6.3 > : to XC3S1000/1500? > > Wait some more days. There should be a corrected Webpack 6.3 available in > some days. Ther was one released about a week ago, but it contained errors > and was withdrawn. > > Bye Well, if webpack supports the XC3S1000/1500, will BaseX do the same ? I've recently bought BaseX (no sign of any upgrade in the post, mind, even though I've registered it etc...) but had resigned myself to using a '400 part because there's no way I could justify $3k (after tax/import duty/shipping) for Foundation. I'll be a bit miffed if the free version can do more than the pay-for version though... (The real reason to buy BaseX was to use Linux. Webpack was the only thing I still had to use XP for, and the hassle of closing down everything just to use Webpack was a real pain...) SimonArticle: 73572
Hi all, We are working with a Memec development board with a Xilinx Virtex-II Pro FPGA. The idea was to run VxWorks on this board. But we seem to have a bit of problems. And it seems very hard to find resources on the internet that uses VxWorks with Xilinx FPGA's. So I was hoping that anyone here could suggest some places to look out. Also right now we do not have the com module, so no ethernet and no flash. But we load the SDRAM with the vxworks executable and then jump to that address. Is that a good way, or do you have to go through some ROM-loader? All help would be greatly appreciated! With regards Jonas FlodenArticle: 73573
Hello I have some state machines in kiss which I am converting to the verilog format. I would like to encode this verilog with binary, 1-hot, jedi and gray and after that to synthetize them in ISE. I have tried to find out how to do it, but I was unsuccessful Do someone knows the solution thank you in advance regards DominikArticle: 73574
>Tuukka Toivonen wrote: >> Hi all. I'm looking for FPGA for real-time video processing. >> The requirements are not yet fixed [...] Thanks for the help. I'll reply to some posts below. >From actela@nowhere.net Mon Sep 20 16:53:27 2004 >AVNET sells a Spartan3 and Virtex2p development board. >Both have PCI edge-connectors. >Oh, don't forget you'll need to get Foundation ISE (another +$2400 ISE.) Yeah, but I do need some other software too, don't I? At least for uploading the FPGA configuration created with the ISE. Is that available for Linux for the AVnet boards? (I didn't find any word on that so I passed the board last time) >From neeraj_varma@yahoo.invalid Tue Sep 21 13:04:00 2004 >--For the PowerPC development, EDK is pretty self sufficient which includes >the GNU toolchain for IBM405. It does not include any RTOS (except a small >Xilinx kernel, XMK). If you want to run VxWorks on PPC, you need to get that >separately, ditto for other supported RTOSs' Well, I'd love to run Linux on the PPC too :) EDK/XMK might be sufficient in the beginning... or maybe I could just ignore the PPC cores on the FPGA for the beginning and worry about that later. I suppose the Xilinx FPGA can be used without utilizing the PPCs? >From Steve Williams Mon Sep 20 16:53:24 2004: >How much do you want to spend? We actually have a board >we are working on that has all these goodies, plus camera >link, sdram, and a PPC. But I think you'd be looking at a >few (a small few?) thousand dollars:-/ That sounds like a reasonable price range, yes. >What sort of camera? I've used Firewire DV-camera when needed, but the most common way has been to read video from harddisk. Real-time capable FPGA would make the camera more useful. >The scope of what you are talking about is significant for >a first time FPGA designer! Well, I have been writing VHDL for years now... it's just that software simulations tend to be a "bit" slow.
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