Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Symon wrote: > Hi Pepper, > I'd recommend using a Google Groups search of comp.arch.fpga to find > yourself a suitable evaluation board, vga answers, etc. All this stuff gets > chatted about on here a lot. You could also look at Xilinx's website; they > have a cheap'n'cheerful $99 Spartan-3 board which might be a good start for > you. > Have fun, Syms. > "Pepper Orlando" <woodenbicycle@hotmail.com> wrote in message > news:c00eb680.0409200944.59cf7540@posting.google.com... > >>I'm just an undergrad student, but I am interested in getting started >>in some FPGA projects. I would really like to some day build up a >>usable SoC system to play with. OpenCores.org has been fun site to >>read through. I envision something with a RISC core, ethernet, usb >>(HID) and some sort of vga/lvds/dvi. What would be the best way to get >>started? Can you recommend some software and a EVB for someone >>learning the basics but wanting to expand over time? >>Thanks in advance! > > > Hi, The Spartan-3 board is designed by Digilent http://www.digilentinc.com/. They have a few peripheral boards you can add on to it, like additional memory, USB2, or Ethernet interface. I have an old Spartan 2 board from them and got now an USB2 interface for it. The interface connectors are the same, so I can use that interface with the new Spartan-3 board offered via Xilinx as well. Like their concept about the interface, though the board gets big when you add all the peripherals on the outside of it. GuenterArticle: 73476
Austin Lesea <austin@xilinx.com> wrote in message news:<cipgm9$k711@cliff.xsj.xilinx.com>... > Also, making analog elements in a straight CMOS logic process is no > simple task either. Digital process guarantees that the transistors > switch on, and off, quickly. That is about it. Try to make an analog > design in a digital process that will yield 100%. > > All extremely challenging, and by no means a solved problem. Perhaps Broadcom and Silicon Labs should start making FPGAs. :) JakeArticle: 73477
Maybe I am missing something, but wouldn't you just drive all the chips with one onboard clock then in your code trigger the processes on the rising edge? Don "Leroy Tanner" <ikeepthespiritalive@freenet.de> wrote in message news:cirft3$j4c$1@mamenchi.zrz.TU-Berlin.DE... > Hello newsreaders, > > For a while I have been confronted with the following task which I find > quite challenging but unfortuantely didn't manage to solve it, yet. > What I want to do is to use 2-4 FPGAs (Xilinx Virtex 2 Pro) together on > one > printed circuit board (PCB). They are used to process a large amount of > incoming serial data (data rates of several GHz's). My idea is to handle > that data parallel by the 2-4 FPGAs. But now there arises the problem how > to > adequately split the data and how to synchronize the FPGAs among one > another, in particular? > Is it possible or first of all a realistic idea to synchronize multiple > FPGAs in the GHz range? How can this be done without much protocoll > overhead? I would like to do it without applying an extra transfer > protocoll > among the FPGAs just for that purpose! Up to this date I didn't find a > proper solution, yet. > Maybe someone can give me a hint? Any ideas how to solve that problem? > > Regards, Leroy Tanner > >Article: 73478
How recoding this algorithm using variables and then assign the answer to the signal as the last step? By using variables the code should run faster as well. Don "Jim Lewis" <Jim@SynthWorks.com> wrote in message news:4151023D.50302@SynthWorks.com... > Victor, > Cool problem. My analysis starts with the original code. > >> proc1 : PROCESS (In1, In2, OutA) IS >> BEGIN >> IF (In1 = '1' OR >> (In2 = '1' AND OutA = '1')) THEN >> InternalSig <= '1'; >> ELSE >> InternalSig <= '0'; >> END IF; >> END PROCESS proc1; >> >> proc2 : PROCESS (In0, In3, InternalSig) IS >> BEGIN >> IF (In0 = '1' AND >> (In3 = '1' OR InternalSig = '1')) THEN >> OutA <= '1'; >> ELSE >> OutA <= '0'; >> END IF; >> END PROCESS proc2; > > Rewriting this as assignments: > InternalSig <= In1 or (In2 and OutA) ; > OutA <= In0 and (In3 or InternalSig) ; > > Rewriting the assignment as a single assignment to OutA: > OutA <= (In0 and In3) or (In0 and In1) or (In0 and In2 and OutA) ; > > My biggest concern is with the feedback term = > (In0 and In2 and OutA) effect the output? "In0 and In2" > cannot set the output, but "In0 and In2" can extend it once > it has already been set. Already been set includes a glitch > that sets In3 briefly when In2 is also set. > > Would I leave this in my circuit? It depends on where it > is and why I need it in there. Is it at one of the primary > inputs operating on signals that you have no control over? > What are the other timing paths? I would be working to > understand these before I left it in the circuit. > It could be ok under certain conditions, but I would make > sure I understand them. > > > I would be interested in hearing this issue addressed from an ASIC > > design > > point of view as well. > > From an ASIC point of view, combinational logic feedback > on the inside of a design can lead to a test issue. > Again if it is at the IO of a design, you may be ok. > > > Even if detailed analysis says it is ok, my first > instinct is to remove something like this if at all > possible. Is there something in the actual behavior > of the inputs In0, In1, In2, or In3 that would allow you > to eliminate some of the possible states of the circuit? > My preference when working with history/state information > is to use registers if at all possible. This may cost > you more hardware resources, but would be worth it if > it resulted in a circuit that is more stable than what > you have now. > > Since there are order dependencies in the circuit, > simply simulating an algorithmic sequence is not > enough to prove they are the same. You will need to > run particular sequences. > > Cheers, > Jim > -- > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > Jim Lewis > Director of Training mailto:Jim@SynthWorks.com > SynthWorks Design Inc. http://www.SynthWorks.com > 1-503-590-4787 > > Expert VHDL Training for Hardware Design and Verification > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > > > Victor Hannak wrote: > > I am working on synthesizing some legacy code, and Synplify (correctly) > > finds a combinatorial loop in the logic. My gut reaction was to modify > > the > > function to use a latch instead of a feedback path because I've always > > been > > told that combinatorial loops are bad practice for ASICs / FPGAs. After > > completing the redesign, the new circuit takes up at least twice as much > > space as the old one and it is difficult to exhaustively verify that the > > re-implementation preserves the functionality. > > > > The combinatorial loop implementation is in a product, and has been > > working > > without problems (presumably) for years. So the question I would like > > to > > present for discussion is: > > > > Why is it so bad to use combinatorial loops? What are the potential > > pitfalls? > > > > I would be interested in hearing this issue addressed from an ASIC > > design > > point of view as well. > > > > For reference, I am including below a testbench I created to test the > > various implementations. The first two process represent the original > > implementation and create the OutA output. The 3rd and 4th processes > > represent the latch based implementation. The 5th process is an > > (almost) > > exhaustive testbench to verify that the two implementations behave the > > same > > way. > > > > Thanks > > > > > > > > LIBRARY ieee; > > USE ieee.std_logic_1164.ALL; > > USE ieee.numeric_std.ALL; > > > > > > ENTITY test IS > > END ENTITY test; > > > > ARCHITECTURE test_arch OF test IS > > > > SIGNAL Latch : STD_ULOGIC; > > SIGNAL In0 : STD_ULOGIC; > > SIGNAL In1 : STD_ULOGIC; > > SIGNAL In2 : STD_ULOGIC; > > SIGNAL In3 : STD_ULOGIC; > > SIGNAL InternalSig : STD_ULOGIC; > > SIGNAL OutA : STD_ULOGIC; > > SIGNAL OutB : STD_ULOGIC; > > SIGNAL TestVector : UNSIGNED(3 DOWNTO 0); > > > > BEGIN > > > > proc1 : PROCESS (In1, In2, OutA) IS > > BEGIN > > IF (In1 = '1' OR > > (In2 = '1' AND OutA = '1')) THEN > > InternalSig <= '1'; > > ELSE > > InternalSig <= '0'; > > END IF; > > END PROCESS proc1; > > > > proc2 : PROCESS (In0, In3, InternalSig) IS > > BEGIN > > IF (In0 = '1' AND > > (In3 = '1' OR InternalSig = '1')) THEN > > OutA <= '1'; > > ELSE > > OutA <= '0'; > > END IF; > > END PROCESS proc2; > > > > > > proc3 : PROCESS (In0, In3, In1, In2, Latch) IS > > BEGIN > > > > IF (In0 = '0') THEN > > OutB <= '0'; > > ELSE -- IF (In0 = '1') THEN > > IF (In2 = '0') THEN > > OutB <= In3 OR In1; > > ELSE -- IF (In2 = '1') THEN > > OutB <= Latch; > > END IF; > > END IF; > > > > END PROCESS proc3; > > > > proc4 : PROCESS (In0, In3, In1) IS > > BEGIN > > > > IF (In0 = '0') THEN > > Latch <= '0'; > > ELSIF (In3 = '1' OR In1 = '1') THEN > > Latch <= '1'; > > ELSIF (In2 = '0' AND In1 = '0') THEN > > Latch <= '0'; > > END IF; -- note that there is no else statement here, thereby > > inferring > > a latch > > > > END PROCESS proc4; > > > > > > stim : PROCESS IS > > BEGIN > > > > FOR i IN 0 TO 15 LOOP > > > > TestVector <= to_unsigned(i, 4); > > WAIT FOR 1 ns; > > ASSERT (OutA = OutB) REPORT "Error found" SEVERITY error; > > > > FOR j IN 0 TO 3 LOOP > > TestVector(j) <= NOT TestVector(j); > > WAIT FOR 1 ns; > > ASSERT (OutA = OutB) REPORT "Error found" SEVERITY error; > > END LOOP; > > > > END LOOP; > > > > WAIT; > > > > END PROCESS stim; > > > > In0 <= TestVector(0); > > In1 <= TestVector(1); > > In2 <= TestVector(2); > > In3 <= TestVector(3); > > > > > > END ARCHITECTURE test_arch; > > > > > > > -- > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > Jim Lewis > Director of Training mailto:Jim@SynthWorks.com > SynthWorks Design Inc. http://www.SynthWorks.com > 1-503-590-4787 > > Expert VHDL Training for Hardware Design and Verification > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~Article: 73479
Hi all,
Using Xilinx' XST, I want to add a VHDL "loc" constraint to a signal
within a sub-component, without having to export the signal to the
outside world via the entity's "port" declaration.
I tried the following:
-------
entity Blinky is
port(CLK: in std_logic);
end entity Blinky;
architecture arch of Blinky is
signal LED: std_logic_vector(7 downto 0);
attribute LOC: string;
attribute LOC of LED: signal is "P11 P12 N12 P13 N14 L12 P14 K12";
process (CLK) is
variable counter: std_logic_vector(23 downto 0);
begin
if rising_edge(CLK) then
if counter = 0 then
LED <= not LED;
end if;
counter <= counter + 1;
end if;
end process;
end architecture arch;
-------
... But alas, this doesn't work.
Does anyone know if it is possible to obtain the intended behavior
from XST, and, if yes, how?
Best regards,
Sidney Cadot
Article: 73480Post Below... "Don Golding" <dgolding@sbcglobal.net> wrote in message news:Prf4d.24210$uJ3.5681@newssvr29.news.prodigy.com... > Maybe I am missing something, but wouldn't you just drive all the chips with > one onboard clock then in your code trigger the processes on the rising > edge? > > Don > > "Leroy Tanner" <ikeepthespiritalive@freenet.de> wrote in message > news:cirft3$j4c$1@mamenchi.zrz.TU-Berlin.DE... > > Hello newsreaders, > > > > For a while I have been confronted with the following task which I find > > quite challenging but unfortuantely didn't manage to solve it, yet. > > What I want to do is to use 2-4 FPGAs (Xilinx Virtex 2 Pro) together on > > one > > printed circuit board (PCB). They are used to process a large amount of > > incoming serial data (data rates of several GHz's). My idea is to handle > > that data parallel by the 2-4 FPGAs. But now there arises the problem how > > to > > adequately split the data and how to synchronize the FPGAs among one > > another, in particular? > > Is it possible or first of all a realistic idea to synchronize multiple > > FPGAs in the GHz range? How can this be done without much protocoll > > overhead? I would like to do it without applying an extra transfer > > protocoll > > among the FPGAs just for that purpose! Up to this date I didn't find a > > proper solution, yet. > > Maybe someone can give me a hint? Any ideas how to solve that problem? > > > > Regards, Leroy Tanner > > > > > > Start Post.... It gets tricky when you have multiple FPGAs clocked at hundred(s) of MHz. I don't have any direct expeience there, but I think looking for appnotes on vendor sites that address "Board Level De-skew" (using FPGA clocking resources to account for clock distribution headaches) and specifically for Xilinx, "Channel bonding" (using multiple RocketIO transceivers to receive data in parallel). The RocketIO transceivers are difficult beasts, at least if you're not using a standard protocol. I'm not sure if the channel bonding can span multiple V2pro devices, but I know it can span multiple transceivers. Not sure on your budget, or application requirements, but it may be worthwhile going to a single, larger part that contains the resources you need. It at least partially removes the headache of high-speed PCB design/layout. --Josh ModelArticle: 73481
"Chris Alexander" <info@bostonsemiconductor.com> wrote in message news:376c28cd.0409220408.5da521d7@posting.google.com... > Just so! There is more marketing jive going on here than just from > Altera. Being new to this group, I thought this was a Xilinx only > area until the "infamous posts" showed up. > > I look forward to the technical threads, but the hype from anyone > (including Austin) I skip over. > > One more poster to add to the "skip-over-list". Much of Austin's stuff is worth reading. Occasionally though, he goes into over-the-top marketing mode. PeteArticle: 73482
In verilog,
{cout, sum} = in1 + in2 + cin;
will perform an addition of width max({cout, sum}, in1, in2, cin).
The statement that "the width for + is maximum of the width
of the two operands" is true if "a+b" is in isolation ('self-determined'
in Verilog terms).
However, for c = a+b, then the operands are extended to width
max(a,b,c), and only then is the addition performed.
Shalom
glen herrmannsfeldt wrote:
> rickman wrote:
>
> > Actually, what you are describing is a VHDL coding issue, not a MAP
> > issue. If you want a 21 bit result from a VHDL add (I don't know
> > Verilog well enough to say) you have to have at least one 21 bit input.
> > VHDL won't assume that you expect a 21 bit result.
>
> I am not sure about verilog. If I assign to a variable
> the same width as the operands of +, I get warnings
> about truncated bits.
>
> One book says that {cout, sum} = in1 + in2 + cin;
> will generate a full adder.
>
> Another book says that the width for + is maximum of the width
> of the two operands.
>
> cross posted to comp.lang.verilog, to see if anyone there can say.
>
> -- glen
--
Shalom Bresticker Shalom.Bresticker @freescale.com
Design & Verification Methodology Tel: +972 9 9522268
Freescale Semiconductor Israel, Ltd. Fax: +972 9 9522890
POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 5441478
[ ]Freescale Internal Use Only [ ]Freescale Confidential Proprietary
Article: 73483Derek_SImmons@msn.com (Derek Simmons) wrote in message news:<14030831.0409211923.4840b077@posting.google.com>... > > > > For many years, I have teased Altera about their absence from this ng, and > > later I have welcomed Paul Laventis for his positive contributions. But I > > will have nothing in common with Dave Greenfield. > > > > I don't feel this is true. Some of the questions I have posed about > Altera and their devices I have gotten response from individials from > Altera. Their responses have 'right on the ball' and very helpful. > > Now if they only offered a NIOS II Development Kit with EP2S60... > > Derek Simmons :-) The 'new' Nios II kit with the EP2S30, comes with an EP2S60 device on the board. My 2 cents, Karl.Article: 73484
Austin Lesea wrote: > Ben, > > KEEP or SAVE. > > Austin > > Ben Jackson wrote: > >> In article <6fO3d.84788$D%.79178@attbi_s51>, >> Kevin Neilson <kevin_neilson@removethiscomcast.net> wrote: >> >>> There was a thread about ring oscillators recently. I tried to build >>> one in >>> a Xilinx V2Pro and found, as I suspected, that the ISE tools >>> collapsed the >>> ring of inverters into a single inverter. >> >> >> >> Maybe the KEEP attribute would work? >> >> http://toolbox.xilinx.com/docsan/xilinx6/books/data/docs/cgd/cgd0125_78.html >> >> Thanks, guys. I used KEEP and SAVE and had to really fight the tools to keep everything from getting pruned and merged, but I finally got it to work. -KevinArticle: 73485
Hi, Can you provide me a code piece to use async. sram e.g. in spartan-3 starter kit ? I could not get it work. Thanks in advance. MeteArticle: 73486
mete <mete@ieee.org> wrote: : Hi, : Can you provide me a code piece to use async. sram e.g. in spartan-3 : starter kit ? I could not get it work. You can't use BRAM as asynchronous memory. A clock is always needed for the BRAMS Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 73487
well that's the way i always do it you could also make the pps_edge registred with a FF "Rune Christensen" <rune.christensen@adslhome.dk> wrote in message news:415148e7$0$232$edfadb0f@dread12.news.tele.dk... > > "Jeroen" <jayjay.1974@xs4all.nl> skrev i en meddelelse > news:41513083$0$78738$e4fe514c@news.xs4all.nl... > > > > "Rune Christensen" <rune.christensen@adslhome.dk> wrote in message > > news:415121e2$0$302$edfadb0f@dread12.news.tele.dk... > >> Hello > >> > >> I have created an edge reset on a counter by using two flipflops > >> http://old.iot.dk/jjm/adsen/VHDL/KnowHow/Edge_Reset/edge_reset.htm > > > > This is asynchronous design which should be avoided. > > > >> reset : process(e_rst, e_rst_rst) > >> begin > >> if (e_rst_rst = '1') then > >> s_rst <= '0'; > >> elsif (e_rst'event and e_rst = '1') then > >> s_rst <= '1'; > >> end if; > >> end process reset; > >> > >> reset_reset : process(clk) > >> begin > >> if (clk'event and clk = '1') then > >> if (s_rst = '1') then > >> e_rst_rst <= '1'; > >> else > >> e_rst_rst <= '0'; > >> end if; > >> end if; > >> end process reset_reset; > >> > >> But is it possible to simplify edge reset? > >> > >> I have tried this from > >> http://www-ee.eng.hawaii.edu/~msmith/ASICs/HTML/Book/CH12/CH12.6.htm > >> > >> counter : process(a_rst, e_rst, clk) > >> begin > >> if (a_rst = '1') then > >> cnt <= 0; > >> elsif (e_rst'event and e_rst = '1') then > >> cnt <= 0; > >> elsif(clk'event and clk = '1') then > >> cnt <= cnt + 1; > >> end if; > >> end process counter; > >> > >> But xilinx will not accept the "elsif (e_rst'event and e_rst = '1') then" > >> > >> Thanks > >> Rune Christensen > >> > > > > No synthesizer will accept it, because there is no way to synthesize it. > > Think hardware ;) The clk'event and clk='1' is a indication to the > > synthesizer that you want a flipflop on the outputs after the > > combinatorial > > logic you describe in the process. There can only be one such statement. > > > > This is the way: > > > > signal reset_0,reset_1; > > signal cnt:integer; > > process(clk) > > begin > > if a_rst='1' then --asynchronous reset in > > cnt<=0; > > elsif clk'event and clk='1' then > > > > reset_0<=s_rst; -- synchronous reset in > > reset_1<=reset_0; > > > > -- detect edge on s_rst > > if reset_0='0' and reset_1='1' then > > cnt<=0; > > else > > cnt<=cnt+1; > > end if; > > end if; > > end process; > > > > Hope this helps, > > > > Jeroen > > > > > > > > Thanks for the answer. > I have created the following from your description > > p_pps_edge : process(rst, clk) > begin > if (rst = '1') then > pps_edge_old <= '0'; > elsif (clk'event and clk = '1') then > pps_edge_old <= pps; > end if; > end process p_pps_edge; > > pps_edge <= not pps_edge_old and pps; > > Hope this is correct :-) > pps is an input pin with a signal comming from a acutime2000 GPS reciever > (pulse per second). > > > Cheers > Rune > >Article: 73488
Hello , got a problem with the SOPC-Builder from Altera. I made a new Project in Quartus2, and added a MEGAFUNCTION from SOPC. In the SOPC i added the NIOS2 Core, OnChip Memory, Jtag UART and Serial UART. When I try to generate the code, an error occurs. here is the whole logfile: Altera SOPC Builder Version 4.10 Build 208 Copyright (c) 1999-2004 Altera Corporation. All rights reserved. # 2004.09.22 18:17:35 (*) mk_custom_sdk starting # 2004.09.22 18:17:35 (*) Reading project C:/test/NIOS/templates_microtronix/standard_32_nios/ref_32_system.ptf. # 2004.09.22 18:17:35 (*) Finding all CPUs # 2004.09.22 18:17:35 (*) Finding all available components no install.ptf file found at c:/altera/quartus41/sopc_builder/bin/europa/europa_utils.pm line 1700. Error in processing. System NOT successfully generated. Has anyone an Idea what the problem could be? Thanks RomanArticle: 73489
...or at least take all the high speed serial stuff into one FPGA and distribute it from that one to the others at a slower parallel rate. Also, it looks like V4 could take care of this with its ChipSync thingy for source synchronous application. Cheers, Syms. "Josh Model" <model@ll.nospam.mit.edu> wrote in message news:iWf4d.45> > Not sure on your budget, or application requirements, but it may be > worthwhile going to a single, larger part that contains the resources you > need. It at least partially removes the headache of high-speed PCB > design/layout. > > > --Josh ModelArticle: 73490
Is it possible to generate SVF files for operations other than just programming a FGPA/CPLD in Quartus? In Xilinx ISE impact I can make a batch files which looks like (batch.imp): setMode -bsfile setCable -port svf -file get-epm7128-idcode.svf addDevice -p 1 -file 7128aet100.bsd readIdcode -p 1 quit Then I can run this by: impact -batch batch.imp and get a SVF file which will read the idcode and compare it to the expected value found in the BSDL file. Is something like this possible in Quartus? (I don't mean "set_global_assignment -name GENERATE_SVF_FILE ON" to get a SVF file to program the FPGA). Thanks Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 73491
Petter Gustad <newsmailcomp5@gustad.com> writes: > I have a RocketIO simulation environment including a working > testbench running using ISE 4.2iSP2, VCS 5.1 under Solaris 5.1. > However, this is a slow and outdated machine and I'm trying to > migrate it to a newer environment, namely ISE 62iSP3, VCS 7.1.1 Could anybody here confirm that the combination VCS 7.1.1 and the RocketIO swift model in ISE 6.2i SP3 under Linux or Solaris 9 actually works? Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 73492
hpa@terminus.zytor.com (H. Peter Anvin) writes: > I just noticed yesterday that according to the schematic there is no > configuration EEPROM for the NIC on the Altera Nios development kit > (Cyclone edition.) Yet my board has a MAC which looks relatively > random (00:07:ed:0b:06:81). 00:07:ed is a prefix assigned to Altera. > > So... where is this number stored or derived from, if there is no > EEPROM? I'd like my own design to be compatible with the backup image > on the board, preferrably across multiple boards. I think it's stored in the FLASH, even though you can set it to whatever you like. The nr_plugs_initialize function has a pointer to a struct containing the MAC address. If you look at hello_plugs.c you will see something like: settings.ethernet_address.u32=0x11121314; settings.ethernet_address.l16=0x1516 + nr_timer_milliseconds(); Where one part is fixed and the other is simply a random (well, sort of) value. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 73493
Good information, but perhaps not the information pursued. I was thinking the same thing when I first read the post. Does anyone have experience with the "1M-byte of Fast Asynchronous SRAM (512Kx16 or 256Kx32)" that's included on the Spartan-3 starter board to help the original poster? "Uwe Bonnes" <bon@elektron.ikp.physik.tu-darmstadt.de> wrote in message news:cis8h9$pgs$1@lnx107.hrz.tu-darmstadt.de... > mete <mete@ieee.org> wrote: > : Hi, > > : Can you provide me a code piece to use async. sram e.g. in spartan-3 > : starter kit ? I could not get it work. > > You can't use BRAM as asynchronous memory. > > A clock is always needed for the BRAMS > > Bye > -- > Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 73494
Until you compile it on a different revision of the tools :-O
In circumstances like this, I find it easier to just instantiate the primitives for
what you want, taking away any room for 'creativity' by the tools. Instantiation
also lets you place the bits so that you can get reasonably consistent timing from
run to run.
Kevin Neilson wrote:
>
> >>
> Thanks, guys. I used KEEP and SAVE and had to really fight the tools to
> keep everything from getting pruned and merged, but I finally got it to
> work.
> -Kevin
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 73495
Hi Jim/All,
So after discussing it with Austin and Peter, we believe that
it might indeed be possible to generate 32 different phases of clock
in V4. You will need to use 8 DCM's 4 in the top half of the chip and
4 in the bottom half of the chip. Each DCM can generate 4 phases
0,90,180,360 and can be offset by a delay of 1/32 of the clock
from the other DCM's. Routing the same input clock to all 8 DCM's
may require using two different IO pins one for each half of the
chip. The use of two IOB pins may create some systemic skew
between 16 phases and the other 16 phases - but the IOB Idelay
should help minimize that.
I am not an expert on a lot of this (IOB/DCM) but I think it is
feasible. Jim, perhaps you could try implementing it in V4 - and
if you run into any problems - I am sure Austin/Peter could
help you. At the very least generating 16 phases should be a cinch.
- Vic
Jim Granville wrote:
>
>
> So, supposing someone wants to create a 'phased array' of clocks,
> to push their time-resolution well below the 1/clock, ( as in other
> threads ) what is the practical limit in Virtex-4, for the number of DCM
> controled phases that can be generated, AND dispersed thru the chip ?
> ( IIRC earlier DCM's had just 4 phases ).
> Can each of the 32 global clock buffers be driven to +1/32 phase
> advance, for example ?
>
> -jg
Article: 73496Hi, I'm planning on connecting a 3.3V Spartan 2E FPGA to the 5V PCI bus. To deal with the bidirectional level shifting I was hoping I could just use 100 ohm resistors. The FPGA datasheet does say that the device is 5V tolerant if used with 100 ohm resistors. Has anyone any experience of interfacing 3.3V FPGA's to 5V devices? Would using 100 ohm resistors be okay for the bidirectional signals? The PCI specification states that the minimum high voltage is 2V, which is well within the FPGA's 3.3V output. So is it okay to drive the 5V input signals from the 3.3V FPGA outputs? Thanks for any help,Article: 73497
Hi, You might find XAPP646 on the Xilinx website helpful. There are a number of ways you could approach the problem you are facing. I don't know if the 100 ohm resistor approach was designed with the PCI bus in mind. Instead you may want to consider "bus switches" which seem to be the most common solution for this problem. Either way, use of external parts like this is not compliant with the spec. Some people demand full compliance. If you have the option, I personally think the best thing to do is use Spartan-II (instead of Spartan-IIE) because you can connect it directly to a 5V PCI bus. Sometimes this is not possible due to pricing, or other features you need, but it eliminates external components and is compliant. EricArticle: 73498
Hi all, I just wonder if someone in the US could comit the following: ALTERA will bring out an update for its SOPC set featuring the MMU and optional a FPU for the NIOS-II system. These enhancements shall be availabel this year? This would make it possible to run standard unix like Linux (MMU required) ... Best Regards MarkusArticle: 73499
kathy wrote: > > for Loc drop-down box, there sre T,L,R,TL,TR,BL,BR,RT,RB,LT,LB. What they mean? T = top L = left R = right TL = top left TR = top right BL = bottom left ... you get the idea. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z