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I am interested in adding a "busy" signal to the Input/Ouptut port of the Picoblaze. This will allow me to add a Wishbone wrapper to the picoblaze and allow me to used some free wishbone cores from Opencores.org. Since the picoblaze is written using xilinx primatives the VHDL code is a little hard to follow. On to my question: Has anyone put together a block diagram of the internal signal connections of the picoblaze? The Xilinx documantation I've seen doesn't "pictorially" show the internal signal connections. I'm willing to look through the code and put together a diagram, but if someone else has done it and could save me some time... great! Thanks, Eric Holland ericjohnholland@hotmail.comArticle: 72976
Alan wrote:
> subtype wordT is std_logic_vector(15 downto 0); -- e.g.
> type RomT is array (0 to 1023) of wordT;
> constant MyRom : arrayT := FNFillRom("file name");
>
> The advantage of this is that the ROM gets filled during elaboration,
> and so is instantly available at time 0. The disadvantage is there's
> no direct link to synthesis - unless I suppose you write the function
> to read in the file in the format that your target technology
> supports.
Another possible solution is to use perl or bash
to convert the external hex file to a deferred
constant package body something like:
constant MyRom : arrayT :=
(
-- begin data
x"0000",
x"0001",
x"0002",
x"0004",
x"0008",
x"0010",
x"0020",
x"0040"
-- ...
-- end data
);
This would give you synthsizable code,
but require running the script and
a "vcom myPackageBody.vhd" for
each iteration.
-- Mike Treseler
Article: 72977roller wrote: > > and as for accessing an internal signal, i know that you can "up" hierarchy > by specifiying it's full "pathname", but i dont know if it works "down" > hierarchy, you can always try. I was trying to do that, but I can't figure out the format for specifying the heiarchy. I looked in the LRM and could not find any references to that. What is used as separators in a "path" name? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 72978
"rickman" <spamgoeshere4@yahoo.com> escribió en el mensaje news:4140967F.2EF867B@yahoo.com... > roller wrote: > > > > and as for accessing an internal signal, i know that you can "up" hierarchy > > by specifiying it's full "pathname", but i dont know if it works "down" > > hierarchy, you can always try. > > I was trying to do that, but I can't figure out the format for > specifying the heiarchy. I looked in the LRM and could not find any > references to that. What is used as separators in a "path" name? > it's the dot like in Ada (and Java, or like "use work.package.all") though it's been a long time since i read about it (plus i havent ever used it) maybe you can check the visibility rules or tutorials explaining that, sorry i couldnt help you more http://tech-www.informatik.uni-hamburg.de/vhdl/doc/faq/FAQ1.html#visibilityArticle: 72979
Oh, thanks a lot, Subroto, In order to get the CD I could have mailed my favourite Altera dealer straight away. The purpose was more to let off some steam about the process involved. I'm having a valid license with dongle, that should be sufficient, no ? But thanks for prefetching the delivery, this is appreciated. Rene Subroto Datta wrote: > Hi Rene, > > I know a CD is available if requested. I wil forward this > to the person > responsible for this so that he can get you the CD. > > Subroto Datta > Altera Corp. > > "Rene Tschaggelar" <none@none.net> wrote in message > news:413e208e$0$700$5402220f@news.sunrise.ch... > >>I got a mail that SP1 of the Quartus2 V4.1 was available >>for download. >>After a few unsuccesfull login attempts, partly due >>to the overloaded server partly due to me not knowing >>the login parameters, my motivation to download the 120MB >>or so vanished. >>Anyone knows whether the paying users get this update on >>CD mailed home ?Article: 72980
My company is going to start getting into the area of digital signal processing for one of our projects. FPGAs seem to be what we need, however I am a little foggy on how many gates to expect we need. Can someone give an example of how many gates can preform a specific operation in order to get a little better understanding on the number I need. Thanks!Article: 72981
Hi, all I have timing violation with a sdram controller design. The function , post map simulation works fine( except some initialise timing violation, I think I can ignore it, right ? ). My target platform is virtex II 250. Input clock 25Mhz is doubled with mirrored DCMs to get internal and external 50MHz. External 50Mhz goes to drive MICRON sdram 256Mb ( mt48lc16m16a2 ). The internal 50Mhz and ext 50Mhz are not aligned perfectly, some delay is there. In post par simulation, I got "X" with 2 bits on data bus, but not on whole write data cycles . The micron sim module reports timing violation here and there. I doubt many timing violation from micron module can be ignored, because when I simulates xapp134, there are endless timing violations, but xilinx says the design is validated. :) The hardware test shows several bits can be read after write, but the bits after X are wrong. I have not imposed UCF constraints yet. My question is how can I get rid of these "X" ? Can the delay between int/ext clk be got rid of or it is not important. How about the Setup/Hold timing violation reported by micron module ? I have put the wave output and text output at, please have a look. http://mitglied.lycos.de/dxslyz/fourphotogalery.html please excuse me not know how to post the link to be click friendly. Thanks in advance for any suggestions. Steven Yu. Following is the text output from modelsim. # tb_1.micron256 : at time 1318.0 ns AREF : Auto Refresh # tb_1.micron256 : at time 1478.0 ns LMR : Load Mode Register # tb_1.micron256 : CAS Latency = 2 # tb_1.micron256 : Burst Length = 8 # tb_1.micron256 : Burst Type = Sequential # tb_1.micron256 : Write Burst Mode = Programmed Burst Length # ** Error: mt48lc16m16a2.v(1068): $setup( Addr:1476746 ps, posedge Clk:1477957 ps, 1500 ps ); # Time: 1477957 ps Iteration: 1 Instance: /tb_1/micron256 ---------------problem ------------------------ # ** Error: mt48lc16m16a2.v(1068): $setup( Addr:1496746 ps, posedge Clk:1497957 ps, 1500 ps ); # Time: 1497957 ps Iteration: 1 Instance: /tb_1/micron256 ---------------problem ------------------------ # tb_1.micron256 : at time 1518.0 ns AREF : Auto Refresh # ** Note: ### write ### # Time: 2 us Iteration: 0 Instance: /tb_1 # tb_1.micron256 : at time 2058.0 ns ACT : Bank = 0 Row = 0 # tb_1.micron256 : at time 2158.0 ns WRITE: Bank = 0 Row =0, Col =0, Data =3 # tb_1.micron256 : at time 2178.0 ns WRITE: Bank = 0 Row =0, Col =1, Data =4 # tb_1.micron256 : at time 2198.0 ns WRITE: Bank = 0 Row =0, Col =2, Data =5 # tb_1.micron256 : at time 2218.0 ns WRITE: Bank = 0 Row =0, Col =3, Data =6 # tb_1.micron256 : at time 2238.0 ns WRITE: Bank = 0 Row =0, Col =4, Data =7 # ** Warning: /X_LATCHE SETUP High VIOLATION ON I WITH RESPECT TO CLK; # Expected := 0.182 ns; Observed := 0.004 ns; At : 2251.933 ns # Time: 2251933 ps Iteration: 5 Instance: /tb_1/uut/uut/data_sys_in_4 ---------------problem ------------------------ # ** Warning: /X_LATCHE SETUP High VIOLATION ON I WITH RESPECT TO CLK; # Expected := 0.182 ns; Observed := 0.004 ns; At : 2251.933 ns # Time: 2251933 ps Iteration: 5 Instance: /tb_1/uut/uut/data_sys_in_6 ---------------problem ------------------------ # tb_1.micron256 : at time 2258.0 ns WRITE: Bank = 0 Row = 0, Col =5, Data =X ---------------problem ------------------------ # tb_1.micron256 : at time 2278.0 ns WRITE: Bank = 0 Row = 0, Col =6, Data =1 # ** Warning: /X_LATCHE SETUP High VIOLATION ON I WITH RESPECT TO CLK; # Expected := 0.182 ns; Observed := 0.004 ns; At : 2291.933 ns # Time: 2291933 ps Iteration: 5 Instance: /tb_1/uut/uut/data_sys_in_4 # ** Warning: /X_LATCHE SETUP High VIOLATION ON I WITH RESPECT TO CLK; # Expected := 0.182 ns; Observed := 0.004 ns; At : 2291.933 ns # Time: 2291933 ps Iteration: 5 Instance: /tb_1/uut/uut/data_sys_in_6 ---------------problem ------------------------ # tb_1.micron256 : at time 2298.0 ns WRITE: Bank = 0 Row =0, Col =7, Data =X ---------------problem ------------------------ # tb_1.micron256 : at time 2318.0 ns NOTE : Start Internal Auto Precharge for Bank 0 # tb_1.micron256 : at time 17338.0 ns AREF : Auto Refresh # ** Note: ### Read ### # Time: 23120 ns Iteration: 0 Instance: /tb_1 # tb_1.micron256 : at time 23178.0 ns ACT : Bank = 0 Row = 0 # tb_1.micron256 : at time 23303.0 ns READ : Bank = 0 Row = 0, Col = 0, Data = 3 # tb_1.micron256 : at time 23323.0 ns READ : Bank = 0 Row = 0, Col = 1, Data = 4 # tb_1.micron256 : at time 23343.0 ns READ : Bank = 0 Row = 0, Col = 2, Data = 5 # tb_1.micron256 : at time 23363.0 ns READ : Bank = 0 Row = 0, Col = 3, Data = 6 # tb_1.micron256 : at time 23383.0 ns READ : Bank = 0 Row = 0, Col = 4, Data = 7 ---------------problem ------------------------ # tb_1.micron256 : at time 23403.0 ns READ : Bank = 0 Row = 0, Col = 5, Data = X # tb_1.micron256 : at time 23423.0 ns READ : Bank = 0 Row = 0, Col = 6, Data = 1Article: 72982
AMBA works in a pipelined manner ... data from a master (HWDATA) should always be valid one cycle after the address is valid. Data should then be held until HREADY is sampled ... when the slave has signalled that it is complete. The delayed version of HMASTER is only used in the arbiter for the AMBA bus. Mike "mack" <mmkumar@gmail.com> wrote in message news:aba94305.0409082246.164990a@posting.google.com... > Hi, > I am designing an AMBA-AHB Master interface.As per the spec ,there > is a delayed version of the HMASTER bus is used to control the write > data mux.So my doubt is ,whether I should have one clk delayed hwdata > from haddr or both can be driven at the same time..It's pretty urgent > to make up the decision... > > ~~Kumar.Article: 72983
SHIFT: process (CLK, RST)
begin
if Rising_Edge(Clk) then
if RST = '1' then
-- D <= SIN;
D <= '0';
elsif EN = '1' then
D <= SIN;
end if;
end if;
end process;
1. How big is area penalty if resetting to SIN instead of '0'?
2. Will the shift reg be optimized out when RST is tied to '0'?
Article: 72984found an error there, excuse me.Article: 72985
Hi Andrew, >> under Assignments (menu) / Device (menu >> option) / Device & pin options (button) / Unused pins (tab) - I am >> concerned that "reserve all unused pins" is set to "as outputs that >> drive an unspecified signal" which seems to be the defualt. Does >> this setting get overridden? The setting is not overridden. The pins will remain unconnected in the hardware. MAX 7KS does not support Programmable Ground for IO pins. You could have been confused when you saw Quartus reporting those pins being set to GND*. GND* refers to the pin being either set to GND or NC. We will fix the report to reflect these pins as RESERVED > The default fitter behaviour (i.e. GND*) and the default setting > displayed by the GUI (output driving an unspecified signal) are > inconsistent when the global assignment does not exist. This refers to the confusion in the Quartus report. The GND* and the 'output driving an unspecific signal' are actually the same in MAX 7KS ie these unused pins remains unconnected in MAX 7KS. > > More info: > Clicking OK on the "unused pins" tab adds a set_global_assignment > -name reserve_all_unused_pins command to the "fitter assignments" > section of the .QSF file. This assignment was not there before. After > recompiling, the unused pins were listed as RESERVED. The only way > I've found to get the project options back to their original state is > to delete the set_global_assignment command using Notepad. Is there a > way to do it using the GUI? If an assignment is not seen in the .qsf, it means that the assignment is set to a default value in Quartus. Whenever an assignment is changed via the UI, the assignment is written to the .qsf and remain even if the assigment is reset back to its default. Once a assignment is changed it is always stored in the qsf, even when it is changed back to a default value. Hope this helps. - Subroto Datta Altera Corp.Article: 72986
mmkumar@gmail.com (mack) wrote in message news:<aba94305.0409082246.164990a@posting.google.com>... > Hi, > I am designing an AMBA-AHB Master interface.As per the spec ,there > is a delayed version of the HMASTER bus is used to control the write > data mux.So my doubt is ,whether I should have one clk delayed hwdata > from haddr or both can be driven at the same time..It's pretty urgent > to make up the decision... > > ~~Kumar. By definition, AHB has a separate address phase and data phase that is to be presented on the bus on two different clocks. Masters are responsible for driving those two different phases. In the case where there are Muxes controlling what is presented to the rest of the bus, you can get away with having a master drive both address and wdata on the same clock. In this case, the Muxing scheme that is used must insure that the two phases happen when they are supposed to. One way to do this is to generate a delayed version of HMASTER from the arbiter. The original HMASTER should be the selector for the address and control signals and the delayed version should control the mux for wdata. See AN 181 for an example of an AHB bus. http://www.altera.com/literature/an/an181.pdf Hope this helps. - Subroto Datta Altera Corp.Article: 72987
I have a few Altera ACEX 1K50 board for sale:
Each board contains:
ACEX EP1K50TC144-3
128 KB RAM
512 KB Flash (configuration and user data)
MAX EPM7032 for configuration from Flash
serial interface with MAX3232
watchdog with LED
Voltage regulators for 3V3 and 2V5
each board for EUR 75,- (about $ 90,-).
Original list price was EUR 145,-
Pictures and schematic of this board at:
http://www.jopdesign.com/board.jsp
Martin
----------------------------------------------
JOP - a Java Processor core for FPGAs:
http://www.jopdesign.com/
Article: 72988Martin Schoeberl wrote: > > I have a few Altera ACEX 1K50 board for sale: > > Each board contains: > ACEX EP1K50TC144-3 > 128 KB RAM > 512 KB Flash (configuration and user data) > MAX EPM7032 for configuration from Flash > serial interface with MAX3232 > watchdog with LED > Voltage regulators for 3V3 and 2V5 > > each board for EUR 75,- (about $ 90,-). > Original list price was EUR 145,- > > Pictures and schematic of this board at: > http://www.jopdesign.com/board.jsp I am curious as to why you chose the -3 version of the chips. In order to keep the cost to a minimum, Altera does not spec or test the PLL in the -3 parts, effectively removing it from operation. Have you tried to use the PLL in these devices? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 72989
> I have a few Altera ACEX 1K50 board for sale: and I have some chips I want to get rid of: 6 pcs. ACEX 1K50TC144-3 7 pcs. MAX EPM7032AETC44-10 about 130 pcs. HY62V8100BLLT1-70 (128 KB 70 ns SRAM) Martin ---------------------------------------------- JOP - a Java Processor core for FPGAs: http://www.jopdesign.com/Article: 72990
> > > > I have a few Altera ACEX 1K50 board for sale: > > > > Each board contains: > > ACEX EP1K50TC144-3 > > 128 KB RAM > > 512 KB Flash (configuration and user data) > > MAX EPM7032 for configuration from Flash > > serial interface with MAX3232 > > watchdog with LED > > Voltage regulators for 3V3 and 2V5 > > > > each board for EUR 75,- (about $ 90,-). > > Original list price was EUR 145,- > > > > Pictures and schematic of this board at: > > http://www.jopdesign.com/board.jsp > > I am curious as to why you chose the -3 version of the chips. In order > to keep the cost to a minimum, Altera does not spec or test the PLL in > the -3 parts, effectively removing it from operation. Have you tried to > use the PLL in these devices? > No, I have not. I used the -3 to produce a low-cost board some time ago.... When the ACEX was the low-cost chip -- at these days even more expensive than a Cyclone today. MartinArticle: 72991
Hello Austin, OK, so it is a mistake since the functionality of a dynamic SR and RAM is different even if they have the same I/O. tEd Austin Lesea <austin@xilinx.com> wrote in message news:<chpqt7$6o81@cliff.xsj.xilinx.com>... > Ted, > > The RAM16 is the same structure as the SRL16. It is the 16 bit LUT. > Can be used three ways: as a LUT, as a RAM, as a SR. > > You used it. I agree that the report is less than obvious. > > Austin > > Ted wrote: > > Hello All, > > > > I am using Synplicity Pro 7.5.1 to generate my edif file and then XST > > tools to do the mapping and PAR etc. > > > > For my design, I am using a RAM16X1S i.e. 16-1 RAMs from the Xilinx > > low-level libraries. ISE 6.2 has this nice feature that reports > > resource usage i.e. No. of MUXF5s used etc in the MAP report (Could be > > done elsewhere in earlier versions). However, when I instantiate > > RAM16X1S, an equivalent number of Dynamic length shift registers are > > always indicated as used resources. This doesn't seem to make sense > > because there seems no need for shift registers in my design. Also, > > looking at FPGA editor indicates no Dynamic shift registers used. I am > > assuming that SRL16s are used in this case with variable address > > inputs. (Funny thing is no distributed RAM reported to be used as > > SRL16s) > > > > Is it a bug or am I missing something? Please get back. > > > > tEdArticle: 72992
I'm trying to do a modular design, building a core, placing it, creating
an RPM then going on to a sibling or (finally) parent core, doing the
same, etc.
I've noticed something very odd - it seems the P&R can place, route and
statically-time a layout which the mapper can subsequently reject with
'Slice XXYY cannot do X,Y,Z at the same time' errors if it is fed the
layout as a floorplan.
My main objective has been to see if it's best to lay out on a
32-clb-high array (with 32-bit carry chains only taking 16 CLB's, for
example), or to do everything on a 16-CLB-high array and having much
more depth to the datapath.
I got to the stage in the 16-CLB high layout where the maximum frequency
dropped from 50 MHz down to 40 for a very thin wrapper around it. I
wanted to test the same level of abstraction with a 32-CLB-high layout.
So, I was creating the RPM layout, and running translate/map/par (T/M/P)
periodically to check things were still ok, and it got to the point
where the automatic layout was pretty much getting there - there were
still a few elements placed "outside" the rectangle when they could have
been inside, but I was reasonably happy, given that I just wanted to see
if it took the same hit as the 16-high CLB layout.
So, I did a 'copy from placement' into the editable area, and moved the
3 or 4 elements from their placed places to ones within my rectangle for
the design. I then tried to T/M/P it, and got errors from areas of the
design I hadn't touched.
I thought I must have clicked on something, so I did a 'copy from
placement' and 'save' immediately, then ran another T/M/P. I still got
errors - it seems that the output of the P&R doesn't work as input into
another round of T/M/P ...
I also noticed that the RPM where the problem was had been split down
the middle (surely the point of an RPM was that this didn't happen), and
I suspect the mapper is complaining that the RPM it's picking up from
the 'rpm_core' directory (in this case an add/sub module) doesn't match
the addsub module geometry that was placed in the design on the last pass:
ERROR:Pack:679 - Unable to obey design constraints (LOC=SLICE_X18Y20) which
require the combination of the following symbols into a single SLICE
component:
MUXCY symbol "as/Madd__n0002_inst_cy_0" (Output Signal =
as/Madd__n0002_inst_cy_0)
MUXCY symbol "as/Madd__n0002_inst_cy_1" (Output Signal =
as/Madd__n0002_inst_cy_1)
LUT symbol "as/Madd__n0002_inst_lut2_011" (Output Signal =
as/Madd__n0002_inst_lut2_0)
LUT symbol "as/Madd__n0002_inst_lut2_110" (Output Signal =
as/Madd__n0002_inst_lut2_1)
The following RPM logic must use the same site due to RLOC origin usage:
LUT symbol "z11" (Output Signal = CHOICE404)
There are more than two function generators. Please correct the design
constraints accordingly.
I have 'Use RLOC constraints' set in the 'Map properties' dialogue, and
'Allow Logic Optimisation Across Hierarchy' is unset in the same
dialogue box.
Am I barking up the right tree, here ? Is this a "well-known"
circumstance, or have I missed something obvious ?
Thanks for any help :-)
Simon.
Article: 72993roller wrote: > > "rickman" <spamgoeshere4@yahoo.com> escribió en el mensaje > news:4140967F.2EF867B@yahoo.com... > > roller wrote: > > > > > > and as for accessing an internal signal, i know that you can "up" > hierarchy > > > by specifiying it's full "pathname", but i dont know if it works "down" > > > hierarchy, you can always try. > > > > I was trying to do that, but I can't figure out the format for > > specifying the heiarchy. I looked in the LRM and could not find any > > references to that. What is used as separators in a "path" name? > > > > it's the dot like in Ada (and Java, or like "use work.package.all") though > it's been a long time since i read about it (plus i havent ever used it) > maybe you can check the visibility rules or tutorials explaining that, sorry > i couldnt help you more > > http://tech-www.informatik.uni-hamburg.de/vhdl/doc/faq/FAQ1.html#visibility Thanks for the info. Seems the way I am trying to access the shared variable is called a "selected name". But that will not work outside of the scope of the variable. So I am back to trying to find a way to make life easy in the simulation. At this point, the external program to generate a deferred constant package seems like it has the best chance of working. It also may do the job for synthesis as well as simulation. But my program memory is not constant, it is read/write, so I may have to do an assignment between them and hope the synthesis tool can figure that out rather than to make two arrays and generate logic to copy them. :) Thanks again. I will try to remember the 'dot' thing in the future. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 72994
Mike Treseler wrote:
>
> Alan wrote:
>
> > subtype wordT is std_logic_vector(15 downto 0); -- e.g.
> > type RomT is array (0 to 1023) of wordT;
> > constant MyRom : arrayT := FNFillRom("file name");
> >
> > The advantage of this is that the ROM gets filled during elaboration,
> > and so is instantly available at time 0. The disadvantage is there's
> > no direct link to synthesis - unless I suppose you write the function
> > to read in the file in the format that your target technology
> > supports.
>
> Another possible solution is to use perl or bash
> to convert the external hex file to a deferred
> constant package body something like:
>
> constant MyRom : arrayT :=
> (
> -- begin data
> x"0000",
> x"0001",
> x"0002",
> x"0004",
> x"0008",
> x"0010",
> x"0020",
> x"0040"
> -- ...
> -- end data
> );
>
> This would give you synthsizable code,
> but require running the script and
> a "vcom myPackageBody.vhd" for
> each iteration.
This just might do the job. My only concern has to do with the fact
that my program memory is actually read/write, so the ram will have to
be initialized to this constant data. I don't know if the synthesis
tool can understand that this does not require two memories. :)
--
Rick "rickman" Collins
rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.
Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
Article: 72995Gaaah. For CLB, read 'slice'. It's late :-) Simon.Article: 72996
Austin, Thanks for the insight on the duty cycle. We will check this. One more thing. What can we expect from the integrity of a DCM in a system where it is common to switch clock sources or clock frequencies? We have found that the DCM does not lose lock or indicate "clkin_stopped" during these sequences. Are we supposed to reset the DCM after such an occurrence? If so, we are trying to figure out how we will know to do this since the DCM doesn't unlock or indicate that the input clock has stopped. The DCM spec states (in the "Input Clock Changes" section) that the DCM can tolerate pauses or phase shifts in the clock, but later on in the spec, states "once locked to a frequency, cannot tolerate large variations of the input frequency." Exactly what is meant by "cannot tolerate"? Does this mean that it is possible for the DCM to offset its "phase shift" on the output clock from the optimal setting? Thanks! John Austin Lesea <austin@xilinx.com> wrote in message news:<chprct$73l1@cliff.xsj.xilinx.com>... > John, > > There have been cases where the frequency, jitter, and duty cycle are > just on the edge of where the DCM phase detector will operate reliably. > > Check the input duty cycle. It will need to be as close to 50% as you > can make it. The spec is 45 to 55%, but at the higher frequencies, it > may have to be even closer to 50% when you take clock jitter into > account (as if it is 45%, and it has jitter, then it is sometimes less > than 45%!). > > Hope this helps. > > If you can vary the input clock duty cycle, you should be able to make > it always work, never work, and be in between like it is now. That will > show you where it needs to be. > > Duty cycle management is a tough thing as it is affected by signal > integrity, and at 311 MHz, signals get distorted very easily. > > Even observing the signal can be tough, as it doesn't look like it does > on the die at the pins (just simulate it to see that). > > In the past, I have seen cases where the 100 ohm LVDS receive > termination is removed, and the problem goes away (due to the location > of the 100 ohm resistor, and the stubs causing reflections distorting > the signal). The termination for a clock signal input isn't really > required (would be for a data signal to prevent ISI). > > Subsequent versions of the DCM (S3 and V4) have even better phase > detectors which are more tolerant of the duty cycle. Always room for > improvements. > > Austin > > John Cappello wrote: > > > Hi, > > > > We are seeing evidence that a DCM is intermittently selecting the > > wrong tap position after it completes its lock sequence after a DCM > > reset pulse. I'd like to know if anyone has experienced this effect, > > and if they were able to resolve this problem. > > > > In a 2v6000, I am using a variable phase shift DCM which is driven by > > a 622 MHz clock (divide-by-2 mode). The DCM generates 311 MHz clocks > > on its clk0/clk180 output pins. This interface uses IOB DDR regs for a > > 622 Mhz/16-bit LVDS transmission solution. > > > > The DCM initial value is set to 0. After a DCM reset, the DCM is phase > > shifted to its predetermined optimal "error-free" setting. However, > > intermittently, the interface experiences a small amount of bit > > errors. > > > > To eliminate the errors, the DCM is further phase shifted in one > > direction until it actually achieves error-free operation. The > > subsequent error-free window of operation in this mode matches very > > closely to the original calibration error-free window. > > > > It is as if the DCM locking sequence is corrupted somehow, resulting > > in a mis-aligned tap position. We don't have conclusive evidence > > because we can't see inside the DCM to see its tap position. We have > > found that we can eliminate this error condition by applying another > > one or two reset pulses to the DCM. > > > > I realize that voltage fluctuations and switching noise could be > > causing this effect. Nonetheless, I'd like to hear from real world > > experiences. > > > > Thank you. > > JohnArticle: 72997
Philip,
If you get a chance, play with the DSP blocks. The speeds in there are much
more impressive than the speeds of the fabric.
Philip Freidin wrote:
> Well,
> Xilinx shipped me my Foundation 6.3i software update,
> and since it has the initial support for Virtex 4,
> I installed it and did a design.
>
> Here it is:
>
> ====
>
> module top(in_bus,out_bus);
> input [15:0] in_bus;
> output [15:0] out_bus;
>
> assign out_bus = {in_bus[14:0],in_bus[15]};
>
> endmodule
>
> ====
>
> Par Report (trimmed):
>
> Release 6.3i Par G.35
> Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.
> Thu Sep 02 19:16:08 2004
> Loading device database for application Par from file "top_map.ncd".
> "top" is an NCD, version 2.38, device xc4vfx12, package sf363, speed -11
> Loading device for application Par from file '4vfx12.nph' in environment
> Device speed data version: PREVIEW 1.46 2004-07-09.
> Device utilization summary:
> Number of External IOBs 32 out of 240 13%
> Number of LOCed External IOBs 0 out of 32 0%
>
> Total REAL time to PAR completion: 19 secs
> Total CPU time to PAR completion: 18 secs
>
> Peak Memory Usage: 105 MB
>
> Placement: Completed - No errors found.
> Routing: Completed - No errors found.
>
> ====
>
> Some of the manuals are single page PDFs, that point you to
> the web site to get the real thing.
>
> Although you all do HDL designs only, you might want to get
> the Schematic Designers library guide as well as the HDL guide,
> as the HDL one is 290 pages, and the schematic one is 700 pages.
> Most of the extra stuff is stuff you don't need, such as 4 bit
> counter macros, but there are also some things that are pretty
> interesting that seem to have been left out of the HDL version.
> Probably fixed in the next version.
>
> FPGA editor shows lots of interesting new stuff. Still waiting
> for a data sheet, as the FPGA editor shows you details of the
> forest from the perspective of having your nose pressed against
> a huge tree :-) and the library guides is mostly very detailed
> for simple stuff like logic and FF primitives, and not nearly
> as much info as you might want for the complex stuff.
>
> If this is the sort of thing you like, then you will probably
> like this sort of thing.
>
> Philip
>
> Philip Freidin
> Fliptronics
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 72998"Simon" <news@gornall.net> wrote in message news:E240d.141$Mm5.19@newsfe5-gui.ntli.net... > I'm trying to do a modular design, building a core, placing it, creating > an RPM then going on to a sibling or (finally) parent core, doing the > same, etc. > > I've noticed something very odd - it seems the P&R can place, route and > statically-time a layout which the mapper can subsequently reject with > 'Slice XXYY cannot do X,Y,Z at the same time' errors if it is fed the > layout as a floorplan. > > My main objective has been to see if it's best to lay out on a > 32-clb-high array (with 32-bit carry chains only taking 16 CLB's, for > example), or to do everything on a 16-CLB-high array and having much > more depth to the datapath. > Splitting up the carry chains is usually a bad idea. It takes quite a while to get the signal off the carry chain, and then you have to route it back to the bottom of the die. I'm sure you're much better off leaving the carry chain in a single column, and if not, you'd best pipeline the carry. RPMs are getting a lot better, but there are still some problems. I find it's easier to write a Perl script to create a UCF for you using absolute LOCs. It's kind of a pain, but the tools have no problems with absolute LOCs. You can write a Perl function that will take a root coordinate and creat the LOCs for you. Of course you have to rerun this for different parts or die sizes. The area constraints do work very well. And the placer sometimes (but not always) yields better results than hand-placement. -KevinArticle: 72999
On 9 Sep 2004 09:01:26 -0700, ericjohnholland@hotmail.com (Guitarman) wrote: >I am interested in adding a "busy" signal to the Input/Ouptut port of >the Picoblaze. This will allow me to add a Wishbone wrapper to the >picoblaze and allow me to used some free wishbone cores from >Opencores.org. > >Since the picoblaze is written using xilinx primatives the VHDL code >is a little hard to follow. On to my question: > >Has anyone put together a block diagram of the internal signal >connections of the picoblaze? > >The Xilinx documantation I've seen doesn't "pictorially" show the >internal signal connections. > >I'm willing to look through the code and put together a diagram, but >if someone else has done it and could save me some time... great! http://armoid.com/pacoblaze/ Might be a better place to start, assuming you can read Verilog. Regards, Allan
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