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I thought I would turn this over to Xilinx and open a case. But it seems their web support makes you wait 24 hours. Did I do something wrong? I was hoping to get this into the queue so it might get some attention tomorrow before the weekend. But now it looks like I'll have to wait until Monday. rickman wrote: > > I have some code that compiles fine in Modelsim and under Quartus, but I > get an odd error under XST. > > ERROR:HDLParsers:3324 - > //walmart800/allnetwork/arius/pc104c67/up/dinero/dinero/../OpcodeDefs.vhd > Line 128. IN mode Formal opcode of LIT with no default value must be > associated with an actual value. > > The answer record on this error talks about passing generics into an > instance which is nothing like what I am doing. Here is a section of > the code in question. > > type INSTDSPLY is (LIT, N0P, > CAL, RTI, JMP, JUMZ, JUMC, JUMO, > FTCH, STOR, FCHP, STRP, FCHB, STRB, FHPB, STPB, > DOOP, SWP, DRP, OVR, TORR, RFRM, RFTC, > RADT, RAD, RSB, RCM, RDRP, > ADNC, ADC, SBNC, SBC, CPNC, CPC, LAND, LOR, LXOR, > SHFL, SHFC, ZFLG, BFL, ERR); > > function IRSLV_to_Inst (Opcode : IRSLV; LFLAG, BFLAG : STD_LOGIC) > return INSTDSPLY is > variable OpcodeInt : INSTVAL; > begin > if (Opcode(IRWdth-1) = '0') then > >>>>> return LIT; <<<<<< line number points here > elsif (Opcode = "10000000") then > return N0P; > elsif (not (Opcode(IRWdth-1) = '1' and > CountOnes(Opcode(IRWdth-2 downto 0)) = 3)) then > return ERR; > ... > endif; > end IRSLV_to_Inst; > > This function is being defined in a library package. It just looks up a > value of an SLV and returns an enumerated type for purpose of debug > display. Anyone have a clue? Is this an XST bug? > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAX -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 75201
Frank Wang <ftwang@nospam.berkeley.edu> wrote in message news:<clpmhi$2sf1$1@geode.berkeley.edu>... > I want to be able to read files off the compact flash card through the > xilinx system ace chip which is connected to a xilinx virtex 2e FPGA. > The compact flash card is formated as FAT12. Has anyone done this > before, or at least could point me in the right direction in > implementing this in verilog? > > Thanks, > > frank Which os/sw environment or are you trying this in pure verilog? If linux-ppc, it is very easy. Xilinx did it for you already. Search xilinx's website for info. -TonyArticle: 75202
T Lee wrote: > Frank Wang <ftwang@nospam.berkeley.edu> wrote in message news:<clpmhi$2sf1$1@geode.berkeley.edu>... > >>I want to be able to read files off the compact flash card through the >>xilinx system ace chip which is connected to a xilinx virtex 2e FPGA. >>The compact flash card is formated as FAT12. Has anyone done this >>before, or at least could point me in the right direction in >>implementing this in verilog? > > Which os/sw environment or are you trying this in pure verilog? > > If linux-ppc, it is very easy. Xilinx did it for you already. Similarly, Microblaze uClinux also supports the sysace driver. You can mount any filesystem you like on the CF card, FAT included. Cheers, JohnArticle: 75203
hi all, set dw_prefer_mc_inside true will enable module compiler for datapth in DC-TCL. But do u know how to enable in dcsh. regards whizkidArticle: 75204
Hello Could anyone tell me the name and/or where I can find more information about this FPGA Development Board? http://cgi.ebay.co.uk/ws/eBayISAPI.dll?ViewItem&rd=1&item=3845720583&ssPageName=STRK:MEWN:IT Thanks Rune ChristensenArticle: 75205
I am interested in safety for embedded applications. So I read this articels dealing with "ASICs Vs. FPGA in Safety Critical Apps." posted around 1996 with great interest. People listed a lot of advantages of FPGAs, however the major problem (related to safety) left was that the FPGA has to be reprogrammed at each power up. My question: isn't an CPLD a good solution for small safety critical applications? Falk ---------------------------------------------------------- Chair of Computer Science XI RWTH Aachen University GermanyArticle: 75206
Confused about async./sync. resets? You should read this: http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_Resets_rev1_1.pdf Mostly ASIC related but most of it apply equally to FPGAs as well. Regards, tore "ALuPin" <ALuPin@web.de> wrote in message news:b8a9a7b0.0410260315.7d1cd401@posting.google.com... > Hi @ all, > > it is one possibility to > synchronize an asynchronous reset so that all flip flops in > the FPGA are resetted within the same clock period. > > Using this synchronized reset > can I still write the process like that: > > > process(Sync_reset, Clk) > begin > if Sync_reset='1' then > ... > elsif rising_edge(Clk) then > ... > end if; > > end process; > > or does it make more sense to write it like that: > > process(Sync_reset, CLk) > begin > if rising_edge(Clk) then > if Sync_reset='1' then > ... > else > ... > end if; > end if; > end process; > > I would be very thankful for your opinion. > > Rgds > AndréArticle: 75207
>Could anyone tell me the name and/or where I can find more information about >this FPGA Development Board? >http://cgi.ebay.co.uk/ws/eBayISAPI.dll?ViewItem&rd=1&item=3845720583&ssPageName=STRK:MEWN:IT Text says XC2064-50 so it's probably a very very old board from Xilinx. You will have troubles finding software that supports it and/or people who know anything about that software. It might be interesting if you collect old boards. Get something more recent if you want to learn about FPGAs. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 75208
"Rune Christensen" <rune.christensen@adslhome.dk> wrote in message news:4181f07b$0$291$edfadb0f@dread12.news.tele.dk... > Hello > > Could anyone tell me the name and/or where I can find more information about > this FPGA Development Board? > http://cgi.ebay.co.uk/ws/eBayISAPI.dll?ViewItem&rd=1&item=3845720583&ssPageName=STRK:MEWN:IT > > Thanks > Rune Christensen > DO NOT BUY anything that has xilinx chips older than spartan2! except you want it for personal museum. Antti PS danfubocca is a very nice ebay seller, he often has used FPGA, so I once obtained a XCV2000E for $49 from him and made wire wrap FPGA development from it :)Article: 75209
Could you post a link to the original article? There are lots more concerns other than the reprogramming. One such thing is the effect of Single Event Upsets. For example, configuration bits of the FPGA/CPLD can be flipped by SEUs (even at sea-level this is more important than MTBF) making the logic you designed behave incorrectly. Of course mitigation techniques exist, such as Triple Mode Redundancy, (and Device read-back and reconfiguration for some devices) Having said that CPLDs are much smaller devices, often at higher internal voltages, hence don't have the same problems with MTTE. If your system is small enough, and can be made fully redundant to cover MTBF failures, CPLD would be my advice. You want to check out the IEC-61508 Standard, and the Xilinx Military applications page. (or http://lhc-mpwg-reliability.web.cern.ch/lhc%2Dmpwg%2Dreliability/) HTH Ben "Falk Salewski" <salewski@informatik.rwth-aachen.de> wrote in message news:2uee97F28fi9jU1@uni-berlin.de... > I am interested in safety for embedded applications. So I read this articels > dealing with "ASICs Vs. FPGA in Safety Critical Apps." posted around 1996 > with great interest. > > People listed a lot of advantages of FPGAs, however the major problem > (related to safety) left was that the FPGA has to be reprogrammed at each > power up. > > My question: isn't an CPLD a good solution for small safety critical > applications? > > Falk > ---------------------------------------------------------- > Chair of Computer Science XI > RWTH Aachen University > Germany > >Article: 75210
Thanks for the reply! I got the original article from http://www.fpga-faq.com/archives/04700.html#4721 You can find there the problem you mentioned, too. I was just wondering if a CPLD would meet safety requirements better than a FPGA. Falk "Benjamin Todd" <benjamin.toddnospam@cern.ch> schrieb im Newsbeitrag news:clt313$3or$1@sunnews.cern.ch... > Could you post a link to the original article? > > There are lots more concerns other than the reprogramming. One such thing > is the effect of Single Event Upsets. > For example, configuration bits of the FPGA/CPLD can be flipped by SEUs > (even at sea-level this is more important than MTBF) making the logic you > designed behave incorrectly. > > Of course mitigation techniques exist, such as Triple Mode Redundancy, > (and > Device read-back and reconfiguration for some devices) > > Having said that CPLDs are much smaller devices, often at higher internal > voltages, hence don't have the same problems with MTTE. If your system is > small enough, and can be made fully redundant to cover MTBF failures, CPLD > would be my advice. > > You want to check out the IEC-61508 Standard, and the Xilinx Military > applications page. > (or http://lhc-mpwg-reliability.web.cern.ch/lhc%2Dmpwg%2Dreliability/) > HTH > Ben > > > > > "Falk Salewski" <salewski@informatik.rwth-aachen.de> wrote in message > news:2uee97F28fi9jU1@uni-berlin.de... >> I am interested in safety for embedded applications. So I read this > articels >> dealing with "ASICs Vs. FPGA in Safety Critical Apps." posted around 1996 >> with great interest. >> >> People listed a lot of advantages of FPGAs, however the major problem >> (related to safety) left was that the FPGA has to be reprogrammed at each >> power up. >> >> My question: isn't an CPLD a good solution for small safety critical >> applications? >> >> Falk >> ---------------------------------------------------------- >> Chair of Computer Science XI >> RWTH Aachen University >> Germany >> >> > >Article: 75211
Try the following. dw_prefer_mc_inside = true Learner.Article: 75212
I have encountered a problem with Quartus 4.0 : Component behaves different in simulations when placed in different projects. The behaviour change is quite severe, for example, the LPM_FIFO megafunction supposed to deactivate the "empty" signal when the data becomes valid on its output ports (Show-Ahead mode) and does so in one simulation. However exactly the same megafunction in a different project toggles "empty" signal long before the output becomes valid. I had similar problem with a flip-flop when it would not keep the signal it captured (no resets or anything) but when another flip-flop was connected in parallel to it in the design, it simulated fine. I am at a point where I need to finalize my design, yet this prevents me from moving forward. Does anyone know whats going on ? Thnx.Article: 75213
vadim wrote:
> The behaviour change is quite severe, for example, the LPM_FIFO
> megafunction supposed to deactivate the "empty" signal when the data
> becomes valid on its output ports (Show-Ahead mode) and does so in one
> simulation. However exactly the same megafunction in a different
> project toggles "empty" signal long before the output becomes valid.
You can see source code for lpm_fifo at:
http://www.edif.org/lpmweb/more/vhdl.htm
Talk to altera or write your own fifo.
-- Mike Treseler
Article: 75214Xilinx told me that EDK 6.3 started shipping Oct 18, 2004. I asked if my EDK maintenance period had expired and they sent me a quote for a new copy (full retail price), and said they would ship me the new version when I paid them the quoted price. "E.S." <emu@ecubics.com> wrote in message news:<vIbgd.26$SJ2.10@fe61.usenetserver.com>... > Hi all, > is the edk 6.3 shipping in the meantime/already ? > Still waiting for mine, but just saw the first patch for it already ... > > cheers & thanksArticle: 75215
Let's keep things in pespective. Yes, "SRAM-based" FPGAs can be upset by random SEUs. But how likely is this? We at Xilinx have done extensive real-time tests with thousands of large devices (XC2V6000) over more than a year, and here is a snapshot of the result: A device of Virtex-II 1000 complexity ( "1 million FPGA gates") is likely to pick up a functional error due to SEU roughly once per thousand years of operation. The much smaller XC2V40 is about twice the complexity of the largest CPLD, and it would encounter a functional error once per 25000 years. That's a pretty good MTBF. Better than the FIT rate of many other, even passive, coponents. Peter Alfke, Xilinx Applications ===================== > From: "Benjamin Todd" <benjamin.toddnospam@cern.ch> > Organization: CERN - European Laboratory for Particle Physics > Newsgroups: comp.arch.fpga > Date: Fri, 29 Oct 2004 11:37:38 +0200 > Subject: Re: CPLDs and Safety? Re: ASICs Vs. FPGA in Safety Critical Apps. > > Could you post a link to the original article? > > There are lots more concerns other than the reprogramming. One such thing > is the effect of Single Event Upsets. > For example, configuration bits of the FPGA/CPLD can be flipped by SEUs > (even at sea-level this is more important than MTBF) making the logic you > designed behave incorrectly. > > Of course mitigation techniques exist, such as Triple Mode Redundancy, (and > Device read-back and reconfiguration for some devices) > > Having said that CPLDs are much smaller devices, often at higher internal > voltages, hence don't have the same problems with MTTE. If your system is > small enough, and can be made fully redundant to cover MTBF failures, CPLD > would be my advice. > > You want to check out the IEC-61508 Standard, and the Xilinx Military > applications page. > (or http://lhc-mpwg-reliability.web.cern.ch/lhc%2Dmpwg%2Dreliability/) > HTH > Ben > > > > > "Falk Salewski" <salewski@informatik.rwth-aachen.de> wrote in message > news:2uee97F28fi9jU1@uni-berlin.de... >> I am interested in safety for embedded applications. So I read this > articels >> dealing with "ASICs Vs. FPGA in Safety Critical Apps." posted around 1996 >> with great interest. >> >> People listed a lot of advantages of FPGAs, however the major problem >> (related to safety) left was that the FPGA has to be reprogrammed at each >> power up. >> >> My question: isn't an CPLD a good solution for small safety critical >> applications? >> >> Falk >> ---------------------------------------------------------- >> Chair of Computer Science XI >> RWTH Aachen University >> Germany >> >> > >Article: 75216
Apparently, some CPLD's get reprogrammed after each power cycle. There is at least one where the programmed bits are stored in non-volatile flash, but program RAM LUT's(?) upon powerup that is transparent to the user. I would suspect that the CPLD RAM values are susceptable just like RAM based FPGA's, but that is only a guess on my part. "Falk Salewski" <salewski@informatik.rwth-aachen.de> wrote in message news:<2uee97F28fi9jU1@uni-berlin.de>... > I am interested in safety for embedded applications. So I read this articels > dealing with "ASICs Vs. FPGA in Safety Critical Apps." posted around 1996 > with great interest. > > People listed a lot of advantages of FPGAs, however the major problem > (related to safety) left was that the FPGA has to be reprogrammed at each > power up. > > My question: isn't an CPLD a good solution for small safety critical > applications? > > Falk > ---------------------------------------------------------- > Chair of Computer Science XI > RWTH Aachen University > GermanyArticle: 75217
Hi Rick, Three things come to mind: 1) The error message seems to be objecting the formal input "opcode", which is declared to be of type "IRSLV". Does changing the type to "standard_logic_vector" help at all? Maybe XST gets confused over type declarations. 2) Perhaps the problem is in the function usage rather than the function itself. Can you show a code snippet where the function is called? 3) I've had problems where stuff in a packaged library would not work unless the library was first 'compiled' by running 'check syntax' on the library package alone, separately from the design, in the ISE environment. Maybe this would help? HTH, John (The Other John Smith) rickman <spamgoeshere4@yahoo.com> wrote in message > > ERROR:HDLParsers:3324 - > > //walmart800/allnetwork/arius/pc104c67/up/dinero/dinero/../OpcodeDefs.vhd > > Line 128. IN mode Formal opcode of LIT with no default value must be > > associated with an actual value. > > > > The answer record on this error talks about passing generics into an > > instance which is nothing like what I am doing. Here is a section of > > the code in question. > > > > type INSTDSPLY is (LIT, N0P, > > CAL, RTI, JMP, JUMZ, JUMC, JUMO, > > FTCH, STOR, FCHP, STRP, FCHB, STRB, FHPB, STPB, > > DOOP, SWP, DRP, OVR, TORR, RFRM, RFTC, > > RADT, RAD, RSB, RCM, RDRP, > > ADNC, ADC, SBNC, SBC, CPNC, CPC, LAND, LOR, LXOR, > > SHFL, SHFC, ZFLG, BFL, ERR); > > > > function IRSLV_to_Inst (Opcode : IRSLV; LFLAG, BFLAG : STD_LOGIC) > > return INSTDSPLY is > > variable OpcodeInt : INSTVAL; > > begin > > if (Opcode(IRWdth-1) = '0') then > > >>>>> return LIT; <<<<<< line number points here > > elsif (Opcode = "10000000") then > > return N0P; > > elsif (not (Opcode(IRWdth-1) = '1' and > > CountOnes(Opcode(IRWdth-2 downto 0)) = 3)) then > > return ERR; > > ... > > endif; > > end IRSLV_to_Inst; > > > > This function is being defined in a library package. It just looks up a > > value of an SLV and returns an enumerated type for purpose of debug > > display. Anyone have a clue? Is this an XST bug? > > > > -- > > > > Rick "rickman" Collins > > > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > > removed. > > > > Arius - A Signal Processing Solutions Company > > Specializing in DSP and FPGA design URL http://www.arius.com > > 4 King Ave 301-682-7772 Voice > > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 75218
John wrote: > > Hi Rick, > Three things come to mind: > > 1) The error message seems to be objecting the formal input "opcode", > which is declared to be of type "IRSLV". Does changing the type to > "standard_logic_vector" help at all? Maybe XST gets confused over type > declarations. I haven't tried that. I check. > 2) Perhaps the problem is in the function usage rather than the > function itself. Can you show a code snippet where the function is > called? This error happens when compiling the definition, not the useage. It craps out on this file and never gets to the file where it is called. > 3) I've had problems where stuff in a packaged library would not work > unless the library was first 'compiled' by running 'check syntax' on > the library package alone, separately from the design, in the ISE > environment. Maybe this would help? Yes, this is being compiled and not just syntax checked. I am pretty convinced that this is an XST bug. The fact that it gives the name LIT as the function name says something is pretty messed up. But I am still open to the short between the headphones theory. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 75219
When I use xilinx webpack (the latest version, version 6?) to compile my
VHDL code, I get this warning message: "WARNING xst737: found 1-bit latch
for signal ABC"
The code is like this,
process (HOST_WR, HOST_DATA)
if HOST_WR = '0' then
ABC <= 'HOST_DATA(0)';
end if;
end process;
I know it is a latch, and it is designed to be a latch. But is there a way
to explicitly state that it is a latch, so that the warning message can be
eliminated? Thank you for your answers.
VAX, 9000
Article: 75220rickman wrote: > > I thought I would turn this over to Xilinx and open a case. But it > seems their web support makes you wait 24 hours. Did I do something > wrong? I was hoping to get this into the queue so it might get some > attention tomorrow before the weekend. But now it looks like I'll have > to wait until Monday. I just wanted to clarify this post. I guess the first time you use the webcase page, you have to register, even if you are already registered at the xilinx support site. I assume this to verify that you are entitled to support. They take up to 24 hours to "approve" your registration. Only when this is complete can you enter a case. That is what I am waiting for. I just wanted to make this clear because a Xilinx person saw my post and had the mistaken impression that I had opened a case and was waiting for someone to contact me. He took the initiative to call me and to open a case for me. Thanks Ryan. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 75221
Stick xilinx latch coding style into Google. Click on the second hit. Syms. "vax, 9000" <vax9000@gmail.com> wrote in message news:clu6bq$lai$1@charm.magnus.acs.ohio-state.edu... > When I use xilinx webpack (the latest version, version 6?) to compile my > VHDL code, I get this warning message: "WARNING xst737: found 1-bit latch > for signal ABC" > The code is like this, > > process (HOST_WR, HOST_DATA) > if HOST_WR = '0' then > ABC <= 'HOST_DATA(0)'; > end if; > end process; > > I know it is a latch, and it is designed to be a latch. But is there a way > to explicitly state that it is a latch, so that the warning message can be > eliminated? Thank you for your answers. > > VAX, 9000Article: 75222
> I don't have an option of using unix (or unix-like shell in > windows)... You can always find some sort of Perl or Python for Windows to convert wallclock time to a number and then launch vsim from it. Best regards, BenArticle: 75223
Syms suggests- > >Stick xilinx latch coding style into Google. Click on the second hit. >Syms. > >"vax, 9000" <vax9000@gmail.com> wrote in message >news:clu6bq$lai$1@charm.magnus.acs.ohio-state.edu... >> When I use xilinx webpack (the latest version, version 6?) to compile my >> VHDL code, I get this warning message: "WARNING xst737: found 1-bit latch >> for signal ABC" >> The code is like this, >> >> process (HOST_WR, HOST_DATA) >> if HOST_WR = '0' then >> ABC <= 'HOST_DATA(0)'; >> end if; >> end process; >> >> I know it is a latch, and it is designed to be a latch. But is there a way >> to explicitly state that it is a latch, so that the warning message can be >> eliminated? Thank you for your answers. >> >> VAX, 9000 > thanks for the link to a good reference and you didn't say - RTFM ! the short answer is- complete the if statement - add - else ABC <= ABC; --prior to the end if; this provides explicit instructions to the synthesis engine, and it won't have to warn you of an inferred latch Mike Thomas LSC FAEArticle: 75224
If current peaks are smaller.. than the PSU is smaller => smaller can be more efficient. Also if current doesn't die down instantaneously but decays due to L & C, then in theory, circuits which idle between clocks would draw more power than a circuit which gathers all the idles at the end and just sits there as there is no capacitors to charge and discharge on every clock. (Just a theory!) All the rest valid points.. all made it the thesis too... And you did hit the nail on the head with traffic cops.. That's the big chunk of true async HDL. Sync runs at the speed of the slowest device async goes as fast as possible. so traffic lights are on every corner. The other big chunk is the variable delay used set minimum times for signal transportation or for work to happen. That's why FPGA's don't work.. no async delays. you would be forced to use constant delays and that breaks the async rules. Also I believe that a flip flop that is clocked but does nothing, still consumes more power than a flip-flop doing nothing. (i.e. no clock) CMOS is all about changes not static conditions. The 'average' for async systems doing the same task as sync systems is longer static periods. then there aren't any clock buffers in an async system, no need, in large systems, they can form a significant chunk of power. Your right about different architectures too... As a sync designer I synchronise everything. its the mind set... but to design async you need to think async... and its not easy.. all the rules are thrown out for a new set. Async is all about just in time delivery. And, of course, there are some async designs that draw more power than sync designs... but as time goes by they will get better. and you have a silicon overhead for all the extra 'timing' circuits 20% maybe .. and in reality, today, silicon is more expensive than power. for the manufacturer that is. Simon "rickman" <spamgoeshere4@yahoo.com> wrote in message news:4181274C.875E4850@yahoo.com... > Simon Peacock wrote: > > > > I saw the same posting too.. > > > > Self timed IC's tend to reduce power in several ways... for starts the peak > > is lower.. as nothing switches at the same time :-) > > Is the smily indicating a joke? That doesn't save power, right? > > > > second.. only the circuit active is running.. the next step is still idle > > the last step is now idle. The tend is to then be either idle or running.. > > not 'clocked and waiting'. > > If you have separately clocked circuits, that is like pipelining. Why > wouldn't you run them in parallel? If you take out the pipeline > registers, you will not use any more power and you will make the circuit > smaller. > > > > Third.. the ripple effect... as each stage runs as fast as it wants/needs, > > things which would gobble time doing nothing, now take next to no time to > > do, so simple instructions process faster, and overall, the 'speed' can > > decrease.. or at least .. spend more time doing nothing as speed assumes a > > clock ;-) > > In a sync design the circuits are balanced since they all run together. > Of course this is never perfect. But this way things can run in > parallel and stay in step. In an async circuit you would have to have > traffic cops directing results based on availability at a very low > level. That would add a lot of logic. > > > > That's suppose to be good for a 30 % power drop. That's according to the > > thesis I read a few months back. The problem is, of course, the more you get > > the chip to do.. the less the power saving. Look at a hyper threading P4 > > for example.. all that silicon not doing anything until you hyper thread.. > > and then consume another 10 watts > > > > The classic example of this is a MOVE to register instruction in a > > processor... > > If a standard FPGA or processor, you would setup the address, read, write, > > allocate a bus, and on the next clock edge, execute a simultaneous read and > > write, now the whole chip sees this read and write.. and everything else > > decides its not for them. > > In an Async system, the MOVE sets up a async path between the register and > > the memory... everything else is still idle or doing something else (thru > > other async paths) and the memory and register do the data transfer between > > themselves nothing else knows / cares > > Sounds simple .. but they've been working on this for 10 years. I think > > because when things go wrong.. the system turns to custard, simulation > > requires specialist tools... you can't prototype in a FPGA either. > > But logic that is not being used in a sync design may be clocked, but it > uses far less power than if it were actually working. I still don't see > the power savings. To some extent, this is comparing apples to oranges > since the two methods will use very different design techniques. I > think if you were designing a CPU from scratch you would not even have > the same instruction sets for the two designs. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAX
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