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just saw this http://www.eet.com/semi/news/showArticle.jhtml;jsessionid=TDU3YDUKFOWG4QSNDBCSKHSCJUMEKJVN?articleID=54200060 0.18u/40V/ OTP and MTP IP "without additional process steps" Imagine the CPLD you could ship with that process ?. Coolrunner or Lattice like devices without the voltage ceiling pains... -jgArticle: 76051
Depends on the resistors. 11pF i/p capacitance, 100 Ohms resistor, => RC = 1.1nS. Should be OK. Crap, but OK. Syms. "Jon Elson" <elson@pico-systems.com> wrote in message news:ca94c$41a22254$4503e66a$14885@msgid.meganewsservers.com... > Maciejos wrote: > > There is quartz generator 80MHz connected to GCLK input. It is driven by 5V > > but I used the voltage divider (2 resistors) to connect it to xc3s50. > Huh? You take an 80 MHz clock through a 2:1 resistive voltage divider? > Have you looked at the signal on the Spartan GCLK pin? I would expect > massive attenuation of the high frequency component due to the input > pin's parasitic capacitance. If you really have to do this, you will > almost certainly need a compensating capacitor on the series resistor > to get the signal rise time within spec. An oscillator that will run > on 2.5 V would be a much better choice. > > Jon >Article: 76052
"Rob Young" <rwyoung@ieee.xspam.org> wrote in message news:<10q6lkmdsjalh12@corp.supernews.com>... > There may be a better way but I just made a "dummy" output port and assigned > the signal in question to that dummy port. This was only for the simulation > stage and I am aware that it could alter the routing for post-fit > simulations. In my case, I was only using about 10% of the chip for that > particular experiment so I wasn't very worried and so I did not make any > comparisons of the fit/placement charts with and without my "dummy" output. > > Rob Young Hi, I is there nobody who can tell me, how to trace a signal with Quartus II. I try it with the RTL-Viewer and with the Simulation-Waveform but it doesn't work!! I really need help from somebody who have expirience with Quartus II! I am nearly finished with my bachelor lecture... but I can't end it because my last job is to trace a input-signal in the Post-Compilation. @Rob: Thanks, but my professor unfortunately don't want your method of resolution. :( Thanks to all. EmrahArticle: 76053
On 22 Nov 2004 05:59:04 -0800, javaguy11111@gmail.com (DB) wrote: >I have seen a few low cost($100-$200) fpga boards with 400k Spartan >3's, but nothing with 1million gates yet. I would think with the >supposedly low price of the Spartan 3 that such boards would have made >an appearance by now. Does anyone know if such a board exists yet. www.xess.com has a 1 mill board for $199 http://www.xess.com/prod035.php3 CarstenArticle: 76054
>www.xess.com has a 1 mill board for $199 > >http://www.xess.com/prod035.php3 > Oopz sorry didnt read thread to end before ansvering. CarstenArticle: 76055
On 22 Nov 2004 14:53:09 -0800, cs_posting@hotmail.com (Chris Stratton) wrote: >"Bob" <nimby1_notspamm_@earthlink.net> wrote in message news:<Gwcod.8180$pK6.1111@newsread2.news.atl.earthlink.net>... >> Just use the series resistor to limit the 8051->S3 high-level current. >> >> In the S3->8051 direction, you don't need anything since LVTTL (3.3V supply) >> has exactly the same logic thresholds as TTL (5V supply). > >That should work with most logic familiers - if he has to talk to 5v >devices that really need a higher input voltage, he should be able to >use widely available 74-whatever-xx DIP package buffers or inverters >in a 3.3v volt-compatible logic family as stand-in level translators. I just read that TI's SN74HCT125 (or other in that XCT series) will do that , it has 2v as minimum Vih , and 0.8v as Vil , and will deliver a TTL compatible output. It even runs off 5v CarstenArticle: 76056
(my comments follow the quoted text) Dave Vanden Bout wrote: > javaguy11111@gmail.com (DB) wrote in > news:85472d99.0411220559.531d4b6b@posting.google.com: <snip> > We have a $199 1M-gate Spartan3 board at http://www.xess.com/prod035.php3. > ---------------------------------------- Very nice looking product. Just the right amount of cool stuff on it. It looks like your company might have the same aversion to BGAs as the company I work for. Dwayne Surdu-MillerArticle: 76057
Oops! Pardon me. I'm wrong. The XS3S1000 appears to be BGA. Dwayne Surdu-MillerArticle: 76058
That sounds good, however, when my ModelSim comes up, I see only the IOs for my top level VHDL code in the Signals Window. I would like to see some internal signals. Brian Drummond wrote: > On Mon, 22 Nov 2004 15:23:17 -0800, "Brad Smallridge" > <bradsmallridge@dslextreme.com> wrote: > >> What are the procedures for adding signals to the simulation? I have >> been going to the SIGNALS pane, and clicking on add to wave signals >> in design. Then, since that seems to give me everything, I start >> deleting most of them. > > Select the ones you want in "Signals" before clicking "Add". > > - BrianArticle: 76059
Doh, I just realised Muthu wants to work with Rocket I/O. I'll get my coat, Syms. "Symon" <symon_brewer@hotmail.com> wrote in message news:30hcmpF30ad6sU1@uni-berlin.de... > "salman sheikh" <sheikh@pop500.gsfc.nasa.gov> wrote in message > news:cnvg9c$nuh$1@skates.gsfc.nasa.gov... > > Muthu wrote: > > > Hi, > > > How to be part of NASA as a VLSI Design engineer? > > > > > > Regards, > > > Muthu > > You must be a US citizen first. > Like Verner von Braun. ;-) > >Article: 76060
Just what I was looking for. Thanks Dave Vanden Bout wrote: > javaguy11111@gmail.com (DB) wrote in > news:85472d99.0411220559.531d4b6b@posting.google.com: > > > I have seen a few low cost($100-$200) fpga boards with 400k Spartan > > 3's, but nothing with 1million gates yet. I would think with the > > supposedly low price of the Spartan 3 that such boards would have made > > an appearance by now. Does anyone know if such a board exists yet. > > > We have a $199 1M-gate Spartan3 board at http://www.xess.com/prod035.php3. > > > > -- > ---------------------------------------------------------------- > Dr. Dave Van den Bout > XESS Corp. > PO Box 33091 > Raleigh NC 27636 > Phn: (919) 363-4695 > Fax: (801) 749-6501 > devb@xess.com > http://www.xess.comArticle: 76061
Somehow I saved something in wave.do but I don't remember how. This has got to be the most cryptic set of windows and patch-on programming I have ever seen. I guess the strategy is to save several do files as you go along and hope for the best? What is the initial do file. I saw something in the tutorial about an ini file. Where does that live? And does Xilinx launch a do file from it's environment to bring up all these windows and libraries?Article: 76062
Hi emrah, > Hello, > > I'm a student and I am working on my Bachelor Lecture. Our tool is > Quartus II, so I have a question. How can I trace a signal of a > design, which doesn't "exist" after the Compilation > (Post-Compilation)? Unfortunately I > didn't find the answer neither on www.altera.com nor in altera > documentations. > I am very grateful, if somebody can help me. > Thanks > > Emrah If you are able to select the signal before compilation, either in the block diagram editor or in the node finder, you can tell Quartus to "Implement as output of Logic Cell" by using the Assignment Editor. This will make sure that the signal is always present in the design (unless it's unnecessary and optimized away). If you use VHDL or Verilog, look at the "keep" synthesis attribute, which does the same thing, but from your source code instead of from the Assignment Editor. Good luck with these clues. Best regards, BenArticle: 76063
Fab wrote: > hello all, > > it is not a question concerning FPGA but I could get the answer here: > > from old devices that went to trash I get two EPM7032VLC44-15 and I would > like to reuse them to build my own very low cost first protoboard for > developping wih VHDL. > > It sounds like ALtera CPLD but I do not find the meaning of VLC, is it a low > voltage version (3.3V)? > > Is it a REprogrammable device? > > Thanks by avance for your help. > > A new device of this size is in the order of 4$. Have a look at the MAX3064, a 3.3V replacement. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 76064
On Tue, 23 Nov 2004, Andi wrote: > Do you have SP2 for Wxp installed? Did you uninstalled everything xilinx 6.2 and edk 6.2 with all service packs? > No, I don't have SP2 installed (I heard it had some issues, so I didn't instal it). To my knowledge, I uninstalled all previous versions of EDK and ISE. I actually installed ISE 6.3 before EDK 6.3 because we received it first. ISE 6.3 works, before and after EDK 6.3i installation. I also installed the new ISE SP and the updates for EDK 6.3.Article: 76065
Hi, I am trying to use the Xilinx ZBT Memory Controller for interfacing the virtex2 with the ZBT memory of the Xilinx board. In the simulation the control, address and data signals seem to be working fine. However, after downloading the description to the board, when I write a data in a memory location and I try to read it then, I don't have the same result.Article: 76066
Hello
I am simulating PPC based system using xilinx EDK. A small assembly
code(shown below) is used to read and write a DCR device register
external to PPC on the DCR bus. We see the bus and PPC getting reset
after the PPC completes the DCR transaction and Modelsim issues the
Warning : UTLB has been flush invalidated. Any help is very much
appreciated.
Thanks
Swamy
# include "stdio.h"
int main()
{
char s [1];
//register unsigned int y asm ("%r1");
s[0]='H';
print("H");
//y=5;
//print("H");
asm("xor %r1,%r1,%r1");
asm("addi %r1,%r1,0xA");
asm("mtdcr 0x3F0,%r1");
asm("addi %r1,%r1,0x12");
asm("mtdcr 0x3F0,%r1");
// asm("addi %r1,%r1,0x2");
// asm("mtdcr 0x3F0,%r1");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("mfdcr %r1,0x3F0");
asm("mtdcr 0x3F0,%r1");
print(s);
while(1);
//sprintf("%d",&y);
//register unsigned int X asm ("%r1");
// printf("%d",y);
//print("E");
// print(y);
return 0;
}
Article: 76067I'm looking at the Spartan-3 development board from nuhorizons (http://www.nuhorizons.com/products/xilinx/spartan3/development-board.html) since it looks like a lot of bang for the bucks. However I would like to know if anyone have tried to use the xc3sprog or similar linux configuration software to program this board ? Or if I should expect any immediate problems with this ? Since the board uses a standard JTAG access I wouldn't expect too many problems, however I would like to know if others have experience with this ? Regards Brian Dam Pedersen M.Sc.EEArticle: 76068
I'm a hardware design engineer with 10years background in FPGA design. To date all my design entry and simulation has been with VHDL but I seem to keep having to type similar (but not identical) ram instantiations/ state machines/ clock domain re-synch processes etc. This ends up a bit tedious and I've been wondering how to circumvent the tedium. I've been looking at the grahical state machine entry facility of Modelsim Design and wondering if it's any good and would end up saving any time. I suspect not or the software industry would have adopred this sort of design entry method years ago. This started me wondering what the favourite design entry optomisation methods of our experienced comp.arch.fpga contributors are? Has anyone had any success with graphical entry? Nial ------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design Cyclone Based 'Easy PCI' proto board www.nialstewartdevelopments.co.ukArticle: 76069
I can't believe I spelt optimisation wrongly :-( NialArticle: 76070
I was looking to the Spartan 3L for use in a low power design that will start up soon. Browsing through the datasheet I found however that there is no real difference between the 3 and 3L. Switching of Vccint to safe power? I assume that when you do this, you lose the configuration too. I don't understand why Xilinx tries to mislead customer with the so called 'low power' FPGA. I'm very disappointed about this approach that I will certainly not use S3 for my future product, and I really hope that other potential customers feal the same about this marketing trick for selling vaporware. Regards, LucArticle: 76071
"Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message news:<10q75ds3vo9tkc5@corp.supernews.com>... > That sounds good, however, when my ModelSim comes up, > I see only the IOs for my top level VHDL code in the Signals > Window. I would like to see some internal signals. > It's been a while since I've used Modelsim, but I think if you open the Hieraki/structure or what ever its called in Modelsim, and click on a submodule the signals in that submodule should then be in the signals window -Lasse > Brian Drummond wrote: > > On Mon, 22 Nov 2004 15:23:17 -0800, "Brad Smallridge" > > <bradsmallridge@dslextreme.com> wrote: > > > >> What are the procedures for adding signals to the simulation? I have > >> been going to the SIGNALS pane, and clicking on add to wave signals > >> in design. Then, since that seems to give me everything, I start > >> deleting most of them. > > > > Select the ones you want in "Signals" before clicking "Add". > > > > - BrianArticle: 76072
"Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message news:<10q75ds3vo9tkc5@corp.supernews.com>...
> That sounds good, however, when my ModelSim comes up,
> I see only the IOs for my top level VHDL code in the Signals
> Window. I would like to see some internal signals.
What I do:
1. Go to the signals window and ADD the signals in the design to
"Wave" and "List." This will add all of the design's signals (all
entities).
2. Go to the procedures and variables windows, go to every module
were you have variables in the procedures window, then select the
variables in the variables window, and add the variables to "wave" and
"list"
3. Go to the list window, and save the dataset as "mylist.do"
4. Go to the Wave window, arrange the signals the way you want,
rename them if it makes it easier to read, change colors if you want,
etc. Then save the file "mywave.do"
5. If you launched Modelsim from another program, like Actel's
Libero, or Xilinx's Webpack for example, you may have a file called
"run.do" which has the commands for modelsim to compile the design
along with the testbench. Just copy that file into a new one (like
"myrun.do"), and append the following lines (change it accordingly):
view wave
view list
run mywave.do
run mylist.do
run 6000ns
So, now you may use the file "myrun.do" to run your simulation the
way you want, with all the signals, variables, colors, order, etc.
that you saved. You may run it from Modelsim's command line as : "run
myrun.do" or you may be able to set the third party program (libero,
webpack, etc.) to use your custom file instead of the generic one.
Good luck.
>
> Brian Drummond wrote:
> > On Mon, 22 Nov 2004 15:23:17 -0800, "Brad Smallridge"
> > <bradsmallridge@dslextreme.com> wrote:
> >
> >> What are the procedures for adding signals to the simulation? I have
> >> been going to the SIGNALS pane, and clicking on add to wave signals
> >> in design. Then, since that seems to give me everything, I start
> >> deleting most of them.
> >
> > Select the ones you want in "Signals" before clicking "Add".
> >
> > - Brian
Article: 76073Luc wrote: > I was looking to the Spartan 3L for use in a low power design that > will start up soon. > Browsing through the datasheet I found however that there is no real > difference between the 3 and 3L. > Switching of Vccint to safe power? I assume that when you do this, you > lose the configuration too. > I don't understand why Xilinx tries to mislead customer with the so > called 'low power' FPGA. > I'm very disappointed about this approach that I will certainly not > use S3 for my future product, and I really hope that other potential > customers feal the same about this marketing trick for selling > vaporware. If you expected the 'L' to be something special, then you will be disappointed. What is different, is they are brave enough to fill out the MAX column in the 'L', but only spec typicals on the non L. As the typicals are the same, you are right - this is a fairly 'minimal sort' of devices. [So the price should be the same too ?] :) -jgArticle: 76074
Luc, Sorry you are disappointed. There are two modes, one the devices are selected for low quiescent current. We have many customers who appreciate this, and are willing to pay a small premium for it. Because they asked for it, we figured out how to offer it. Very similar to speed grades, or in this case, leakage grades. The other mode, is that the device is also tested to be able to be externally switched on and off with its supplies. It may seem like a trick to you, but it is most certainly not. All the IOs and internal logic are well behaved, and the supplies can be switched on and off without any glitching or funny behavior. We also had customers wishing to use the devices in this way. To test and grade devices from the larger population for special applications is not free. To specify and stand behind those specifications allows a wider application of S3 without spending what it would take to make another product line. Customer wins, we win. Again, sorry it did not meet your needs, Austin Luc wrote: > I was looking to the Spartan 3L for use in a low power design that > will start up soon. > Browsing through the datasheet I found however that there is no real > difference between the 3 and 3L. > Switching of Vccint to safe power? I assume that when you do this, you > lose the configuration too. > I don't understand why Xilinx tries to mislead customer with the so > called 'low power' FPGA. > I'm very disappointed about this approach that I will certainly not > use S3 for my future product, and I really hope that other potential > customers feal the same about this marketing trick for selling > vaporware. > > Regards, > > Luc
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Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z