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Apart from behavioral languages such as systemC thats about it,vhdl,verilog,ahdl is rarely used now, so VHDL is about your best bet,its not perfect but its better than a poke in the eye with a sharp stick..Article: 80876
James wrote:
> To this end, I've used a dual clock FIFO, with the write port connected
> to the sensor, and the read port to the avalon interface (+ glue logic,
> of course).
Consider a synchronous fifo on the fastest clock.
Synchronize the slow side to the fast clock.
> Now the problem appears when I use Nios to transfer the contents of the
> FIFO directly to the UART (and to a computer for some post-processing);
> after a few 1000 pixels (around 15% of the total), the stream of data to
> the computer stops.
Smells like a logic race.
Bogus full or empty from the fifo?
After some debugging with Nios' GDB/Eclipse getup
> and SignalTap it appears that the constructed FSM is in no state (since
> the signaltap signals <state_signal>.<state_name> for each of the 3
> states were low).
Consider binary encoding.
> During the compilation process, I received no warnings/errors regarding
> timing constraints etc. or anything else for that matter. I am at a
> complete loss as to how to even begin fixing this. Thoughts anyone?
Logic races come without warning to
teach the lessons of synchronization.
-- Mike Treseler
Article: 80877Hi Jezwold wrote: > Apart from behavioral languages such as systemC thats about > it,vhdl,verilog,ahdl is rarely used now, so VHDL is about your best > bet,its not perfect but its better than a poke in the eye with a sharp > stick.. I agree. If you want to implement the hardware I recomment either verilog or VHDL. AHDL is vendor specific while most vendor tools can deal with both verilog or vhdl or mixed. So now between verilog and vhdl, I can hardly guide you. I don't know verilog but from what I've seen it's more concise than VHDL. The latter tends to be very verbose. However, I work only with vhdl and I'm happy, with generate you can write more "generic" code to be reused and it still syntetize well. Finally, what ever you choose, never forget that you must decribe the hardware you want built and not the behavior you want implemented ! SylvainArticle: 80878
In article <d11kuf$ia5$1@news.dialog.net.pl>,
"Piotr Wyderski" <wyderskiREMOVE@ii.uni.wroc.pl> writes:
|> VHDL: very disappointing, the nicest part of Ada has ben removed.
|> No support for anonymous types, stiff and annoying syntax, weak
|> interface inference (needs explicit component specifications).
Hm, you can define components in packages and just "use" them. So you don't need
to cut'n'paste the interface into each architecture. A lot of VHDL examples
(esp. from the FPGA vendors) don't use packages, as it hides the port names and
makes the instantiation examples harder to understand.
--
Georg Acher, acher@in.tum.de
http://wwwbode.in.tum.de/~acher
"Oh no, not again !" The bowl of petunias
Article: 80879Hi Rob, > Looking at the voltage differences between the Spartan3 and the IDE > interface, it is my guess that I don't need to do any fancy voltage level > adjustments, just put 10 Ohm resistors in the path for unidirectional > lines, and 100 Ohm resistors for the bi-directional lines. I hooked an old HDD to an Altera Cyclone without any resistors to write/port an IDE interface myself. This took about three days to do, and both the Cyclone and the HDD survived this period. But, I have no experience with Spartan, so your mileage may vary. > Also, I will be starting a senior design project soon. My primary goal > when I graduate is to move in to embedded devices/FPGA's. I'd say, do something with System-on-a-chip stuff. From my perspective this would be using an an embedded processor plus custom logic/custom instructions in VHDL or Verilog to do something useful in the DSP arena, like decoding MP3 audio from a hard disk and filtering out the voice during playback (for karaoke or music annotation). If you go for this, make sure you don't quite finish the project - you'll be worth a lot if you can state in your job interview that you can properly implement this functionality now that you've learned from your past experiences. Best regards, BenArticle: 80880
Kelly wrote: > I'm trying to find an experienced FPGA Engineer (currently holding a > clearance) - where do people like this look for jobs typically? The > clearance is critical to this opening. > > Thank you for your help - > > Kelly > kellydingee@adelphia.net Which nation? Which market (Military, Aerospace, Telecommunication, Support)? Full time/Part time/Contract/Subcontract? Each question generates a different answer.Article: 80881
Hi all I'm trying to start learning systemc. The bad thing that when I used the Active VHDL 6.3 (trial version) I didn't find systemc.h in it. Do any one help to get this file. Regards AhmedArticle: 80882
On Sat, 12 Mar 2005 21:01:31 +0000, newman wrote: > > "Mac" <foo@bar.net> wrote in message > news:pan.2005.03.12.19.14.14.656152@bar.net... >> On Sat, 12 Mar 2005 18:52:24 +0000, newman wrote: >> >>> In ISE 6.2i, I compile a design off a mapped drive at a foreign site(ie I >>> did not install the software and do not have administrative privileges). >>> For example, I try to run Map, sometimes it completes with a green check >>> mark, and sometimes it completes with no green check mark. Sometimes >>> when >>> it compiles with a green check mark, and I hit the Map Report, it reruns >>> all >>> the tools again (like xst, ngcbuild, map) as though a source hdl file had >>> been changed. but no source files have been changed. Its maybe like the >>> filesystems are running off two different timestamp clocks? >>> >>> Any ideas? >>> >>> -Newman >> >> The timestamp thing can be a problem for make-based dependency checking >> (which ISE uses). >> >> But if all the design files are stored on the same computer, I would think >> that the timestamp would be consistent across all of them. >> >> As a practical matter, would it be possible for you to simply check the >> time on all relevant computers? The first step to corrective action is to >> determine what the problem is. Inconsistent time is one hypothesis, now >> you should test it. If the time is consistent, then you will have to come >> up with a new hypothesis. >> >> --Mac >> > Well, the files are stored on a remote computer. Looking at the file > timestamps in an explorer window, I did notice that when I refreshed the > window, some of the working files were later than the time displayed on the > local computer (where the compilation takes place). I did bump up the local > time by a couple of minutes in order to guess an approximate equal time for > both computers, but I still experienced the same problem. > > -Newman If you want to solve this problem, here is what I suggest. First, devise a simple, repeatable test which identifies the problem. Then, formulate a hypothesis about what is causing the problem, and take appropriate steps (according to the hypothesis) to make the problem go away. Then perform the simple repeatable test to see if the problem is fixed. If it is fixed, then, just to be sure, undo the fix, and perform the test again to make sure the problem comes back. Sometimes I go back and forth like this several times to really convince myself that I have solved the problem. If the potential solution doesn't work, undo it, and try another potential solution. And so on. In this case, the question you should ask yourself is, did you synchronize the clocks or not? Do you feel that you have ruled out clock differences as a potential cause of the behavior you are seeing or not? If you haven't ruled it out, then keep messing around until you can. I would think the one thing you DON'T want to have, is files with modification times in the future, so if you can't sync the clocks exactly, at least try to make the clock on the system running the compiler slightly faster than the one storing the data. Good luck. --MacArticle: 80883
Moti wrote: > Hi James, > If I understand you correctly, you are using a ONE-HOT encoding style > (3 flops - one for each state) . Try to convert the FSM encoding style > to GRAY and check it out. I've recompiled the FSM with gray coding, so now it seems to be in a valid state, but it seems that the FSM isn't the culprit now. It appears that when my fifo write signal is asserted, the fifo doesn't actually start storing information. The odd part was that it WAS doing that a few microseconds ago at system reset, but no more, and nothing short of a system reset is able to fix it. > Maybe your FSM suffers from some asynchronous > related problems, if the GRAY will reduce or eliminate the occuronce > rate of this problem (no state problem) then you know that you have to > check your design for async hazards. But it seems to me that everything in the circuit is synchronized to either the pixel clock or the system clock, and from what little I remember from my digital logic course I thought the dual clock fifo was supposed to do the synchronization between the two clock domains, so I don't really know where a hazard could exist. > > I hope that it is helpful, Moti. >Article: 80884
Mike Treseler wrote: > James wrote: > >> To this end, I've used a dual clock FIFO, with the write port connected >> to the sensor, and the read port to the avalon interface (+ glue logic, >> of course). > > > Consider a synchronous fifo on the fastest clock. > Synchronize the slow side to the fast clock. > I'm sorry perhaps I don't understand the term "synchronous fifo" or what a dual clock fifo is, but wouldn't the dc-fifo be synchronized on the write side to the write clock, and on the read side to the read clock. If it helps I'm using Altera's provided lpm_fifo_dc megafunction. >> Now the problem appears when I use Nios to transfer the contents of the >> FIFO directly to the UART (and to a computer for some post-processing); >> after a few 1000 pixels (around 15% of the total), the stream of data to >> the computer stops. > > > Smells like a logic race. > Bogus full or empty from the fifo? Well since I'm using Altera's provided megafunction (lpm_fifo_dc), I've assumed that it generates the full/empty signals correctly. But I suppose I could try checking under the hood, tho I'd rather not cuz of the daunting (from my point of view atleast) hierarchy present under the lpm_fifo_dc megafunction. I re-encoded my FSM using gray coding for the states, and it now seems to be in the correct state. However the problem seems to have migrated to the fifo, which doesn't want to store information. When I assert the write signal, it doesn't take for some reason, and the fifo empty signal stays active. Odd thing was that it worked fine but a few microseconds earlier. > > After some debugging with Nios' GDB/Eclipse getup > >> and SignalTap it appears that the constructed FSM is in no state (since >> the signaltap signals <state_signal>.<state_name> for each of the 3 >> states were low). > > > Consider binary encoding. > >> During the compilation process, I received no warnings/errors regarding >> timing constraints etc. or anything else for that matter. I am at a >> complete loss as to how to even begin fixing this. Thoughts anyone? > > > Logic races come without warning to > teach the lessons of synchronization. > > -- Mike Treseler -- JamesArticle: 80885
Alexei A. Frounze wrote about UARTs: > The oversampling not only makes it possible to determine the position of the > start bit, but also it combats the noise and errors. The 16 consecutive > sampled values (each being 0 or 1) are used to decide on the actual bit > value. If most of these 16 samples are 1, it's 1. Otherwise, it's 0. I've never seen a UART that behaves that way. Such a UART would be very unreliable, because if the sender was slightly slow or fast relative to the receiver, the 1 bits would get smeared into adjacent bits. Normal UARTs find the leading edge of the start bit, then wait 8 clocks and sample again to make sure the start bit is valid. After that, they take a single sample every 16 clocks. Some of the fancier UARTs (e.g., some Motorola/Freescale microcontrollers) take samples at 7, 8, and 9 clocks into the bit cell, and will report noise if they are not all equal. EricArticle: 80886
Eric Smith wrote: > Alexei A. Frounze wrote about UARTs: > >>The oversampling not only makes it possible to determine the position of the >>start bit, but also it combats the noise and errors. The 16 consecutive >>sampled values (each being 0 or 1) are used to decide on the actual bit >>value. If most of these 16 samples are 1, it's 1. Otherwise, it's 0. > > > I've never seen a UART that behaves that way. Such a UART would be > very unreliable, because if the sender was slightly slow or fast relative > to the receiver, the 1 bits would get smeared into adjacent bits. > > Normal UARTs find the leading edge of the start bit, then wait 8 clocks > and sample again to make sure the start bit is valid. After that, they > take a single sample every 16 clocks. > > Some of the fancier UARTs (e.g., some Motorola/Freescale microcontrollers) > take samples at 7, 8, and 9 clocks into the bit cell, and will report noise > if they are not all equal. Another example : The 80C51 UART sampled 3 times, in mid-bit, and does a majority vote. It does not flag any errors on this. Some UARTs start looking for a START egde, at the END of the Stop bit. As an excercise, consider if this is a good idea, and if not, what would be better ? jgArticle: 80887
Nemesis wrote: > Hi everyone, > I'm going to buy Xilinx ISE Foundation, I'd like to know if this package > contains also IP cores like DDC, FFT and so on. > It seems that the "LogiCore" IPs should be shipped within ISE > Foundations, am I right? > Yes, ISE Foundation comes with Coregen.Article: 80888
Hello Marco, i had the same problem, edit the file: bfm_sim_xps.make in your project directory and uncomment "SUBMODULE_OPT = -lp ../../../.." with "#". I don't know if this is the correct solution, but it work's for me. Daniel Marco schrieb: > I'm trying to perform a simulation of my OPB peripheral. > > I have done the following steps: 1. Opened bfm_system.xmp project in XPS. 2. Clicked Options -> Project Options ... to open up the Project Options and modified 3. Clicked Tools -> Generate Simulation HDL files in XPS to generate the BFM simulation platform. > > This is the console log: > > (Console Log) PM_SPEC -- Xilinx path component is <C:/EDK> Project Opened. At GMT date and time: 2005:3:11:13:10:38 Command bash -c "cd /xygdrive/c/edk_user_repository/MyProcessorIPLib/pcores/opb_lcd_display_v1_00_a/devl/bfmsim/; /usr/bin/make -f bfm_sim_xps.make simmodel; exit;" Started... > * ******************************************** Create behavioral simulation models ... > * ******************************************** simgen bfm_system.mhs -p xc3s200ft256-5 -lang vhdl -lp ../../../../../ -mixed yes -s mti -X C:/ISE_Lib/ -E C:/EDK_Lib/ -m behavioral Simulation Model Generator Xilinx EDK 6.3 EDK_Gmm.10 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. > > PM_SPEC -- Xilinx path component is <C:/EDK> Command Line: simgen -p xc3s200ft256-5 -lang vhdl -lp ../../../../../ -mixed yes -s mti -X C:/ISE_Lib/ -E C:/EDK_Lib/ -m behavioral bfm_system.mhs > > MHS file : \...\devl\bfmsim\bfm_system.mhs Language (-lang) : VHDL Simulation Model (-m) : Behavioral Simulator (-s) : ModelSim (MTI) Part (-p) [ family ] : xc3s200ft256-5 [ spartan3 ] Output directory (-od): C:\edk_user_repository\MyProcessorIPLib\pcores\opb_lcd_display_v1_00_a\devl\bfms im\ > > Edklib (-E) : C:\EDK_Lib\ Xlib (-X) : C:\ISE_Lib\ > > Library Path (-lp): C:\edk_user_repository\ > > Simulation Model Generator started ... > > Reading MHS file ... lp : C:\edk_user_repository\ ERROR:MDT - Path 'C:\edk_user_repository\' already added. make: *** [simulation/behavioral/bfm_system.do] Error 1 Done. > > What I could do to solve the troulbe? > > Thanks MarcoArticle: 80889
> Another example : The 80C51 UART sampled 3 times, in mid-bit, and does a > majority vote. It does not flag any errors on this. Wehn I have done UARTs, I put the filter before the start bit detector so if there is is a glitch in the beginning of the start bit, then this is filtered away, Come to think ábout it, this might be a bad idea if there is a positive spike after the start bit is detected, DO we know for sure that it is only the middle of the startbit that is filtered or is the start bit edge filtered as well. Some UART detect 8 valid samples low and some only sample half a bit time after the first low is detected. Any comments on what is good and what is bad? > Some UARTs start looking for a START egde, at the END > of the Stop bit. As an excercise, consider if this is a good idea, and > if not, what would be better ? > > jg > Aint a good idea if the sending UART is faster than the receiving UART. Then you will sample at your perceived end of stop bit and the sender has at that time already started sending the next startbit Eventually you will lose one character. Have to start searching for the startbit after 3/4 or shorter depending on error. -- Best Regards, Ulf Samuelsson ulf@a-t-m-e-l.com This message is intended to be my own personal view and it may or may not be shared by my employer Atmel Nordic ABArticle: 80890
I am using the same board..and have almost the same problem.. When I use the command below in EDK testApp Xuint32 FIFO_mReadReg(Xuint32 BaseAddress, unsigned RegOffset) the base address is 0x00000000 shall I use the offset below? #define FIFO_IPIF_RDFIFO_DATA_SPACE_OFFSET (0x00000300) After download the bitstream, I use 'mrd 0x00000300' in xmd, it seems that nothing is written in the memory... You can read '1' and '7' at least...but I have nothing........so sad...Article: 80891
Użytkownik "Joel Kolstad" <JKolstad71HatesSpam@Yahoo.Com> napisał w wiadomości news:C6CdneUiR69idqzfRVn-1w@comcast.com... > Does anyone know where I might obtain some Actel A54SX16P FPGAs in the > VQ100 package? Actel has exactly one distributor, and they're out of > stock for awhile. We've been searching the gray market some, and I > figured I'd ask here. > > Speed grade doesn't matter, pricing isn't too important (within reason), > just the package and the fact that it's the 'P' suffix (we're using it > with 5V inputs). We're after about 250, although smaller quantities would > be fine too since we don't need them all right away. > > The sooner we could get some... the better! > > If you know of a source, please reply to jkolstad71@yahoo.com or to the > group. > > Thank you, > ---Joel Kolstad Hi, Try www.hkinventory.com Best regards Jaroslaw CzulaArticle: 80892
does anybody try it with a different linux platform from red hat enterprise? I have a debian testing and it don't work Eric Smith ha scritto: > Ray Andraka <ray@andraka.com> writes: > >>FWIW, I don't even load a mjor release anymore until service pack 1 is >>out. Better to let someone else find the easy bugs! > > > I just load it in a different directory. If I have trouble with it, I > can easily switch back to the previous release.Article: 80893
Jezwold wrote: > its not perfect but its better than a poke in the eye with a sharp > stick.. Only *just*... ;) MarkArticle: 80894
antonio bergnoli <bergnoli@pd.infn.it> wrote:
> does anybody try it with a different linux platform from red hat
> enterprise? I have a debian testing and it don't work
> Eric Smith ha scritto:
> > Ray Andraka <ray@andraka.com> writes:
> >
> >>FWIW, I don't even load a mjor release anymore until service pack 1 is
> >>out. Better to let someone else find the easy bugs!
> >
> >
> > I just load it in a different directory. If I have trouble with it, I
> > can easily switch back to the previous release.
Download the shell script.
Edit the script to not erase the payload on error:
#!/bin/sh
# This script was generated using Makeself 2.1.2
CRCsum="3131057736"
MD5="00000000000000000000000000000000"
TMPROOT=${TMPDIR:=/tmp}
label="Xilinx ISE WebPACK Installer"
script="./setup"
scriptargs=""
targetdir="wpdl_all_lin.build"
filesizes="390880212"
keep=y
^^^^^^^
Change from n to y
Now run again. The directory "wpdl_all_lin.build" should get created.
Try to find "libcurl.so.2" and copy to
wpdl_all_lin.build/platform/lin/bin
set the DISPLAY variable to :0
Run wpdl_all_lin.build/setup...
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de
Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Article: 80895The free versions dont have those features. You can ask them for a one month eval license.Article: 80896
Hi all, I am developing my first circuit board with FPGA. Trying to make a circuit board without PROM for FPGA programming so just using the FPGA, hence cutting down the cost as well for security. Planning on using the JTAG method where the bit file is used to directly program the FPGA. In this case since the FPGA needs to be programmed every time on powerup, is there a cache in the FPGA which stores the bitstream and configures the FPGA each time on powerup. Or does the bitstream need to be downloaded each time when the FPGA is powered up unlike the PROM method where the FPGA gets configured from the PROM. I couldnt find any documentation on Xilinx website for these questions. So any help with this is greatly appreciated. Thanks & regardsArticle: 80897
The goal of the PhD Forum is for PhD students to give exposure to their work and to get feedback from experienced researchers and industrial partners. The accepted contributions will be published in the proceedings and the PhD students will present their work in a special poster session during the conference. Eligibility conditions Eligible students need to fulfil the following conditions: - Minimum 1 year of experience in a PhD program - PhD not completed yet at the time of submission - University approved thesis proposal or 1 published paper - Has not been accepted to a PhD forum in an earlier FPL conference Financial support Selected PhD students will receive a free registration to the conference and a reimbursement of their travel costs up to 750 Euro. Paper formatting - The PhD forum submission must not exceed 2 pages. Follow the general submission guidelines. http://fpl.cs.tut.fi/ and click PhD Forum. Contact PhD Forum Chair Philip Leong The Chinese University of Hong Kong, Hong Kong fpl-phd-forum@cs.tut.fi -- T.RissaArticle: 80898
"Eric Smith" <eric@brouhaha.com> wrote in message news:qhu0ne4ys9.fsf@ruckus.brouhaha.com... > Alexei A. Frounze wrote about UARTs: > > The oversampling not only makes it possible to determine the position of the > > start bit, but also it combats the noise and errors. The 16 consecutive > > sampled values (each being 0 or 1) are used to decide on the actual bit > > value. If most of these 16 samples are 1, it's 1. Otherwise, it's 0. > > I've never seen a UART that behaves that way. Such a UART would be > very unreliable, because if the sender was slightly slow or fast relative > to the receiver, the 1 bits would get smeared into adjacent bits. I don't see where it's unreliable. The majority tells the final value. Your "slightly", which is about 1/16th of the bit duration isn't going to make it unreliable so badly. > Normal UARTs find the leading edge of the start bit, then wait 8 clocks > and sample again to make sure the start bit is valid. After that, they > take a single sample every 16 clocks. > > Some of the fancier UARTs (e.g., some Motorola/Freescale microcontrollers) > take samples at 7, 8, and 9 clocks into the bit cell, and will report noise > if they are not all equal. That's fine. AlexArticle: 80899
Hi all, I want to graphically create and edit waveforms for documentation purpose. Xilinx's HDL Bencher does not exist under Linux... (too bad: it can export in HDL) Waveformer is $6000, gasp! A guy here uses some commercial spreadsheet...;-) please tell me what do you use!
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Compare FPGA features and resources
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Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z