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B. Joshua Rosen wrote: > On Mon, 04 Apr 2005 19:48:58 +0100, Thomas Womack wrote: > > >>Is there any way of using the Xilinx toolchain on a Mac? >> >>I have become spoiled by my Mac Mini, and unpacking my loud PC >>just to run place-and-route seems inelegant. >> >>Tom > > > Take your PC, put Linux on it, install the Linux Xilinx tools, put it in > another room and then rlogin or ssh into it. The Mac will make a fine > X server. You can do all of your work from the Mac while the PC is safely > out of earshot. Not if you want to run the EDK. On a Mac X display, drop-down menus appear at screen co-ords (0,0), and the 1st option is unselectable. Oh, and the EDK misbehaves when you get to the 'add peripherals' stage - you can never get past that screen. Running using VNC from the linux box to the mac is better, but you still get lag and sometimes strange behaviour. I've just bought a DVI KVM, so I can run the EDK on my Linux box with the output going to my gorgeous mac monitor - it's the only solution I can find that has no problems :-( Oh, and a bog-standard 64-bit AMD box (2GHz) runs about 3x the speed of a dual 2GHz G5 box when running iverilog, so it'll be a *lot* faster than on a G4 Mac Mini. I love the form-factor of the mini, but a computing powerhouse it most certainly ain't. I'd say the AMD box would be ~10x the speed of the mini... Simon.Article: 82176
Hi Group,
I am using SPARTAN3 CLBs to divide a clock. I can't use the DCM because
the input clock is less than the minimum required by the DCM. Does
anybody know how to calculate/estimate the jitter on the divided clock?
I am using the following VHDL code to divide by 2
div2: process
wait until Clkin'event and Clkin = '1';
Clkdiv2 <= not Clkdiv2;
end process;
Thanks in advance.
Sudhir
Article: 82177<Sudhir.Singh@email.com> schrieb im Newsbeitrag news:1112937690.795304.253750@l41g2000cwc.googlegroups.com... > Hi Group, > I am using SPARTAN3 CLBs to divide a clock. I can't use the DCM because > the input clock is less than the minimum required by the DCM. Does > anybody know how to calculate/estimate the jitter on the divided clock? > > I am using the following VHDL code to divide by 2 > > div2: process > wait until Clkin'event and Clkin = '1'; > Clkdiv2 <= not Clkdiv2; > end process; > > Thanks in advance. > Sudhir > is your clock less than 1MHz? for S3 the minimum supported clock is 1MHz (DFS mode) antti http://gforge.openchip.orgArticle: 82178
Hi Antti, My clock frequency is 10.84MHz. I tried to use the CoreGen on Xilinx ISE to create the DCM component but it didn't let me. It gave a error message that the minimum clock frequency was something like 25MHz. Have you used the CoreGen or manually done DCM settings? ThanksArticle: 82179
<Sudhir.Singh@email.com> schrieb im Newsbeitrag news:1112939292.255805.314940@l41g2000cwc.googlegroups.com... > Hi Antti, > My clock frequency is 10.84MHz. I tried to use the CoreGen on Xilinx > ISE to create the DCM component but it didn't let me. It gave a error > message that the minimum clock frequency was something like 25MHz. > Have you used the CoreGen or manually done DCM settings? > > Thanks you can not use CLK0 outputs must deselect all those, leaving FX only then you can use coregen for DCM input as low as 1MHz anttiArticle: 82180
Hi all, I'm working with ISE 6.3 under Windows right now, I'd like to use it under Linux but I'm holding back because MXE will not work under Linux. Any solutions? I will be using Suse 9.3 (when it's released). From the simulator, I only need the ability to simulate my design with a testbench, I don't need TCL, etc. My design uses placed LUTs and FFs, no synthesized logic. I did look in the usual places like Freshmeat etc but I'm overwhelmed by the number of choices. Thanks! -JimArticle: 82181
Thank you Antii.Article: 82182
Dear all, I'm a little bit confused about the usage of IBUFGDS and IBUFDS. In my design (on a XC2V8000 fpga) I have to acquire LVDS input data using a LVDS clock which comes from an external board. It is not really clear to me which is the best between these 2 options 1) use IBUFGDS on clock and then drive a BUFGMUX 2) use IBUFDS on clock and then drive a BUFGMUX Data input goes to IBUFDS. In both cases the output of BUFGMUX is a global line, so I don't understand which is the best option and the differences between IBUFGDS and IBUFDS. Any advice about that ? Thanks in advance.Article: 82183
Terje Mathisen <terje.mathisen@hda.hydro.com> writes: >I have never seen either the patent or the relevant MIPS asm code >generated, but it seems to me that the hw I'd want would look like this: Well, what you describe is pretty much how Alpha does it. MIPS does it differently. >a) > > LoadAligned r1=[r0] > >where any low-order bits in r0 would be ignored. Alpha calls this instruction ldq_u (u for unaligned). >c) (The somewhat tricky one!) > > ShiftToAlign r3=r1,r2,r0 Alpha uses three instructions for that. Two extq instructions for shifting and masking r1 and r2, and an or instruction to combine the results. Overall an unaligned load looks like this on Alpha: lda at,0(t0) ldq_u t9,0(at) ldq_u t10,7(at) extql t9,at,t9 extqh t10,at,t10 or t9,t10,t3 The lda (for computing the effective address) could be optimized away in nearly all cases, but that effort was apparently not expended by gas. It is interesting that the offset for the second ldq_u is 7, not 8 (and the extqh must match that). My guess is that this is done so that you do not get an exception when you use this sequence for loading the last word of a page with an aligned address. Hmm, this requires two instructions, which are just used for this purpose AFAIK: extqh and extql (ldq_u is also used for byte loads etc. on the Alpha). How much longer would the sequence be if we allowed only one 2-in-1-out special-purpose instruction, or none (but slightly more general-purpose shift-and-mask-byte instructions)? I can see how to do it with one less instruction with two special-purpose instructions: extqh does not need to set the low-order byte (this can be covered by extql in every case), so it could store the low-order bits of the address there. Then extql could be modified to take the result of extqh instead of the address, and perform the merge. The sequence would look like: lda at,0(t0) #can be optimized away ldq_u t9,0(at) ldq_u t10,7(at) extqhx t10,at,t10 extqlor t9,t10,t3 This probably would have required additional muxes in the data path, though. Followups set to comp.arch. - anton -- M. Anton Ertl Some things have to be seen to be believed anton@mips.complang.tuwien.ac.at Most things have to be believed to be seen http://www.complang.tuwien.ac.at/anton/home.htmlArticle: 82184
On 2005-04-08, Jim George <send_no_spam_to_jimgeorge@gmail.com> wrote: > I'm working with ISE 6.3 under Windows right now, I'd like to use it > under Linux but I'm holding back because MXE will not work under Linux. > Any solutions? I will be using Suse 9.3 (when it's released). From the > simulator, I only need the ability to simulate my design with a > testbench, I don't need TCL, etc. My design uses placed LUTs and FFs, no > synthesized logic. You should check out Google archives of comp.lang.vhdl. It has been discussed there several times. In short, free alternatives: - GHDL - Savant - FreeHDL Savant and GHDL are probably best, FreeHDL was missing quite many features when I last time looked (granted, quite a long time ago). Simili from SymphonyEDA is free, as in no cost. Also many expensive commercial simulators are available for Linux, I'm quite sure ModelSim is. Use Google to find them.Article: 82185
Hello All, If I am using a Xilinx or any other FPGA and I am not using the platform flash which is recomended to configure FPGA. I am configuring FPGA in a slave parallel mode or in case of xilinx say Slave Select Map. In this case I want to simulate the whole set up say one general purpose flash one CPLD and FPGA for configuration. Can I do that ...? will the simulation model of FPGA configuration functionality be available...? Regards KedarArticle: 82186
"Kedar P. Apte" <kedarpapte@gmail.com> schrieb im Newsbeitrag news:f37647e6.0504072343.c26d6c4@posting.google.com... > Hello All, > > If I am using a Xilinx or any other FPGA and I am not using the > platform flash which is recomended to configure FPGA. > I am configuring FPGA in a slave parallel mode or in case of xilinx > say Slave Select Map. > In this case I want to simulate the whole set up say one general > purpose flash one CPLD and FPGA for configuration. Can I do that ...? > > will the simulation model of FPGA configuration functionality be > available...? > > Regards > Kedar to my best knowledge it is not available when I was doing FPGA testing for MMC card based FPGA loader (only takes 21 PLD Cells!) then I wrote a partial FPGA configuration model for the master serial mode that was used in testing. Similarly the parallel mode model could be written too. AnttiArticle: 82187
Kryten wrote: > "Leon Heller" <leon_heller@hotmail.com> wrote in message > news:42556b03$0$289$cc9e4d1f@news-text.dial.pipex.com... > >>http://www.fpgajournal.com/articles_2005/20050405_cray.htm > > > Apart from abusing the word 'leverage' as a verb, > the article seems big on gas and small on substance. > Which is essentially > > "Cray machines are using Xilinx FPGA as computing engines". > > BFD. > > The Sanger Centre has used FPGA solutions to accelerate pattern-matching in > DNA sequencing. > > And that was not rocket science either, as this is essentially comparing a > pattern with bits in a shift register. > > > > > > Well, fpgajournal is more focused on advertisement than on science... and they are late: the XD1 was presented at SuperComputing'04. Cray is not the first to see DNA comparison as a possible application for high performance computing, and the market is already well occupied by IBM, SUN, ..., life science departments. Sun Servers can include Timelogic FPGA accelerators for DNA applications, and they know what thay are talking about. The real question, I think, is how to use XD1? Who will make the RTL? Who will split the algorithms on the cluster, and then, between SW and HW? "C to RTL" is far from ready, and still need a lot of human intervention. So what? Cray will sell the machine or the engineers going with? I'd like to play with, anyway!Article: 82188
"John Mashey" <old_systems_guy@yahoo.com> writes:
> The *point* of the patent was that if you have a straightforward RISC
> pipeline that supports caches and paged virtual memory, then requiring
> hardware to do all the work of handling arbitrarily-aligned data [i.e.,
> crossing cache-line or worse, page boundaries] adds *greatly* to the
> implementation complexity, and one doesn't want to do this. [The
> implementation penalty for some microcoded CISCs cn be much less.]
>
> The MIPS solution was some much simpler hardware (very minimal
> additions, and nothing tricky] beyond what was there, that allowed
> compilers to generate code to deal with unaligned accesses that
> sometimes came up from legacy code without burdening the base hardware
> design.
ARM has an "interesting" way of handling unaligned word addresses: If
the address is not word aligned, it uses the rounded-down address to
load a word but then rotates the word such that the byte at the
unaligned address is the LSB of the resulting word (this is for
little-endian mode). The behaviour is probably a side-effect of the
byte load instruction (which ANDs with 0xFF after the rotate). I once
wrote a fast string copier that exploited this behaviour, but I don't
think it makes unaligned word access any faster.
Torben
Article: 82189Sudhir.Singh@email.com wrote: > Hi Group, > I am using SPARTAN3 CLBs to divide a clock. I can't use the DCM because > the input clock is less than the minimum required by the DCM. Does > anybody know how to calculate/estimate the jitter on the divided clock? > > I am using the following VHDL code to divide by 2 > > div2: process > wait until Clkin'event and Clkin = '1'; > Clkdiv2 <= not Clkdiv2; > end process; > > Thanks in advance. > Sudhir Howdy Sudhir, If you are truely concerned about jitter, using the DCM would not be the way to go, even if it did let you. The datasheet lists CLKOUT_PER_JIT for a DCM... it's lowest when using the CLK0 output, and highest when using the CLKFX output, where I don't recall ever seeing anything less than 600ps of jitter spec'ed: http://www.xilinx.com/applications/web_ds_v2/jitter_calc.htm To minimize jitter, don't use a DLL/DCM, stay off the global clock lines, and keep the routing as short as possible within the device (put the output pin close to the input pin). Good luck, MarcArticle: 82190
Hi, We have a design with a microblaze which runs from bram at startup (connected through the LMB bus). After startup it is possible to download an application to sdram (connected through the OPB bus) and run from sdram. Since we are going to change the fpga type and get a lot more brams available; we are thinking to remove the sdram (to reduce costs) and replace it by bram. My question is: is it possible to have a microblaze with bram connected to the LMB bus and a seperate bram connected to the OPB bus and have different programs in the brams (a bootloader in de bram which is connected to the LMB bus, and an application downloaded at runtime in the bram which is connected to the OPB bus) and run both of them (not at the same time of course)? As far as I can see, it doesn't matter what kind of memory is used for the application (bram or sdram) as long as the code is built to run from the correct addresses. Can anyone confirm this and/or has experience with this? Thanks in advance, FrankArticle: 82191
Hi, im tryin to perform a 2D DCT in VHDL with modelsim simulator but to be honest with you i don't know how to start so if someone can help me it will be great. thanks Wojtek/PolandArticle: 82192
I want to simulate a fpga-based SDRAM controller with a SDRAM model. Say the PCB delay is 1 ns, shall I delay the feedback clock with 1ns or 2ns (because of the round trip trace on the PCB)?Article: 82193
Frank,
why not having the whole bram (sum of your LMB and OPB) attached to LMB
only? how is helping you if you have two mems on different buses? (OBP
can get slow if you have to many peripherals...)
Aurash
Frank van Eijkelenburg wrote:
>Hi,
>
>We have a design with a microblaze which runs from bram at startup
>(connected through the LMB bus). After startup it is possible to download an
>application to sdram (connected through the OPB bus) and run from sdram.
>Since we are going to change the fpga type and get a lot more brams
>available; we are thinking to remove the sdram (to reduce costs) and replace
>it by bram.
>
>My question is: is it possible to have a microblaze with bram connected to
>the LMB bus and a seperate bram connected to the OPB bus and have different
>programs in the brams (a bootloader in de bram which is connected to the LMB
>bus, and an application downloaded at runtime in the bram which is connected
>to the OPB bus) and run both of them (not at the same time of course)?
>
>As far as I can see, it doesn't matter what kind of memory is used for the
>application (bram or sdram) as long as the code is built to run from the
>correct addresses. Can anyone confirm this and/or has experience with this?
>
>Thanks in advance,
>Frank
>
>
>
>
--
__
/ /\/\ Aurelian Lazarut
\ \ / System Verification Engineer
/ / \ Xilinx Ireland
\_\/\/
phone: 353 01 4032639
fax: 353 01 4640324
Article: 82194We use always the same bitgen options for all designs. Did you programmed a bitfile containing MicroBlaze via Slave-Serial-Mode(i.e. using a CPLD)?Article: 82195
The bitfile has always the same length (3961632 bit for an Spartan2E-600)! The bitfile in the FLASH has always the same lenght, it starts with the synchronization words (FF FF FF FF AA 99 55 66...) and ends with the dummy words. The FLASH has width of 64 Megabit. We use the AM29LV640MH/L from AMD.Article: 82196
I am looking for heat sinks with an attached fan for use on a Xilinx FF1152 package on a PCI card. Aavid Thermalloy has some on their web site, but they are either special order, or discontinued. Does anyone know of some other sources that they would recommend? Thank you, John McCaskill jhmccaskill@ domain aboveArticle: 82197
Dear All, Is the answer to the following question, "You Can't!" and does this mean that there is such a word as "can't"? Question: How can one simulate the Rocket I/O MGT block in ModelSim XE? Cheers SimonArticle: 82198
http://support.xilinx.com/xlnx/xil_tt_faq.jsp?iLanguageID=1&sProduct=MXE+III#139 Q11 Can MXE III simulate the Xilinx PPC405 and Gigabit I/O SWIFT Models? No -- to simulate SWIFT models, you will need a SWIFT-compliant simulator such as ModelSim SE, ModelSim PE, Synopsys VCS, or Cadence NC-Sim. stockton wrote: > > Dear All, > > Is the answer to the following question, "You Can't!" and does this > mean that there is such a word as "can't"? > > Question: How can one simulate the Rocket I/O MGT block in ModelSim > XE? > > Cheers > > SimonArticle: 82199
No problem having both LMB and OPB BRAM visible to the same processor as long as the addresses are not overlapping as indicated in the original post. I agree that LMB is likely preferred if the Microblaze is the only entity to access the memory space. OPB BRAM might be needed if other peripherals require access to the memory such as a DMA engine. Paul Aurelian Lazarut wrote: > > Frank, > why not having the whole bram (sum of your LMB and OPB) attached to LMB > only? how is helping you if you have two mems on different buses? (OBP > can get slow if you have to many peripherals...) > Aurash > > Frank van Eijkelenburg wrote: > > >Hi, > > > >We have a design with a microblaze which runs from bram at startup > >(connected through the LMB bus). After startup it is possible to download an > >application to sdram (connected through the OPB bus) and run from sdram. > >Since we are going to change the fpga type and get a lot more brams > >available; we are thinking to remove the sdram (to reduce costs) and replace > >it by bram. > > > >My question is: is it possible to have a microblaze with bram connected to > >the LMB bus and a seperate bram connected to the OPB bus and have different > >programs in the brams (a bootloader in de bram which is connected to the LMB > >bus, and an application downloaded at runtime in the bram which is connected > >to the OPB bus) and run both of them (not at the same time of course)? > > > >As far as I can see, it doesn't matter what kind of memory is used for the > >application (bram or sdram) as long as the code is built to run from the > >correct addresses. Can anyone confirm this and/or has experience with this? > > > >Thanks in advance, > >Frank > > > > > > > > > > -- > __ > / /\/\ Aurelian Lazarut > \ \ / System Verification Engineer > / / \ Xilinx Ireland > \_\/\/ > > phone: 353 01 4032639 > fax: 353 01 4640324 > >
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Threads starting:
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