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I missed your original post, so I'll reply here.
1) the polyphase decimator is a mathematical manipulation to reduce the
computational load. From a black box perspective, it provides the same
output as you would have using a single rate filter followed by a
decimator (dropping output samples). The difference is if you are
clever about your filter implementation, you don't have to do all the
computation for samples that are dropped. The polyphase filter takes
advantage of that fact. It consists of R sub-filters whose outputs are
summed. Each subfilter is running at the decimated sample rate instead
of the input sample rate, so you get a reduction of the computations per
unit time by a factor of R (R is the decimation ratio).
2) Multichannel operation is achieved by doubling the tap delays and
interleaving the samples from each channel. The physical filter is
operated at C times the sample rate (C is the number of channels). In
order to do that, you need a multiplied clock and your logic has to be
fast enough to operate at the increased clock rate. The reason for
doing this is to reduce the size of the hardware by time-sharing (the
classic time-area trade-off).
Where you have multiple bandwidths, you've got an opportunity to change
the output sample rate to match the selected bandwidth. The advantage
to using a CIC filter is that the filter shape referred to the output
sample rate is nearly independent* of the decimation ratio. That means
that you can follow the CIC with a filter that does not have to be
changed when you change the bandwidth. In your case, you have only two
bandwitdh settings, so it is not unreasonable to change filter
coefficients to change the bandwidth. In either case, if you have a
sample decimation ratio greater than 2, it is usually more efficient in
terms of computation and amount of hardware to use a multi-rate approach
where you decimate in each stage of a multi-stage filter. My DDC
designs typically include a mixer followed by a CIC filter, followed by
two stages of decimate by 2 FIR filters, the first of which is a
halfband filter with a relatively small number of taps (typically around
15). If using a CIC, you'll want the final bandwidth to be no more than
1/4 the CIC's first null in order to keep the CIC's droop manageable.
* The CIC filter response has a very small component that is dependent
on the ratio, which is only minimally noticible at ratios less than
about 15.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 81326Hi Henrik, Henrik Koksby Hansen wrote: >>>I am not sure but is this got something to do with the DONE pin not >>>going high. I dont know abt platform studio but then with Project >>>navigator there is a setting which drives the done pin high that is if >>>the done pin in the circuit is not connected to a pullup resistor. >> >>[...] > Damn, it did not work. After some hours it went mad at me again. > > Does anyone have any ideas on what to try out? I've seen similar strangeness on this board, maybe it's relevant. It occurrs if I have the configuration mode jumpers set for Slave Serial mode (e.g. for configuring from the PROM) but was actually configuring via JTAG instead. The fix for me was to ensure that the mode jumpers were in the exactly correct place. So, for JTAG, I think that's Open closed open closed (from left to right). Or, for PROM-configuration, all closed. Hope this helps, JohnArticle: 81327
Carsten <xnews1@luna.kyed.com> writes: > I have bought the Xilinx FPGA S3 Starterkit , and have a ISE Webpack , > and a time limited ISE 6.2i > > Am i understanding thic correct , that the above is a full ISE6.3i > with no timelimit ??? , and i guess the "No support" means no upgrade > path possible or ???? If you question is whether Webpack is the full ISE, the answer is no. Webpack doesn't support the largest devices, and it doesn't include the FPGA Editor and Core Generator, and probably has some other pieces left out as well. However, Webpack 6.3i (and 7.1i) are still very useful, and the price is right. If Webpack had been available for Linux six months ago, I probably wouldn't have purchased a copy of ISE BaseX, but I don't regret it. EricArticle: 81328
Jason Lewis wrote: > Has anyone checked out the new TI power supply for FPGAs, the TPS75003: > http://focus.ti.com/docs/prod/folders/print/tps75003.html > > I was considering it for a potential Spartan-3E design and was looking for > feedback from anyone who has sampled it or knows more about it. In > particular, I was wondering if the reference design on page 7 of the > datasheet was well suited for the -3E, or if anyone recommended other parts > or modifications. > > Thanks :) For our S3 design, we used the power manager device. It is a programmable power sequencing chip. It saved us as we had to have different voltage sequencing for the fpga and our MCU. If you are using FETs, the 1208 is the one to use. The software is free and it is easy to use. www.latticesemi.com/products/ispPAC/POWRMGR/index.cfmArticle: 81329
drwho8__NOTME__@att.net (The Eighth Doctor) writes: > But we need reccomendations on which programmer to select, and whose. I've been happy with an Xeltek Superpro III, which is discontinued, but refurbished units are available. But I imagine that more recent Xeltek products will also do what you want. The SuperPro Z appears to be roughly equivalent to the Superpro III, and only costs $249. http://www.xeltek.com/ My main device programmer these days is a used Data I/O Unisite, which can program almost any programmable device that was ever made. (It can't handle the first few EPROMs made in the early 1970s, such as the 1701, 1702, 1702A, 5203, and 5204.) If you can find a used Unisite, grab it. New they cost *many* thousands of dollars, but once in a while used ones can be found for under $250. Before you buy a programmer, check the list of supported devices to make sure it can handle the ones you need.Article: 81330
Preben Holm <64bitNOnoSPAMno@mailme.dk> writes:
> Well, I get an error about libcurl.so.2, I only have libcurl.so.3.0.0.
> I tried creating an symbolic linking from libcurl.so.2 to
> libcurl.so.3.0.0 but this doesn't work:
I wouldn't expect it to.
I used libcurl extracted from the curl RPM for Fedora Core 2, and it
worked fine.
I posted instructions for using 6.3i and 7.1i on Fedora Core 3, which
can be found on Google Groups:
http://groups-beta.google.com/group/comp.arch.fpga/msg/4b592cb14bad823f
I think most of the information would be generally applicable to other
distributions.
Eric
Article: 81331
This is what I've been using. The low address stuff is on the right end.
INIT_00 : bit_vector(255 downto 0) :=
-- VIOLET BLUE GREEN ?????? ORANGE RED BROWN TEAL
X"0080017000980101000170010070408000015AD0000101A00001608000707001";
Article: 81332I. Ulises Hernandez <delete@e-vhdl.com> wrote: > Are you sure about that 11 Gbps figure? > > 11.1 was quoted at a xilinx conference I was attending last week. -- Wing Wong.Article: 81333
On Mon, 21 Mar 2005 14:52:39 -0500, "faizal" <faizal@ieee.org> wrote: >hi All, > I am trying to initialize the BLOCK RAM :- RAM16_S2 in a design using the >following statements > On simulation using MODELSIM , I dont get the correct values of the BLOCK >RAM, looks like >the the BLKRAM is failing to Initialize ,inspite of these INIT statements. >What could be the reason? >Thanks >Faizal > > > >generic map ( > INIT_00 => >X"FFFFFFF000000000000000000000000000000000000000000000000000000000", > ----- > ------ > Have you looked in the FAQ? Maybe this will help: http://www.fpga-faq.org/FAQ_Pages/0031_How_to_initialize_Block_RAM.htm =================== Philip Freidin philip.freidin@fpga-faq.org Host for WWW.FPGA-FAQ.ORGArticle: 81334
I. Ulises Hernandez wrote: > Are you sure about that 11 Gbps figure? > > I've just had a look to the latest 'ug' from Xilinx > http://direct.xilinx.com/bvdocs/userguides/ug076.pdf and still says it can > run up to 10.3125 Gbps... so... a pity that they are missing OTU2 (10.709 > Gbps). This implies you still need an LIU between your optics and your V4 if > you want to go up to OTU2, doh! It will support OC192... probably with the > xpensive/fastest speed grade. http://www.google.com/search?&q=11.1+xilinx shows lots of hits for 11.1 Gbps. In fact, it seems the only thing saying 10.3125 Gbps is the most important document of them all, the ten day old V4 RocketIO user guide. BTW, I wouldn't be so quick to use this for OC-192 rate SONET applications... you'll notice the below two pdf's go out of their way to say that the V4 RocketIO is _OC-48_ compliant: http://www.xilinx.com/publications/xcellonline/xcell_52/xc_pdf/xc_v4rocketio52.pdf http://www.xilinx.com/company/press/kits/v4/v4_backgrounder.pdf If it were OC-192 compliant, I suspect they'd be bragging about it. Have fun, MarcArticle: 81335
I've only just started looking at the abovementioned module. I'm attempting to run the testbench as supplied with the OCEIDEC3 core, but it fails with... INFO: WISHBONE MASTER MODEL INSTANTIATED (test.m0) # ***************************************************** # *** IO Test 1 *** # *** Testing WISHBONE wait state insertion, and *** # *** iordy assertion. *** # ***************************************************** # *** MODE SELECT: 'iordy' enable: 0, wb-delay: 0 iordy_del: 0 # >>> Running Read Only test 1 ... (36500) # >>> Running Read/Write test 1 ... (995600) # >>> Running Read/Write test 2 ... (2947600) # >>> Running Read/Write test 3 ... (4899600) # ************************************* # ERROR: Watch Dog Counter Expired Anyone had experience with this? Regards, MarkArticle: 81336
Hi Guys..
I need to write in VHDL code to do a DMA from SDRAM to my IP
on the new ML 310 board..I have lot of questions ..So I just wanted
some example from where in I can start of.But I am not able to find any
examples ..and moreover my IP is sitting on OPB (On Chip Peripheral
Bus)..So I need to be a master inorder to do a DMA ..After that I have
no idea about the things that I have to do ..Actually my questions are
do I need to inlcude the ddr core that Xilinx gives when u create the
EDK project or else do I need to have a SDRAM controller within my IP
only...So if anybody has done this sort of stuff ..please help me out
..
--
Parag Beeraka
Article: 81337
Mark McDougall wrote:
How is this going to work?
[ata_device.v]
always @(posedge ata_dior)
begin
dout = mem[ addr ];
dout_en = 1;
end
always @(posedge ata_dior)
begin
dout_en = 0;
end
Article: 81338If you create the device files, it does. Don't worry I have a sense of humor.Article: 81339
I'll be presenting a Net Seminar on both FPGA and HardCopy II power this Thursday, March 11, at 11 am Pacific Standard Time. It'll be a technical presentation, so I believe it'll be of interest to most of the people on this group who have been following the power debate for the last few months. In this talk, I'll: - give an overview of how to analyze power accurately - describe the steps we took to optimize total device power (dynamic + static + IO) in Stratix II - provide both estimator/specification-based and measured power comparisons between Stratix II and Virtex 4 - describe the power you can expect from Altera's HardCopy II structured ASICs (hint: low :). See http://www.altera.com/education/net_seminars/current/ns-fpgapower.html for details and to register (registration is free of course!). Vaughn Betz Altera [v b e t z (at) altera.com]Article: 81340
I disagree with every claim in Austin's post, which may be a new record. Rather than debate them here in text form yet again, I'd encourage those interested in real power data and comparisons to attend the Power Net Seminar I'm presenting on Thursday, March 24 at 11 am Pacific Standard Time. I'll be providing a lot of detailed power comparisons between Stratix II and Virtex 4, using both measured data and the published estimators and specifications of both companies. As well, I'll provide a first look at HardCopy II power, and show you the power reductions you can expect from it. To register (free of course), see http://www.altera.com/education/net_seminars/current/ns-fpgapower.html. Hope to see you there, Vaughn [v b e t z (at) altera.com]Article: 81341
Mark McDougall wrote: > I've only just started looking at the abovementioned module. > I'm attempting to run the testbench as supplied with the OCEIDEC3 core, > but it fails with... > > INFO: WISHBONE MASTER MODEL INSTANTIATED (test.m0) > # ***************************************************** > # *** IO Test 1 *** > # *** Testing WISHBONE wait state insertion, and *** > # *** iordy assertion. *** > # ***************************************************** > # *** MODE SELECT: 'iordy' enable: 0, wb-delay: 0 iordy_del: 0 > # >>> Running Read Only test 1 ... (36500) > # >>> Running Read/Write test 1 ... (995600) > # >>> Running Read/Write test 2 ... (2947600) > # >>> Running Read/Write test 3 ... (4899600) > # ************************************* > # ERROR: Watch Dog Counter Expired > > Anyone had experience with this? > > Regards, > Mark Try to ask in the OpenCores discussion forum. Thats where you downloaded the module from, right ? I know for a fact that the developer of this module does read the OpenCores discussion forum ... Regards, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and SynthesisArticle: 81342
Rudolf Usselmann wrote: > Try to ask in the OpenCores discussion forum. Thats where you > downloaded the module from, right ? I know for a fact that the > developer of this module does read the OpenCores discussion > forum ... And how would you know that? ;) OK, shall do! Thanks. Regards, MarkArticle: 81343
Hi folks, two things about the EDK on Linux:
1) If I have paid for BaseX 6.3i (and received an upgrade to 7.1i), and
also paid for the EDK 6.3, is there an upgrade path for the EDK as well
? I've only just bought the EDK, do I have to buy it again, or is it
under the same upgrade conditions as ISE ? Or is it just not ready yet ?
2) I think I've found a bug in the EDK's X interface - if you serve the
DISPLAY to a remote machine (in my case, a Mac):
(a) The drop-down menus appear at the top-left screen co-ords,
not under the mouse
(b) More importantly, the Wizard that builds a starting point for
new designs cannot proceed beyond the 'add a peripheral' stage.
No peripherals are shown, and 'Next' just leaves you in the same
state (ie: nothing seems to happen when you press it).
Neither of these are critical, but thought I'd mention it. As to *why*
I'm serving the display to my Mac, well the linux box has a 1024x768
display, and the Mac has a 30" 2560x1600 screen. Which would you prefer
? [grin]
Cheers,
Simon.
Article: 81344> >Another option would be to buy a textbook with or by itself > >the student version of 6.3 which is same as full ise but without > >any support. > >http://www.amazon.com/exec/obidos/tg/detail/-/0131858394/qid=1111234703/sr= 2-1/104-7812736-3159945?v=glance&s=books > > > >Alex > > > > I have bought the Xilinx FPGA S3 Starterkit , and have a ISE Webpack , > and a time limited ISE 6.2i > > Am i understanding thic correct , that the above is a full ISE6.3i > with no timelimit ??? , and i guess the "No support" means no upgrade > path possible or ???? The "Xilinx Student Edition (XSE) 6.3i" is equivalent to the commercial-edition ISE BaseX 6.3. It includes everything except the "FPGA editor" package and technical-support. Xilinx's CoreGen is included (at least it was included with XSE 2.1 and XSE 4.2) Looking at an old comparison-chart, it doesn't look like ISE BaseX 6.3 supports your Virtex4/LX25.Article: 81345
In XCELL issue 52, page 19 Xilinx claims that: V4-PowerPC reduces power 10:1 compared to FPGA Fabric built version (of PowerPC) but that means Xilinx has internally a PowerPC Soft Core IP? If they dont then could not measure the power difference :) I wonder why there is no information about the xilinx soft-core PowerPC at all? AnttiArticle: 81346
"Wing Fong Wong" <wing@stud.com> wrote in message news:d1nql7$r56$1@enyo.uwa.edu.au... > I. Ulises Hernandez <delete@e-vhdl.com> wrote: >> Are you sure about that 11 Gbps figure? >> >> > > 11.1 was quoted at a xilinx conference I was attending last week. > > -- > > Wing Wong. Hopefully any of the Xilinx guys in this group can enlighten us a little bit... Regards, -- I.U. Hernandez " I'm not normally a praying man, but if you're up there, please save me, Superman!" - Homer Simpson ;O)Article: 81347
Am I allowed to change the pin location on the same bank generated by MIG for my virtex4 design ? Would it not be a hassle or restricted if I am forced to use the exact pin location for my DDR2 design ? One of my Virtex4 eval board has it's own fixed DDR2 pins and I would like MIG to follow those pins constraint. Thanks a lot.Article: 81348
Marc, Thanks for pointing me to the XCell paper, they seem to be claiming it's OC-48 complaint... and it makes you doubt about OC-192 if they are not shouting it from the roof tops... it could be jitter in the tx direction or something. As you said, there are lots of 11.1 Gbps figures but suddenly in their last and most recent datasheet no more 11.1Gbps, only 10.3125 Gbps... Regards, -- I.U. Hernandez " I'm not normally a praying man, but if you're up there, please save me, Superman!" - Homer Simpson ;O) "Marc Randolph" <mrand@my-deja.com> wrote in message news:1111460872.774966.176750@g14g2000cwa.googlegroups.com... > > I. Ulises Hernandez wrote: >> Are you sure about that 11 Gbps figure? >> >> I've just had a look to the latest 'ug' from Xilinx >> http://direct.xilinx.com/bvdocs/userguides/ug076.pdf and still says > it can >> run up to 10.3125 Gbps... so... a pity that they are missing OTU2 > (10.709 >> Gbps). This implies you still need an LIU between your optics and > your V4 if >> you want to go up to OTU2, doh! It will support OC192... probably > with the >> xpensive/fastest speed grade. > > http://www.google.com/search?&q=11.1+xilinx > > shows lots of hits for 11.1 Gbps. In fact, it seems the only thing > saying 10.3125 Gbps is the most important document of them all, the ten > day old V4 RocketIO user guide. > > BTW, I wouldn't be so quick to use this for OC-192 rate SONET > applications... you'll notice the below two pdf's go out of their way > to say that the V4 RocketIO is _OC-48_ compliant: > > http://www.xilinx.com/publications/xcellonline/xcell_52/xc_pdf/xc_v4rocketio52.pdf > http://www.xilinx.com/company/press/kits/v4/v4_backgrounder.pdf > > If it were OC-192 compliant, I suspect they'd be bragging about it. > > Have fun, > > Marc >Article: 81349
Hi Gregg, > Hello from the Eighth Doctor > (Apologies if this question is not group appropriate.) > It seems my company's perenial problem with the PAL chips have sprouted > again. The same individual that we created a something or other for, using > a collection of PAL chips, and some normal glue logic wants us to make > more of these things. Essentially a follow on to that thing. What it's > supposed to do isn't the problem. Yet. It's the programming of the blank > parts that is the problem. Can't you convince your colleague to use something slightly more modern than a PAL? I see more and more manufacturers dropping support for PALs (great pity), and PALASM is not the most user-friendly way to develop logic or testing harnesses in. Especially now that (s)he is going to use multiple PALs on a board (s)he might take a look at CPLDs (sort of a super-PAL), which have a larger capacity for logic and registers, plus the great majority can simply be programmed while already soldered on the board through JTAG. I'm professionally biased towards Altera MAX devices, but there's a whole bunch of other CPLD vendors that offer JTAG programmability. Best regards, Ben
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