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Hello, I passed your comments on to those working on the architecture wizard for RocketIO. Based on your comment, I suggested that they consider not only "1-lane" and "2-lane", but "dual 1-lane" as valid configurations for architecture wizard generated output. I also suggested that they add an option for, "I don't want CRC block functions, please hide those ports from me..." which would cause them to be tied off inside the module instead of brought to ports. Having used the architecture wizard for x1 and x4 PCI Express designs, I can appreciate your comment on the number of ports. There are a lot, but then the block has a great deal of capability. Feedback like yours will drive the addition of options to make the resulting architecture wizard modules easier to use in cases where not all the capability is needed. Yes, what you've got right now for a single lane, transmit only function certainly seems like a lot of extra ports! The best I can offer you currently is to sit with the user guide and go through the module's input ports one at a time, determining what value to assign to either deassert them or leave them in a benign state. It is tedioius but not too hard (having done it myself...) If you have specific questions about how to tie a given port, the Xilinx customer applications hotline is the best place to get them answered. EricArticle: 85226
Hi Everybody, Actually I'm pretty new in using Xilinx software so can't yet fix these small troubles by myself. But anyway, I'm trying to build a very simple project using the BSB method described in the Digilent XUPV2P getting started doc. Unfortunately Xilinx hasn't opened a WebCase account for me yet so I can't ask them. Everything was going fine, but after about 7mins of compilation I got these error messages (After all low level, HDL level and software level synthesis were done) Running generate for OS'es, Drivers and Libraries ... Copying Library Files ... ERROR:MDT - ERROR FROM TCL:- cpu () - Couldn't make xmdstub: make[1]: Entering directory `/cygdrive/c/FPGA/testBSB/microblaze_0/code' mb-as -o xmdstub.o xmdstubaddr.s xmdstub.s make[1]: Leaving directory `/cygdrive/c/FPGA/testBSB/microblaze_0/code' make[1]: *** [xmdstub] Error 57 ERROR:MDT - Error while running "generate" for processor microblaze_0... make: *** [microblaze_0/lib/libxil.a] Error 2 Done. If needed I can post all my log file. Thank you all very much for your help and time. DimitriArticle: 85227
praveen.kantharajapura@gmail.com wrote: > > Falk Brunner wrote: > >>"Peter Alfke" <alfke@sbcglobal.net> schrieb im Newsbeitrag >>news:1117771436.575914.41260@o13g2000cwo.googlegroups.com... >> >> >>>I do not know why you are so slow, you could easily be a thousand times >>>faster. >> >>Why hurry withou a need? By scanning so low you >> >>a) consere power >>b) do a debounce >> >> >>>Since you can only detect a single closure, you could encode the scan >>>into a 6-bit word. >>> >>>I am glad you realized that you cannot detect multiple simultaneous key >>>closures, without inserting iolation non-linearities (diodes) into the >>>array. >> >>??? Been there, done that? >> >>I worked on this topic not too long ago, you CAN easyly detect multiple >>pressed keys withOUT having diodes in the matrix. >>All you need is a "walking one" scan. > > > falk, as you know i am implementing this in a CPLD. > In my application i need multiple(two) key press detection. > As many of them are opposing my 36-bit approach for detecting two keys > pressed simultaneously, my question is how will u achieve multiple key > detection with a 6-bit approach. > >>Regards >>Falk > > Probably lost in another thread: Why not output an encoded 8bit byte for each row, at a maximum of 5 simultaneous keys per row. bits 0-4 (5bits) would hold 5 simultaneous key states, bits 5-7 (3bits) would denote which of the 8 rows (Row:0,1,2,3,4,5,6,7) the first bits 0-4 represented. Yes treatment is 40keys. Yes a full scan is 64bits wide. However the data is transfered in very common and manageable 8bit groups. Hey, IMHO! Nme. God Bless.Article: 85228
Hi Antti, > 3 out 4 microblaze user are not able to use 4.0 for uClinux and all those 3 have downgraded to 3.0 > > 1 out 4 reports no problems with 4.0, to my knowledge this one lucky user is working on linux host, all others are doing the EDK system on windows boxes. I took the standard ml401_uclinux_66mhz project distributed via my website, changed microblaze's HW_VER to 4.0, rebuilt, and it appears to work OK. The design marginally fails timing, but it seems that lots of V4 microblaze designs do under 7.1. This is ISE7.1 SP2, EDK7.1 SP1, building under Linux (CentOS 3.4 **) Anyway here's the proof: # cat /proc/cpuinfo FPGA-Arch: virtex4 CPU-Ver: 4.00.a CPU-MHz: 66.666667 BogoMips: 32.87 HW-Div: yes HW-Shift: yes Icache: 16kB Dcache: 16kB HW-Debug: yes Note I'm still building the kernel with the custom toolchain (based on EDK6.3) - am still trying to resolve some issues I'm seeing with the mb-gcc in 7.1 http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux Regards, John ** CentOS is our new recommended platform for Xilinx Linux work - it's a re-engineer of RH EL3.0, and the Xilinx tools work straight out of the box. You do need to rebuild the parallel port and windrvr drivers, but that also works trivially, just download from xilinx, type "make" and you're done.Article: 85229
On Mon, 06 Jun 2005 21:30:33 +0000, Guy Macon wrote: > > > Eric wrote: > >>What is the best FREE Schematic & PCB Layout software available that >>will run on Windoze XP? >> >>I've looked at PCB123.com and Expresspcb.com and they have pretty good >>programs available. Unfortunately if I use either one I'm stuck getting >>the prototypes through them. (Because they won't output Gerbers) >> >>I've also looked at Eagle Layout at cadsoft.de, but the size limitation >>of 100 x 80mm on the free version is a negative. It would work for my >>current project. >> >>I'm just curious at what other people's opinions are. > > > http://bach.ece.jhu.edu/~haceaton/pcb/ > > http://pcb.sourceforge.net/ IME, pcb doesn't run that well on Windows. --MacArticle: 85230
> For the record, I was referring to the Excel spreadsheet 'accuracy'. > > Use of the verilog test bench file with the XPower tool results in a far > better estimate, given the customer actually has captured what is really > happening in their simulation. We've checked XPower's accuracy, and it is much worse than +/-50%. I agree it should be significantly better than the web tool, given that it knows the placement and routing, and is connected to a simulator to get good toggle rates. That leads me to expect a very large error bar on the web tool. > But, have you fixed the power on surge problem in Cyclone II? There is no power-on surge on Cyclone II. Interestingly, Xilinx's web site does not claim there is a power-on surge for Stratix II anymore, nor does it claim any power-on surge for Cyclone II. It appears that your marketing folks have removed their earlier claims related to power-on surge, presumably because they are easily contradicted by a lab measurement. Vaughn Altera [v b e t z (at) altera.com]Article: 85231
So, having had something of a forced absence from FPGA's for a few months, I've just been looking at upgrading to 7.1 for both ISE and EDK. My BaseX subscription seems to have allowed me to update ISE to 7.1, but I can't see any way of upgrading my EDK ? Questions: 1) Is it possible to do an upgrade, or is it a question of re-purchasing the EDK every time there's a release ? I bought it in March (just checked the order :-) and I thought you got upgrades for a year ? 2) Will the EDK 'service pack 7_1_01' (which I do seem to have access to) upgrade a 6.3 version of the EDK ? 3) Am I simply being stupid and missing the blinking neon lights somewhere on the site saying 'Oy, it's over here'... ? Tx for any help :-) SimonArticle: 85232
Joe, You are making us to answer question without knowing your background. Why donot you tell us which USB core you are having and what is this non AHB interface you are talking. you got to describe your problem. Good luck Regards PraveenArticle: 85233
Fred, Peter is right there is plenty of the XC3S200. It is those of us using the larger parts who have soiled underwear.Article: 85234
In my old Olympus C900Z, it has very brilliant color display, and a resonable 240*180 resolution. When I opened it, the connectors and everything are in good order. Now I need to find out the connection so that I can use it in my hobby projects. Is there a standard connection for such small LCD displays? Thanks.Article: 85235
5v inputs apparently can cause damage over time. I used series resistors to get a simple IDE interface up and running on the digilent S3 kit a while back... don't remember the particulars, other than that it was a couple days of frustration before I learned to talk to the drive, but after that it went quite well. Unless you are doing one of the really high speed modes, small resistors should not cause you signal integrity problems. Be carefull of the polarity of some of the control signals - some of the various writeups online can imply misleading things. But the various microncontroller projects are good examples for how to initialize the drive (strongly suggest LBA mode).Article: 85236
Lina wrote: > Hi All, > > I used EDK7.1i to do some projects(Microblaze core), in the projects there are many floating point computing, so I want to use FPU in EDK7.1 to speed up. However, there are some mistakes of the results, so I would like to know > > (1)how to use the FPU step by step? Set the C_USE_FPU to 1 for MicroBlaze, either directly in the .mhs file or using the GUI under "add/edit cores" button in XPS. The compiler will start to use the new FPU instructions due to this parameter setting. > > (2)should I have to set some parameters in order to use FPU? See above > > (3)should I add #include "stdlib.h" #include "math.h" .... or other .h files in my programmes to do the floating point? yes. That is how the C language is doing it. > > Thank you! > > Lina GöranArticle: 85237
Could u please suggest me the Xilinx FPGA device I/O pin with around 150mA current sink/source capability. what is the name of this specification in the FPGA documents.Article: 85238
In comp.arch.embedded Eric <ericjohnholland@hotmail.com> wrote: > What is the best FREE Schematic & PCB Layout software available that > will run on Windoze XP? > Have you considered TinyCAD and FreePCB? Both open source and free. -- Wing Wong.Article: 85239
I'd keep an eye on MOL or Mac on Linux. It allows any PPC box (Apple or otherwise) that runs a PPC Linux to run OSX in a window with little loss in perf. Now moving the open source MOL back to x86 with std out of the box OSX with x86 code would allow any x86 Linux box to do the same. I think pandoras box just got opened, not sure if Apple can close it. johnjakson at usa dot comArticle: 85240
Hello, I'm using a Virtex-II Pro with 1 PowerPC 405. All worked very well until the moment I had to add big FIR filters (2 D.A. with 85 taps and 2 MAC with 17 taps). Now, at any time, the programm stop: the FPGA part continue to work but the PPC part doesn't work anymore. The only solution to continue is to reset the board. Is it because the number of slices occupied grow up from 48 % to more than 75 % and it's to big for the PPC? Does someone have find the same problem ? My configuration: PPC @ 300 MHz 16ko ISOCM (for PPC instructions) 16ko PLB BRAM (for PPC data) 32 ko DOCM BRAM (use as dual port between "PPC part" and "FPGA part") FPGA with external clock at 60 MHz (multiply by 2 with DCM) Thank you for our help. PierreArticle: 85241
"David Brown" <david@westcontrol.removethisbit.com> wrote in message news:d81lte$c4g$1@news.netpower.no... > Piotr Wyderski wrote: >> David Brown wrote: >> >>> You want a "free and efficient" cpu, yet you want a Windows port for >>> it?? >> >> >> Yes. :-) Thanks to MS Academic Alliance it is possible. Of course >> the device will not be produced (i.e. there will exist a single specimen >> of it, used by myself). >> >> Best regards >> Piotr Wyderski >> > > If you are an academic, I believe Altera have special prices and deals for > academic use. I have no idea of the details, but it's worth checking out. > Of course, that doesn't get you any nearer wince on an FPGA - but I > personally wouldn't consider using wince for anything but a PDA, even if > it were completely free of cost. If you really do try to port wince to an > opencores cpu, you are going to have a big job on your hands - while some > of the opencores cpus have good toolsets, they are almost exclusively > gcc-based, and aimed at either no OS at all, or open source OS's. Trying > to get wince working will be "educational", however, which is perhaps your > aim here. The university programs are great. We only currently use xilinx (not my decision). I believe there is a port of wince for excalibur (Altera fpga with arm hardcore) was done by one of the Singaporean Universities. There was a paper on it at a Programmable Logic conference - FPT2004 in December 2004, at UQ in Brisbane Australia. Should be available via IEEE. Alex GibsonArticle: 85242
We have 15pcs XC3S200-4VQ100C, date-code 0441, sealed package, never opened, that we can sell. If someone is interested, just send me an e-mail (we have switched the project to S3E, so we have no longer a need for them...). Thomas Entner www.entner-electronics.com "Uwe Bonnes" <bon@elektron.ikp.physik.tu-darmstadt.de> schrieb im Newsbeitrag news:d82m9v$f12$3@lnx107.hrz.tu-darmstadt.de... > Peter Alfke <peter@xilinx.com> wrote: >> Frederic, >> We have plenty of XC3S200, but how can we halp you when you give >> neither your name nor your company affiliation. Being "pissed off" is >> no good when you give us no chance to help you. > > Peter, > > go to www.nuhorizons.com , search for XC3S and let only available device > get > listed. You'll get horrified... > > Why does .www.xilinx.com only sell CPLDs? > > -- > Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 85243
Hello, I'm trying to generate a divider core with Xilinx core generator. I'm confused about the signed/unsigned option, and it seems that ther's a mistake in the datasheet of the core. dtatsheet : http://www.xilinx.com/ipcenter/catalog/logicore/docs/sdivider.pdf At the end of the first page, -9/4 is translated in binary in a strange way. First, 9 is 1001 in unsigned, but -9 doesn't exist in signd binary as far as I can remember.... in the datasheet : -9/4=9/-4=-(2 1/4) this corresponds to : (1)0111/0100 or 1001/1100 isn't that wrong ? thanksArticle: 85244
"vinch" <vincesusu@yahoo-dot-fr.no-spam.invalid> wrote in message
news:KvednQrWrplsyjjfRVn_vg@giganews.com...
> At the end of the first page, -9/4 is translated in binary in a
> strange way.
> First, 9 is 1001 in unsigned, but -9 doesn't exist in signd binary as
> far as I can remember....
> in the datasheet :
> -9/4=9/-4=-(2 1/4)
> this corresponds to :
> (1)0111/0100 or 1001/1100
> isn't that wrong ?
Well, 10111 would be -9 in 5-bit binary, so it depends what you mean by
"wrong". "Sloppy" might be a better word. I think it's a red herring though.
The point it's illustrating is that if the result of a signed division is
negative, the quotient will always be negative (or zero). However, if you
choose an *integer* remainder then it may differ in sign from the quotient;
if you choose a *fractional* remainder then it will always have the same
sign as the quotient.
Cheers,
-Ben-
Article: 85245Sorry, they are already sold now... "Thomas Entner" <aon.912710880@aon.at> schrieb im Newsbeitrag news:42a556ed$0$30428$91cee783@newsreader01.highway.telekom.at... > We have 15pcs XC3S200-4VQ100C, date-code 0441, sealed package, never > opened, that we can sell. If someone is interested, just send me an e-mail > (we have switched the project to S3E, so we have no longer a need for > them...). > > Thomas Entner > > www.entner-electronics.com > > > "Uwe Bonnes" <bon@elektron.ikp.physik.tu-darmstadt.de> schrieb im > Newsbeitrag news:d82m9v$f12$3@lnx107.hrz.tu-darmstadt.de... >> Peter Alfke <peter@xilinx.com> wrote: >>> Frederic, >>> We have plenty of XC3S200, but how can we halp you when you give >>> neither your name nor your company affiliation. Being "pissed off" is >>> no good when you give us no chance to help you. >> >> Peter, >> >> go to www.nuhorizons.com , search for XC3S and let only available device >> get >> listed. You'll get horrified... >> >> Why does .www.xilinx.com only sell CPLDs? >> >> -- >> Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de >> >> Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt >> --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- > >Article: 85246
Hi Ray Andraka Thank you for your reply. Now I was writing my own FIR with Multipler and adder units....I could complete it in a day, but i just wrote plain VHDL using some arrays to store the filter state. so it takes lots of slices. Now i am trying to put in dual port ram. am trying to fit the design in my FPGA spartan-3 (50K device the lowest available) of which i am already using 68 % of the slices.. I have already 2 FIR filter running in my FPGA, this is the 3rd Filter which need to be adaptive one. But you were telling about adaptive filter core , but it is not available in my coregen. i am using ISE 6.3. in which version of ISE adaptive filter is available. Thanks a lot for your reply... regards bijoyArticle: 85247
That's a great shame. Unfortunately I need the pins! so was going for the PQ208 package. "Thomas Entner" <aon.912710880@aon.at> wrote in message news:42a556ed$0$30428$91cee783@newsreader01.highway.telekom.at... > We have 15pcs XC3S200-4VQ100C, date-code 0441, sealed package, never > opened, that we can sell. If someone is interested, just send me an e-mail > (we have switched the project to S3E, so we have no longer a need for > them...). > > Thomas Entner > > www.entner-electronics.com > > > "Uwe Bonnes" <bon@elektron.ikp.physik.tu-darmstadt.de> schrieb im > Newsbeitrag news:d82m9v$f12$3@lnx107.hrz.tu-darmstadt.de... >> Peter Alfke <peter@xilinx.com> wrote: >>> Frederic, >>> We have plenty of XC3S200, but how can we halp you when you give >>> neither your name nor your company affiliation. Being "pissed off" is >>> no good when you give us no chance to help you. >> >> Peter, >> >> go to www.nuhorizons.com , search for XC3S and let only available device >> get >> listed. You'll get horrified... >> >> Why does .www.xilinx.com only sell CPLDs? >> >> -- >> Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de >> >> Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt >> --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- > >Article: 85248
I think the speed of your sale suggests emphasises they're more like rocking horse droppings. "Thomas Entner" <aon.912710880@aon.at> wrote in message news:42a566c0$0$13522$91cee783@newsreader01.highway.telekom.at... > Sorry, they are already sold now... > > "Thomas Entner" <aon.912710880@aon.at> schrieb im Newsbeitrag > news:42a556ed$0$30428$91cee783@newsreader01.highway.telekom.at... >> We have 15pcs XC3S200-4VQ100C, date-code 0441, sealed package, never >> opened, that we can sell. If someone is interested, just send me an >> e-mail (we have switched the project to S3E, so we have no longer a need >> for them...). >> >> Thomas Entner >> >> www.entner-electronics.com >> >> >> "Uwe Bonnes" <bon@elektron.ikp.physik.tu-darmstadt.de> schrieb im >> Newsbeitrag news:d82m9v$f12$3@lnx107.hrz.tu-darmstadt.de... >>> Peter Alfke <peter@xilinx.com> wrote: >>>> Frederic, >>>> We have plenty of XC3S200, but how can we halp you when you give >>>> neither your name nor your company affiliation. Being "pissed off" is >>>> no good when you give us no chance to help you. >>> >>> Peter, >>> >>> go to www.nuhorizons.com , search for XC3S and let only available device >>> get >>> listed. You'll get horrified... >>> >>> Why does .www.xilinx.com only sell CPLDs? >>> >>> -- >>> Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de >>> >>> Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt >>> --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- >> >> > >Article: 85249
"Fred" <Fred@nospam.com> wrote in message news:42a56b34$0$23915$db0fefd9@news.zen.co.uk... >I think the speed of your sale suggests emphasises they're more like >rocking horse droppings. I bought them immediately, not because I might have trouble getting them (I haven't checked with Memec) but because Thomas was selling them cheaper than I can get them for, and it's less trouble than dealing with Memec. I don't have an account with them, which always seems to cause problems. Leon
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