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what package do you need? Antti "Fred" <Fred@nospam.com> schrieb im Newsbeitrag news:42a4814e$0$2594$da0feed9@news.zen.co.uk... > 14 week lead time for samples for the XC3S200. How can you prototype with > that? > > It makes worry even more when it comes to manufacture where I might need > quantity. > >Article: 85176
I generally agree with your input Peter: power consumption is increasingly important, good estimation tools are critical, and advanced design methodologies are helpful. The relentless attacks on Altera would be more interesting if they better aligned with reality. Those customers interested in optimal power estimation accuracy will find compelling advantages with Quartus II support for Stratix II. Previous post (from Austin) highlighted accuracy of Xilinx estimation tool at +/- 50% - our correlation analysis indicates that this "accuracy" rating is exceedingly generous. Quartus II estimation tools provide accuracy +/- 20%. I'll assume someone is thinking (as I agree again with Peter's assertion that Xilinx has been consistent in their messaging): if Xilinx says they are 10X better in power, better estimation tools don't really matter. Reality is that Virtex 4 static power is a little lower than Stratix II static power and Stratix II dynamic power is a little lower than Virtex 4 dynamic power. And both Altera and Xilinx can identify plenty of "ideal" design examples that make our respective parts look great and our competitor's parts look terrible. Design dependency becomes the limiting factor, and this of course is where tool estimation accuracy can be a critical factor. If static power is really the limiting concern, then it is unlikely that Stratix II or Virtex 4 will be the ideal solution. Low-cost (albiet lower performing) FPGAs provide the lowest static power. Cyclone II has the lowest dynamic power of any FPGA and the lowest static power of any 90 nm FPGA, resulting in the lowest total power seen by an FPGA of this density. Dave Greenfield Altera Marketing Peter Alfke wrote: > I see three distinctly different purposes for a pre-design power > analysis: > 1. You want to estimate battery life and required battery size, cost, > and weight. > 2. You want to install the appropriate Vcc regulators, definitely not > too small. > 3. You want to estimate thermal conditions, especially junction > temperature. > > #3 is the toughest, since it allows the least margin. > If you have to design for 50 degr C ambient, and want to keep the > junction temperature under the specified 85 degrees C, you are walking > a fine line. Without a heatsink, you never get below 10 degrees/W, > which means 3.5 W is your max limit. > With a good heatsink and plenty of airflow, you can tolerate far more > power, but with modern high-performance circuits you will always be > close to the edge. Which means you estimator has to be accurate. > An answer of "somewhere between 5 and 10 W" does'nt help you much, and > "somewhere between 10 and 20 W" is even worse. > Power consumption is a very important issue. You should forgive us for > our relentless attacks on our competitor Altera. In many cases, the > part with the guaranteed lower power consumption wins, and it is > worthwile to explore all the advanced design methodologies in order to > reduce power. > Virtex-4 helps, if you are willing to use its power-saving options, > like DSP slices, FIFOs etc. > Modern FPGAs are not just seas of LUTs that you simply throw VHDL at. > It pays to do some creative thinking and planning, if you want to avoid > the power=heat crunch.. > Peter Alfke, from home.Article: 85177
What i would like to know is how to interface USB1.1 which is
having non-AHB interfacing signals, which is working at fullspeed
(12Mhz) with ARM processor which is operating at 25 MHz usign AMBA 2.0
specification.
--Joe
Mike Lewis wrote:
> dude what information are u looking for? The AMBA spec is readily available
> from ARM website. Whose USB core are u trying to implement? If u are asking
> for doumenation for that ... would you not have received that with the IP ..
> even
> if it was a long time ago.
>
> Does the USB core have an AMBA interface? Or is the interface something else
> that
> you want to modify to connect to an AMBA bus? What is the interface?
>
> We need more detail if we are going to help you.
>
> Mike
Article: 85178But then what do you propose to do with the 33554432 Hz clock? The need was to generate 35.328 MHz +/- a few Hertz in 1 Hz increments from a 35.328 MHz clock. "Vladislav Muravin" <muravinv@advantech.ca> wrote in message news:a__oe.3724$_n2.347454@news20.bellglobal.com... > Bijoy, > > Say you can generate 2^^25 = 33554432 Hz clock in the FPGA (or its double / > quadruple). > This means running NCO with 1 bps resolution is achieved. > > Now, how to do this??? > > 33554432 = 35328000 * (8192/8625) > if you use a dedicated PLL for this fractional synthesys, like ICS307-03, > fine. > > if not, we can do the following: 8192/8625 = (32/25) * (32/23) * (8/15) > > First term is done by DCM > Second term is first division by FFs, then multiplication using DCM's CLKFX > output. > the same for the third one. > > you will have an inevitable jitter as a result of using CLKFX, but i think > this is the best you can have. > > hope this is helpful. > > Vladislav > > > "bijoy" <pbijoy@rediffmail.com> wrote in message > news:ee8ea39.-1@webx.sUN8CHnE... > > Hi I am using Spartan-3 fpga > > > > I need to generate 35.328 MHz clock > > > > I have an external xtal of 35.328 MHz feeding to FPGA. > > > > From this clock i need to generate 35.328 MHz square wave with fine > > resolution. > > > > We need a resolution of 1Hz, that means i should be able to change the > > square wave out put frequency by 1 Hz resolution. > > > > I tried to generate this by using DDS core provided by core-generator and > > taking the MSBit of the sine wave samples given by the DDS. But the > > spurious components generated using this method is too much for my > > application to accept. > > > > Is there any-other way out ? > > > > ( This is for ADSL Modem appliaction. we currently use DDS provided by > > Analog devices. > > > > So i thought of using FPGA for this purpose as an alternative solution. ) > > > > Thanks bijoy > >Article: 85179
http://www.apple.com/pr/library/2005/jun/06intel.html Apple at to switch to using Intel procesors, presumably x86, for Macs. Perhaps a light is in sight for the groups reccouring question of 'EDA tools on OS X?' Even if the FPGA tool vendors still chose not to port their tools to the Mac, x86 linux should run at near full speed under ~virtualisation, much like User Mode Linux. Might be a PITA to setup, but... Here's hoping... --- cdsArticle: 85180
Why is this the case even when a single Aurora transmitter or a single receiver is chosen? This seems to be wasting precious resources... How can I utilize all the available GT11 blocks? Thanks, /MikhailArticle: 85181
Don't hold your breath. When I think EDA, I think Sun, HP, Linux and to a lesser extent Windows NT/2K/XP. It would be cool, but no. As far as x86 Linux apps on OS X, I wouldn't even bother. If you can get a Intel based Mac, you can get a cheaper Linux box. -Chris c d saunter wrote: > http://www.apple.com/pr/library/2005/jun/06intel.html > > Apple at to switch to using Intel procesors, presumably x86, for Macs. > > Perhaps a light is in sight for the groups reccouring question of 'EDA > tools on OS X?' > > Even if the FPGA tool vendors still chose not to port their tools to the > Mac, x86 linux should run at near full speed under ~virtualisation, much > like User Mode Linux. Might be a PITA to setup, but... > > Here's hoping... > --- > > cdsArticle: 85182
I had a question about the latest happening in this market. Since I am new in this area excuse me in advance if the question sounds stupid.(:-. What is trend for programming devices now a days. I mean are people using VHDL/Verilog more and more for design or they use design tools such as Orcad etc. What is better off the two. What are the pro/cons of using VHDL/Verilog in comparision to schematic capture. ThanksArticle: 85183
Hi, I need to double an input clk of 13.5mhz to 27 mhz...but the DCM core in xilinx can take frequencies from 24 Mhz and up only... On going through some of the posts, this is the idea that I have come across: Give my input clk to one input of the XOR gate. Delay my input clk with a series of inverters and give it as the second input of the XOR gate.. Would this work? Thank you, MethiArticle: 85184
-- Per rispondermi via email sostituisci il risultato dell'operazione (in lettere) dall'indirizzoArticle: 85185
kempaj@yahoo.com wrote:
> David is correct -- Piotr if you are in any way involved with an
> academic institution
Yes, I am, the institution is the university of Wroclaw,
the faculty of computer science (I'm a Ph. D. student).
> please visit the Altera University website...
I will check it, thanks. BTW, we are looking for
a small number of cheap Cyclone boards for an
experimental course of FPGA programming and
it seems that you have an appropriate model
The second option is to purchase similar kits from
Xilinx, but I think that Altera will be the winner
because we are much more familiar with Quartus
compared to ISE. But we don't need CPU IP cores.
> As far as whether Nios II is free: I would contend, that for the
> hobbyist all you need is a board
The problem is that I (this time as a hobbyist) don't use
development boards -- I buy raw Cyclone chips and mount
them directly on their destination PCBs. And since the device
should be portable (it's a high-performance software radio
transceiver + a PDA), the free NIOS2 evaluation kit is not
enough.
> The downloadable evaluation core provides complete functionality of
> Nios II and all peripherals provided that you maintain a JTAG link to
> your host PC (tethered mode).
And that's the problem: I can't maintain a permanent JTAG link,
because the device is designed to be portable (the FPGA chip
will be configured via PS mode by an external MCU; its configuration
images, among other things, are stored on a CompactFlash card).
> I personally think this is quite generous considering
> the amount of development that has gone into the product over the past
> 5+ years, and the amount of interesting things one can do with the
> product while connected via JTAG cable.
I agree, but I would like to have a working amateur device, so
there are only two possibilities: use a free, full-featured NIOS
(which doesn't exist) or do not use NIOS at all...
Best regards
Piotr Wyderski
Article: 85186
David Brown wrote:
> If you are an academic, I believe Altera have special prices and deals
> for academic use.
Well, I am, but I don't want to abuse it, it will be unfair.
> but I personally wouldn't consider using wince for anything but a
> PDA, even if it were completely free of cost.
Why?
> If you really do try to port wince to an opencores cpu,
> you are going to have a big job on your hands
The complexity is not a problem, I do it in my spare time.
It could take even several months, doesn't matter...
Best regards
Piotr Wyderski
Article: 85187"methi" <gmethi@gmail.com> wrote in message news:1118085861.383732.169030@g14g2000cwa.googlegroups.com... > Hi, > > I need to double an input clk of 13.5mhz to 27 mhz...but the DCM core > in xilinx can take frequencies from 24 Mhz and up only... > > On going through some of the posts, this is the idea that I have come > across: > > Give my input clk to one input of the XOR gate. > > Delay my input clk with a series of inverters and give it as the second > input of the XOR gate.. > > Would this work? > > Thank you, > > Methi > Best way is PLL, but if not .... Clock into one side of XOR. Output of XOR clocks D-type. Q of D type thru inverter to D and other input of XOR. Take doubled clock out of XOR output. Bit naff but works. ChuckArticle: 85188
On 6 Jun 2005 13:26:56 -0700, "Eric" <ericjohnholland@hotmail.com> wrote: >What is the best FREE Schematic & PCB Layout software available that >will run on Windoze XP? > >I've looked at PCB123.com and Expresspcb.com and they have pretty good >programs available. Unfortunately if I use either one I'm stuck getting >the prototypes through them. (Because they won't output Gerbers) > >I've also looked at Eagle Layout at cadsoft.de, but the size limitation >of 100 x 80mm on the free version is a negative. It would work for my >current project. > >I'm just curious at what other people's opinions are. My opinion is that you ask for an awful lot for free. What do you do for a living? Would you mind terribly much doing that for free? -MithrandirArticle: 85189
chrisbw@gmail.com wrote: > Don't hold your breath. When I think EDA, I think Sun, HP, Linux and to > a lesser extent Windows NT/2K/XP. > It would be cool, but no. > As far as x86 Linux apps on OS X, I wouldn't even bother. If you can > get a Intel based Mac, you can get a cheaper Linux box. > Wasn't the whole point of moving to OS-X to run on a G5 processor?Article: 85190
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Article: 85191Jim George wrote: > Sean Durkin wrote: > > Hi *, > > > > I keep coming across answer records and script files containing the > > setting of undocumented environment variables, such as > > XIL_ROUTE_ENABLE_DATA_CAPTURE, XIL_BITGEN_VIRTEX2ES, > > XIL_XST_HIDEMESSAGES and so on. > > > > Is there a complete list of these hidden cheat codes? Any "official" > > documentation at all? > > > > Whenever I'm stuck in a design, and find out that some magical > > environment variable just fixes my problem, I wonder if maybe there is > > something like the Holy Grail... something like the "Answer to Life, the > > Universe and Everything", as in a "XIL_MAKE_EVERYTHING_WORK"- or > > "XIL_42"-variable or something. Haven't found it but thought I could ask. > > > > cu, > > Sean > > > XIL_XST_HIDEMESSAGES is supposed to suppress the warnings that cause my > report files to grow to several tens of thousands of lines long... IT > DOESN'T WORK! > > -Jim I'm using XIL_XST_HIDEMESSAGES with 6.1i and it works fine. You just can't pick which messages it hides. One thing I noticed was that I usually need to add these variables to the user environment because for some reason they are not always picked up by the tools when placed in the system environment. -GaborArticle: 85192
learnfpga@gmail.com wrote: > I had a question about the latest happening in this market. Since I am > new in this area excuse me in advance if the question sounds > stupid.(:-. What is trend for programming devices now a days. I mean > are people using VHDL/Verilog more and more for design or they use > design tools such as Orcad etc. What is better off the two. What are > the pro/cons of using VHDL/Verilog in comparision to schematic capture. IMO, VHDL/Verilog is used by professionals who work moreless fulltime with this stuff. The schematic approach is much easier when you come from the hardware side. What is more and more becoming used is somewhat unnecessay as it involves the sales to occasional users. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 85193
"learnfpga@gmail.com" <learnfpga@gmail.com> ha scritto: >thanks a lot I'm sorry but your email account does not accept attachments (even of small size: 600 kB):Article: 85194
methi wrote: > Hi, > > I need to double an input clk of 13.5mhz to 27 mhz...but the DCM core > in xilinx can take frequencies from 24 Mhz and up only... Only true if you use DLL outputs. For FX-only you can go down to 1.5 MHz IIRC. > > On going through some of the posts, this is the idea that I have come > across: > > Give my input clk to one input of the XOR gate. > > Delay my input clk with a series of inverters and give it as the second > input of the XOR gate.. > > Would this work? Maybe. Is your input duty cycle 50%? Is it still 50% after the IBUF inside the part? Do you need a specific duty cycle on the doubled clock? Can you tolerate jitter on the doubled clock? If your input has exactly 50% duty cycle you can create a relatively low-jitter doubled clock and it could be squared off by adjusting the delay to one leg of the XOR, or if the jitter is low enough by feeding through the DCM. > > Thank you, > > MethiArticle: 85195
Hi Chuck, Thanks for replying.. Did I get this right: Take my 13.5 and give it as one input of an XOR Take the output of the XOR1 and give it as input clk to a D-FF1 Take the output of the D-FF1 and give it as input to an inverter. Take the output of the inverter and give it as input clk to another D-FF2 and also as the second input of the XOR1 And the output of the XOR1 gives 27mhz Am I understanding this right? Thank you, Methi Chuck Bodgers wrote: > "methi" <gmethi@gmail.com> wrote in message > news:1118085861.383732.169030@g14g2000cwa.googlegroups.com... > > Hi, > > > > I need to double an input clk of 13.5mhz to 27 mhz...but the DCM core > > in xilinx can take frequencies from 24 Mhz and up only... > > > > On going through some of the posts, this is the idea that I have come > > across: > > > > Give my input clk to one input of the XOR gate. > > > > Delay my input clk with a series of inverters and give it as the second > > input of the XOR gate.. > > > > Would this work? > > > > Thank you, > > > > Methi > > > > Best way is PLL, but if not .... > > Clock into one side of XOR. Output of XOR clocks D-type. Q of D type thru > inverter to D and other input of XOR. Take doubled clock out of XOR output. > > Bit naff but works. > > ChuckArticle: 85196
Hi Gabor, Thanks fore replying. "For FX-only you can go down to 1.5 MHz IIRC." How do I do this? I mean, how do I make use of the DCM core in Xilinx to take an input clk of 13.5mhz... Thanks, Methi Gabor wrote: > methi wrote: > > Hi, > > > > I need to double an input clk of 13.5mhz to 27 mhz...but the DCM core > > in xilinx can take frequencies from 24 Mhz and up only... > > Only true if you use DLL outputs. For FX-only you can go down > to 1.5 MHz IIRC. > > > > > On going through some of the posts, this is the idea that I have come > > across: > > > > Give my input clk to one input of the XOR gate. > > > > Delay my input clk with a series of inverters and give it as the second > > input of the XOR gate.. > > > > Would this work? > > Maybe. Is your input duty cycle 50%? Is it still 50% after the IBUF > inside the part? Do you need a specific duty cycle on the doubled > clock? Can you tolerate jitter on the doubled clock? > > If your input has exactly 50% duty cycle you can create a relatively > low-jitter doubled clock and it could be squared off by adjusting the > delay to one leg of the XOR, or if the jitter is low enough by feeding > through the DCM. > > > > > Thank you, > > > > MethiArticle: 85197
Gabor wrote: > chrisbw@gmail.com wrote: > > Don't hold your breath. When I think EDA, I think Sun, HP, Linux and to > > a lesser extent Windows NT/2K/XP. > > It would be cool, but no. > > As far as x86 Linux apps on OS X, I wouldn't even bother. If you can > > get a Intel based Mac, you can get a cheaper Linux box. > > > > Wasn't the whole point of moving to OS-X to run on a G5 processor? No. OS X runs on G3s (PowerPC 750) and G4s (PowerPC 74xx) as well. -aArticle: 85198
Dave, For the record, I was referring to the Excel spreadsheet 'accuracy'. Use of the verilog test bench file with the XPower tool results in a far better estimate, given the customer actually has captured what is really happening in their simulation. As for your other claims regarding S2, I respectfully disagree. As for Cyclone II, it may be that you have very low power (static). We also sell the a static power versions called Spartan 3L. But, have you fixed the power on surge problem in Cyclone II? Austin Dave Greenfield wrote: > I generally agree with your input Peter: power consumption is > increasingly important, good estimation tools are critical, and > advanced design methodologies are helpful. The relentless attacks on > Altera would be more interesting if they better aligned with reality. > Those customers interested in optimal power estimation accuracy will > find compelling advantages with Quartus II support for Stratix II. > Previous post (from Austin) highlighted accuracy of Xilinx estimation > tool at +/- 50% - our correlation analysis indicates that this > "accuracy" rating is exceedingly generous. Quartus II estimation tools > provide accuracy +/- 20%. > > I'll assume someone is thinking (as I agree again with Peter's > assertion that Xilinx has been consistent in their messaging): if > Xilinx says they are 10X better in power, better estimation tools don't > really matter. Reality is that Virtex 4 static power is a little lower > than Stratix II static power and Stratix II dynamic power is a little > lower than Virtex 4 dynamic power. And both Altera and Xilinx can > identify plenty of "ideal" design examples that make our respective > parts look great and our competitor's parts look terrible. Design > dependency becomes the limiting factor, and this of course is where > tool estimation accuracy can be a critical factor. > > If static power is really the limiting concern, then it is unlikely > that Stratix II or Virtex 4 will be the ideal solution. Low-cost > (albiet lower performing) FPGAs provide the lowest static power. > Cyclone II has the lowest dynamic power of any FPGA and the lowest > static power of any 90 nm FPGA, resulting in the lowest total power > seen by an FPGA of this density. > > Dave Greenfield > Altera Marketing > > Peter Alfke wrote: > >>I see three distinctly different purposes for a pre-design power >>analysis: >>1. You want to estimate battery life and required battery size, cost, >>and weight. >>2. You want to install the appropriate Vcc regulators, definitely not >>too small. >>3. You want to estimate thermal conditions, especially junction >>temperature. >> >>#3 is the toughest, since it allows the least margin. >>If you have to design for 50 degr C ambient, and want to keep the >>junction temperature under the specified 85 degrees C, you are walking >>a fine line. Without a heatsink, you never get below 10 degrees/W, >>which means 3.5 W is your max limit. >>With a good heatsink and plenty of airflow, you can tolerate far more >>power, but with modern high-performance circuits you will always be >>close to the edge. Which means you estimator has to be accurate. >>An answer of "somewhere between 5 and 10 W" does'nt help you much, and >>"somewhere between 10 and 20 W" is even worse. >>Power consumption is a very important issue. You should forgive us for >>our relentless attacks on our competitor Altera. In many cases, the >>part with the guaranteed lower power consumption wins, and it is >>worthwile to explore all the advanced design methodologies in order to >>reduce power. >>Virtex-4 helps, if you are willing to use its power-saving options, >>like DSP slices, FIFOs etc. >>Modern FPGAs are not just seas of LUTs that you simply throw VHDL at. >>It pays to do some creative thinking and planning, if you want to avoid >>the power=heat crunch.. >>Peter Alfke, from home. > >Article: 85199
What is the best FREE Schematic & PCB Layout software available that will run on Windoze XP? I've looked at PCB123.com and Expresspcb.com and they have pretty good programs available. Unfortunately if I use either one I'm stuck getting the prototypes through them. (Because they won't output Gerbers) I've also looked at Eagle Layout at cadsoft.de, but the size limitation of 100 x 80mm on the free version is a negative. It would work for my current project. I'm just curious at what other people's opinions are. Thanks, Eric
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