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Gabor wrote: > > Peter Alfke wrote: > >>Well. European geography was never a US forte. Confusing Sweden with >>Switzerland is much worse than mixing up Finland and Sweden. Hell, for >>a few hundred years, before Napoleon, those two were actually together. >>In Europe, I have asked people whether they know the difference between >>Michigan and Minnesota, and I got a blank stare... >>Peter Alfke > > > Sorry to push this thread further off topic, but... > > a) Michigan and Minnesota, while as large as many European > countries are not countries, while Finland and Sweden are. > > b) You'd get a lot of blank stares in the US, too. > > c) At least you didn't confuse Sweden and Norway, you could be > shot for that ;-) > When it would have been mentioned somewhere in a newspaper or whatever media I wouldn't had paid much attention.. Just attracted me since in this FPGA book an own chapter is devoted to opensource and Linux EDA software... ...so in this context it's better to make your homework right (o; ...anyway nice weekend rick ps: a .ch living in .fi born somewhere else (o; contact: RK2991-RIPEArticle: 86301
EIA/JEDEC standard JESD8-B -- Greg readgc.invalid@hotmail.com.invalid (Remove the '.invalid' twice to send Email) <kevin@firebolt.com> wrote in message news:1119617508.454530.56070@o13g2000cwo.googlegroups.com... > Quick question: Anyone know who set the LVTTL spec if there is such a > defined spec. As in, IEEE, ANSI, TIA, EIA, etc... Thanks, > > Kevin >Article: 86302
You might also want to look at xapp609 about local clocking resources. Iam planning to write my own core now, instead of trying to fix there core. Would love to hear what speeds you are able to achieve. We would have to hit 150 MHz clock rate so as to fully use the DSP's processing potential. I dont have any idea if 150 MHz is pushing the limits of local clocking resources or not? Brijesh James Morrison wrote: > On Thu, 2005-06-23 at 15:43 -0400, Brijesh wrote: > >>Hello, >> >>Started to look at the xapp635 to implement link port interface in Virtex II >>device. I ran a simulation (VHDL version) with the test bench that came with the >>app note and it did not pass the test. There is a bug in the receiver >>implementation. It fails at the very first reception. >> > > > <snip> > >>Fixing the bug is going to be a pain as there are no comments what so ever in >>the code. Looks like they intentionally stripped all the comments before >>releasing the code. Wondering if its better to write my own receiver based on >>the same technique rather than trying to fix this one. > > > I ran into the same thing although I'm only looking at a 1-bit > implementation. The _complete_ lack of comments in the VHDL is crazy. > Given the fact that it is meant as a design starting point I would have > imagined it to be about 90% comments to explain why things were done and > other options that are possible. The description in the PDF, while it > helps, is no replacement for inline comments. > > I just started working on my implementation so I can't really give any > more guidance at this point. I found XAPP265 to be more useful than the > two TigerSharc related app notes. The only exception is that the > receiver clock is not continuous so you can't take it into a DCM. > > James. >Article: 86303
John McCaskill wrote: > I have not used Xapp635, but I have use the Verilog link port design > that is in Xapp634, and it works for me. I am using it to comunicate > between Virtex-II FPGAs, and not with a TigerSHARC. Maybe it is worth > a look. I did take look at them. Looks like the new TigerSharc interface is reduced functionality version of the old interface. They seem to have removed the crc verification function and hand placed and routed the whole thing to get better clock rates. Thats the first impression I got. By the what kind of clock rates were you able to get out of it? Did you get the published max throughputs? thanks BrijeshArticle: 86304
Apply it eight times before clocking; the tools will do the rest. I'm not familiar with exactly the way you wrote your equation, but whatever you mean by it, apply it eight times to get your "byte" result. Jason "Kris Neot" <Kris.Neot@hotmail.com> wrote in message news:42bb65e4@news.starhub.net.sg... > My polynomial is S(x) = x(-7) + x(04) + 1, but my input data is one byte > each clock period. What are the equations to inplement this data > scrambler? > > > Thanks. > > >Article: 86305
Hi all, I'm doing a project on "VHDL implementation of LOG CFAR". I need somebody to enumerate the differences FPGA vs. ASIC and FPGA vs. Processor. I dont have much idea on ASIC and am still learning about FPGA. ThanxArticle: 86306
??? If "you" are doing this project, why don't "you" do some research? AustinArticle: 86307
see this thread http://groups-beta.google.com/group/comp.arch.fpga/browse_frm/thread/82209d609e4cf911/d523168b8e75d405?q=eric+cpu&rnum=1&hl=en#d523168b8e75d405Article: 86308
Brijesh wrote: > John McCaskill wrote: > > > I have not used Xapp635, but I have use the Verilog link port design > > that is in Xapp634, and it works for me. I am using it to comunicate > > between Virtex-II FPGAs, and not with a TigerSHARC. Maybe it is worth > > a look. > > I did take look at them. Looks like the new TigerSharc interface is reduced > functionality version of the old interface. They seem to have removed the crc > verification function and hand placed and routed the whole thing to get better > clock rates. Thats the first impression I got. > > By the what kind of clock rates were you able to get out of it? Did you get the > published max throughputs? > > thanks > Brijesh We currently have the system clock input constrained to 100 MHz. The lxclkin and lxclkout clocks would be 50 MHz, or upto 100MB/sec. This is more than fast enough for what we are using it for, so I have not tried to see how fast it will go. We are using V2 -5C speed grade. We have had it running faster in the past, but I would have to go digging through our CVS repository to see how fast. If memory serves, I think we had it running with a main clock of 125 MHz. Regards, John McCaskillArticle: 86309
Hi, I switch to single port block memory core, this time ModelSim works for given init files (X.mif). I believe it is Coregen issue. Hope Xilinx have fix in 7.1's SP3. AlphaArticle: 86310
Hi all, Xilinx has announced support for DDR2 up to 533 MHz. Are there any physical limitations that won't allow higher frequencies to be used? -FernandoArticle: 86311
"Eric Smith" <eric@brouhaha.com> wrote in message news:qhaclgn1s6.fsf@ruckus.brouhaha.com... > Can anyone in the know comment on what the likely order of > availability of Spartan-3e parts (in sub-1000 piece quantities, > not zillions) will be? I'm hoping that the 3S500E in the > chipscale BGA will be one of the first; I've been waiting for > a high-density FPGA in a tiny package. It's a shame that none > of the Spartan-3 parts larger than the 3S50 are available in > that package. > > Thanks, > Eric Hi Mr. Smith, The 3S500E in the CP132 package will be sampling to the general customer base by mid- to end-July 2005. The reason that the higher density CP132 devices are Spartan-3E instead of Spartan-3 is that Spartan-3E delivers more gates at a lower price in that footprint. --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/-3E FPGAs http://www.xilinx.com/spartan3e --------------------------------- The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs.Article: 86312
Hello everyone,
I have generally been using the xilinx CoreGenerator for some
specified components. My query is , can i generate models which uses
generics and these generics will be available only in the design and
keep varying everytime because of the settings made in the settings
file for the design.
Thanks in advance...
Regards,
J.Anil Kumar.
Article: 86313Hi, What is a state of unused pins in SpartanII device? Is this high impedance state? Best Regards Krzysztof PrzednowekArticle: 86314
Jan Panteltje wrote: > On a sunny day (Fri, 24 Jun 2005 09:35:03 +0000 (UTC)) it happened Uwe Bonnes <snip> >>Configuration devices in the webshop would be appreciated! > > I would rather have these in the FPGA itself, as flash. > 1) better security > 2) saves on chip costs > 3) saves on PCB cost > 4) saves work on power up stuff > 5) saves time > 6) saves shipping cost > 7) saves on PCB space > 8) and if you use a 739 pin connector like AMD processors, then you can just > send customers an upgrade, they send old one back for re-programming. > 9) more reliable > 10) faster power up > .. > 99999) less power? > beep you missed 0) Drops performance. There are a ton of reasons why FPGA+Flash on the same die is a compromise, but if we step back a little, and look at other industries the FPGA sector can learn a few things. If you see the latest AMD/Intel etc devices, they include many power supply decouplers - so they are more correctly modules, than silicon chips. Doing that becomes a packaging question, not a die FAB trade off. FPGA vendors _could_ do that, relatively easily - but could it be that the Config costs then become more visible, and the low 2006 price claims are harder to make ? Stacked die are also moving into the mainstream, and they are now eliminating the old bonding wires. See http://www.tezzaron.com/OtherICs/Super_8051.htm This seems to offer a serious speed advantage, as you do not need all the pin resource overhead, and PCB trace overhead. PINS have to have ESD ratings, and large fets to drive many pF of load, a well as the inevitable multiple driver options. Often this load-power dominates over the node-power in the device. Chuck all that overboard so your connection is die-die, and optimised for just what it needs to do, and you can see the advantage. Imagine a stacked die FPGA, with a large VFast SRAM, and Config device ? -jgArticle: 86315
The unused pins can be high impedance, but the actual state depends on the configuration options when you build the .bit file. The default is weak pull-down. If you're using ISE, right click on "Generate Programming File" in the process view and select "properties". In the Configuration Options tab you'll find "Unused IOB Pins" where you can select pullup, pulldown or float (high Z). The state of IOB pins during configuration is determined by the mode pins on Spartan II. You have the choice of high Z or pullup. While the pullup or pulldown is referred to as "weak" in the documents, it's been my experience that it is stong enough to affect connected nets, especially where you have other devices with "weak" pullup or pulldown. For example many chips have dual purpose pins that double as configuration during reset and have internal pullup or pulldown for the default strapping value. The "weak" pullup/pulldown in Spartan II is often strong enough to overcome these internal pullup or pulldowns and change the default configuration options. For nets like this you need to consider both the post configuration options in ISE and the mode selects for pre-configuration. Also be aware that "Unused" refers to the post map IOB list which may have some extra unused pins due to stripped out logic. Krzysztof Przednowek wrote: > Hi, > What is a state of unused pins in SpartanII device? Is this high > impedance state? > > Best Regards > Krzysztof PrzednowekArticle: 86316
Bo wrote: > For what it's worth..we were told by visiting Xilinx engineer to NOT upgrade > our tools to 7.x but instead wait for 8.1 release in August... I was told the same thing. We ran into a problem with timing driven map in 7.1 which made our design impossible to implement. 6.3 works well. They have it fixed in 8.1 (it implemented nicely with 8.1) but it won't be fixed in 7.1 sp3. We were told to skip 7.1 unless we need it for S3E or possibly V4. Jason Daughenbaugh http://www.advanced.proArticle: 86317
Hallo, I'm trying to create a memory controller based on a state machine to send to Microbalze signals like ram_data_out, read_acknowledge, write_acknowledge, etc... I have connected it to OPB Bus. My trouble is that I don't have a clear idea of the steps to read, write, read_acknowledge, write_acknowledge, etc... In example: when microblaze must read data: States: 0 -> 1) enable RAM 1 -> 2) assign address that comes from bus to ram address and assign ram_data_out to bus_data 2 -> 3) read_acknowledge = 1 3 -> 0) disable ram Is it correct? Where I could find a good documentation about it? Many Thanks MarcoArticle: 86318
Kris Neot wrote: > My polynomial is S(x) = x(-7) + x(04) + 1, but my input data is one byte > each clock period. What are the equations to inplement this data scrambler? > > > Thanks. You may have to create a look-up table (LUT) that contains various "S" values for different "x" inputs. An LUT is kind of like ROM where you would use your "x" input as the address. These "S" values are easily computed using Excel or an open-source equivalent spreadsheet program. Also the previous suggestion of performing a multiplication operation several times per cycle is a pretty good idea but it eats up resources or time: m = 1/x n = m * m * m * m * m * m * m o = x * x * x * x S(x) = n + o + 1 "m" will use up multiplication logic (to create the divider) "n" will use up the logic needed for 7 multipliers. *OR* If you adjust your data so that "n" is 8 bits wide then you can use a single multiplier that is 56-bits wide (7*8) but it will take 7 cycles to complete the operation. I recommend using the LUT technique. Best Regards -DerekArticle: 86319
And, you can check your result against the web-tool output at http://www.easics.com/webtools/crctoolArticle: 86320
Vladislav Muravin wrote: > Hello all, > > I am having a strange thing happening. > This was not urgent, so i kinda did not post it previously... > > I have a design synthesized for XC2V2000-FG686-4 or XC2V3000-FG686-4 > > (one) When running the entire ISE flow, everything is smooth, the PROM files > are generated > using two devices 1804v, one 100% full and another 65% full. FPGA is fully > functional and everything is working. > > (two) When running the same using command line, i get that PROM files are > generated > using two devices 1804v, one 100% full and another 62% full. When > programming FPGA with this configuration, > nothing is working. the LEDs which blink once a second per different clock > domains are "dead"... > > I have noticed this with both ISE 6.3 and 7.1 > > The question is what the hell is happening here? I just spent some time today building a Makefile for one of my chips. When I got to promgen, I got a complaint that my design wouldn't fit into the chosen PROM! Turns out that I told it the wrong part type in one of the scripts. I ended up running the whole process in ISE and checking the command lines for each pieces and compared that to what my Makefile was calling out. -aArticle: 86321
Peter Alfke (alfke@sbcglobal.net) wrote: : What's so great about a 30-year old CPU ? : Peter Alfke 0x10 DJNZ 0xD9 EXX The epitomie of CISC, but it illustrates very well why I like the z80 instrucion set - it's simple enough to work in hardware that was around before my time, but it represents a 'good fit' with the way my brain works. --- cds C9'ingArticle: 86322
In EDK, if you browse the install software directory for the opb libraries, you can possibly use the bram_controller.vhd for your application. You just have connect the bram_controller to the IPIF signals and set up the read and write enable lines i.e. bus2ip_arcs(0) & bus2ip_rnw for the read enable and the same for the write enable but with not(bus2ip_rnw). Within the BRAM_controller, a dual-port RAM is instantiated and the control is all setup correctly. Paul Marco wrote: > Many Thanks > Marco > > > "Frank van Eijkelenburg" <someone@work.com> wrote in message > news:d477a$42a86ba6$3e3aa7a5$12385@news.versatel.net... > > > > "Marco" <marcotoschi_no_spam@email.it> wrote in message > > news:d89oml$j4e$1@news.ngi.it... > >> Hallo, > >> I have created a user logic template for obp bus with Create/Import > >> Wizard of EDK with the feature: user logic address range support. > >> > >> Into file user_logic.vhd I have created a Dual port ram with core > >> generator to replace the ram example. > >> > >> Is it possible to map port B of dual port ram into microblaze address > >> space? > > > > Yes, connect the address bits of the opb bus to your bram port. Make a > > state machine which steers the enable and write_enable and the acknowledge > > to the opb bus. > > > >> > >> In this way I could use a C pointer that points to microblaze mapped > >> address space. > > > > Yes you can. > > > >> > >> Otherwise the only way to access it is to use Xio_in and Xio_out ? > > > > AFAIK, you should always be able to access your custom device by using > > pointers > > > >> > >> Many Thanks in advance to everyone > >> Marco > >> > >> Sorry for my bad english > >> > > > >Article: 86323
I just added a answer to your original thread with the dual-port RAM. Try using the bram_controller block within the opb libraries. You just have connect the IPIF signals to it and generate the read and write enables. PaulArticle: 86324
c d saunter writes about the Z-80: > The epitomie of CISC, Not even close. The VAX is a commonly cited example of a CISC, but there are machines with much more complex instruction sets than it has. The Z-80 isn't even in the same league.
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