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> Note : the sensitivity list is incorrect : rst should be removed. I know i have already corrected > Are you sure you want/need to load an input or a register during a reset ? > Can you explain why you need mixing both and what functionality it allows > that not mixing would prevent ? No in fact I don't really need to load during a reset , it's just because i wanted to reset my uart and loading the ctrl_word only by pushing one button > > Mixing both sync and async reset may (according to the FPGA technology and > whether your reset will use a global or not) not be a good idea. > Synchronous reset means reset will be part of your datapath. It may then > add a logic level which isn't always welcome. You may also prevent some > tools from dissolve your global reset if you don't use it. And you force > static timing into analyzing your reset within fmax/Tsu/Th... > It 's only what I wanted to know => if it is a problem to do that or not (indeed I already implemented my design and it's work fine) but I wanted to know if it's could be considerated or not as clean code because use a rst as a simple signal could look like a bit strange > > btw : the divider decoding might be expressed in a simpler way. > Like in this example (dtmf coder): > > ------ > -- Fclock is a generic parameter = 60E6 for Tornado > constant fDiv_Max : natural := Fclock/(697*64)-1; > subtype IntDiv_t is integer range 0 to fDiv_Max; > type Ftable_t is array (0 to 3) of IntDiv_t; > constant F1table : Ftable_t > := ( Fclock/(697*64)-1, Fclock/(770*64)-1, > Fclock/(852*64)-1, Fclock/(941*64)-1 ); > signal Div1 : IntDiv_t; > signal or input Fsel : std_logic_vector (1 downto 0); > .../... > the decoder is then simply : > Div1 <= F1table(to_integer(unsigned(Fsel))); > which you may register or not, reset or not, load or not etc.... > .../... > > Using "integer range" for divisors gets rid of the log2 annoyance and > corner cases (it says you need two bits to divide by 2...) and you have > either to use math_real (not always supported at synthesis) or a custom > function. 0 is also faster to write than (others=>'0'), and it means less > cumbersome conversions and type conversions. > You must verify that your design rules accept integer ranges (I know some > disallow them, but mines don't). > Obviously, this also means you should have the freq div in the same module > as the UART core to benefit from the integer range (they are ruled out in > ports). But that brings another debated issue of partitioning > granularity.... Using a table constant look an interesting issue but would it really make a different (and better) hardware??or is it just a simplest way of writing my decoder?? And as you notice my freq div is in an another module so there is the problem of outport > > Hope this helps, Thank you , it always help still i am yet newbie in fpga world AlexisArticle: 81551
Is there a way to make a global reset on startup of fpga?? Thanks AlexisArticle: 81552
"Jaime Andrés Aranguren Cardona" <jaime.aranguren@gmail.com> wrote in message news:1111808961.860636.147300@z14g2000cwz.googlegroups.com... > Hi, > > Subroto Datta wrote: >> Hi Big, >> >> We'd like to hear your view about how Quartus can be made better > for >> your needs. > > Remove the 150 day restriction for the web edition. make it time > unlimited as the ISE WebPack. > > This is the main factor for me to use Xilinx instead of Altera. And I > am sure that for many more too. > > It is prefereable that it does not work for high-end FPGAs, CPLDs or > Structured ASICs, and only for low/mid range devices, but works > unlimited in time. > > JaaC Problem ? Just request another license like the rest of us. If your lucky you get it same day and keep going as before (even though last time it took a couple of days) I wish Altera would do service packs, instead of having to download the whole thing for the web edtion. But thats my biggest annoyance with xilinx webpack and ise. The stupidly sized service packs. Download 200MB one day then few days later need to download another 300MB for the service pack. AlexArticle: 81553
KCL wrote: >Is there a way to make a global reset on startup of fpga?? > >Thanks > >Alexis > > > > You do not need to think about this. It happens automaticly every time the FPGA is loaded. Regards ThomasArticle: 81554
"Thomas Rudloff" <thomas_rudloff_REMOVE_SPAM@gmx.net> wrote in message news:3ao6ojF6decsqU1@individual.net... > KCL wrote: > > >Is there a way to make a global reset on startup of fpga?? > > > >Thanks > > > >Alexis > > > > > > > > > You do not need to think about this. It happens automaticly every time > the FPGA is loaded. > > Regards > Thomas Sure, my Actel anti-fuse FPGA resets every time it is loaded.....NOT. It does depend on the technology. I have used a simple RC to accomplish a necessary reset. But there is usually some kind of system reset that can be used. -- Greg readgc.invalid@hotmail.com.invalid (Remove the '.invalid' twice to send Email)Article: 81555
Eric wrote:
> Marc, thanks for the answers!
>
> > I don't think it necessarily would be, except that there is no
telling
> > how long it will take all the reflections to settle out (highly
> > dependant upon PCB routing). One way to cut down on all the
> > reflections would be to put a weak termination pull resistor, or
maybe
> > AC-termination, at every couple FPGA's. Don't use the built in
pull
> > resistors - you can't tune tune them, and they are too weak to be
used
> > as anything as a pure weak pull up/down. But too much termination
will
> > affect rise time.
>
> As I understand it reflections are still a problem with LVDS
signalling,
> so you're right, this could be a problem. If I've got a shared
(multidrop)
> LVDS bus with 20 inputs and one driver, I'm also worried about the
input
> capacitance slowing rise time. Would it be possible to use the DCI on
the
> spartan-3s to help cut down on reflections?
Howdy Eric,
Sorry, I didn't really address the differential situation. Multi-drop
LVDS should take care of most of the reflection, but not having done it
myself, I can't address the pro's or con's - and I especially don't
know what the smallest usable bit-time is.
> > You haven't said how many spare pins the aggregator FPGA will have,
but
> > my first thought was to do as you mention and use dedicated serial
links
> > for each FPGA, but without the clock recovery. Instead, just keep
the
> > whole board synchronous: distribute the clock so that it reaches
every
> > FPGA at the same time and put the aggregator FPGA in the middle.
Use
> > the IOB flops for both output and input, and I think you'll have
plenty
> > of time left over for PCB data prop delay.
>
> 20 FPGAs * 4 DDR LVDS Pairs = 160 wires, which isn't something I can
pull
> off with any components I can solder by hand. :( Plus this
configuration
> is a bit of overkill, as I really only need ~125 MB/sec aggregate
> bandwidth (I'm reusing a gigabit ethernet design I did for off-board
IO...
> UDP/IP in vhdl isn't fun, but it's fast).
To save pins, my favorite idea is a variation on Phil Short's response.
You could do a tree network: the four chips in each corner would feed
to one of four sub-aggregator's. The sub-aggregator would combine the
four streams plus its own, and forward the resulting data to the main
aggregator (or maybe could feed it to each other to do a distributed
aggregation?). Of course, this assumes you can stand the pipeline
delay, and have enough space in those four sub-aggreators for a 5:1
function. This would keep pin-count down enough you could do source
synchronous if you wanted.
> I agree that keeping things synchronous would be best, but then I get
> worried about the combined effects of propagation delay and clock
skew,
> which would seem to easily swamp the 4 ns window for DDR 125 MHz.
If the clock nets going to each target device are kept the same length,
clock skew should not be a concern. The window is more of a
challenge...
Approximate worst case timing:
Tickofdcm: 1.75 ns (basicly clk to out)
prop delay:~1.45 ns (approx prop delay of 8 inches of trace)
Tiopick: 1.89 + 0.75 ns (setup time for LVDS)
---------------------
total: 5.84 ns
WAG at best case (just to have some numbers to throw around):
Tickofdcm: 1.25 ns (basicly clk to out)
prop delay:~1 ns (prop delay of approx 6 inches of trace)
Tiopick: 2 ns (setup time for LVDS)
---------------------
total: 4.25 ns
So if these numbers are close to correct (they might not be), the data
would appear at the next chip as if it had been delayed by a clock
cycle (although the best case WAG cuts the margin very close).
> Is there
> any way to use the DCMs on the Spartan-3s to help reduce the effects
of
> clock skew across the 20 FPGAs? I have to confess that I've never
quite
> understood how to use the DCMs, even after reading the app notes.
I believe the original use of DLL/DCM/PLL devices is for actually that
- system synchronous clocking. In their default mode, they remove the
delay so that the rising edge internal to the FPGA occurs at the same
time as the rising edge outside the FPGA (often time, a tad before
BEFORE) - so the whole board, inside the FPGA and out, is transitioning
at basicly the same time.
All you have to do (famous last words) is take the clock to out time,
prop delay, and setup time, and you can compute your timing budget
against your period. Of course, if you have a range of net lengths and
your IO timing is somewhat variable due to temperature, voltage,
process, etc, system synchronous timing can be a challenge for higher
clock rates - starting at around the speed you're at.
Good luck,
Marc
Article: 81556Eric, why do you want to use many small FPGAs in bad packages, when you could reduce your device count by a factor 8 and use a package that guarantees better signal integrity? Spartan-3 has lower performance than Virtex-II, and the TQ144 is probably the worst available package from a signal-integrity point of view. I would use a few Virtex-II devices ( perhaps eight 2V2000 or two 2V6000 chips), and avoid most of the interconnect hassles that you mentioned. "Keep most of the routing on chip!" If this is a university research project, contact Xilinx University Support. They can be quite helpful... Peter Alfke, Xilinx Applications Eric wrote: > Hello! I'm trying to build a 20-FPGA (spartan-3s, XC3S400-TQ144s) board > for a class project to investigate the use of FPGA arrays for accelerating > scientific competition. The idea was to have a 66 MHz 16-bit > single-ended shared TX bus sending 125 MBps to each FPGA, and a shared 66 > MHz 16-bit data aggregation bus where a bus controller would poll each > FPGA sequentially to place its output data onto that bus. > > After discussions with some signal-integrity-leery friends, I'm no longer > convinced that a 12"x12" 20 IC board at 66 Mhz with single-ended buses is > such a good idea. I've been reading the various datasheets on doing LVDS > and DDR signaling. Multidrop LVDS is still a bit tricky, evidently, but to > cut down on trace number I might be able to go to 125 MHz DDR 4-pair LVDS > for the TX bus; the problem I'm having is with the data aggregation bus. > > Could the aggregate data bus be structured in a similar manner, with: > a.) all FPGAs connected to the 4 DDR LVDS pairs? > b.) a single master, with a separate output enable line to each of the 20 > FPGAs > > Such that when FPGA n is output-enabled, it would drive it's m nibbles of > data onto the output aggregation bus. But this would require FPGA n to > drive its pins within 4 ns; this sounds nearly impossible. > > Are there any common solutions I'm missing? One thought was to aggregate > all of the data from the FPGAs via dedicated serial links and do clock > recovery at the bus master; this would require recovering 20 separate > clocks, alas, and with the spartan 3s we don't have quite that many DCMs. > > An obvious solution is "do an IBIS simulation, duh" but we don't > have access to the sort of high-end signal integrity simulation software > that this would require. > > Can anyone with spartan-3 serial interconnect experience offer > suggestions as to how to make this work, either through different > LVDS configurations or interconnect topolgies? > > Thanks for any advice you > can give, > ...EricArticle: 81557
info_ wrote: > [...] > As of Xilinx, I haven't tested 7.1 yet. Has anyone feedback & experience > to share ? There are a few minor improvements here and there (advanced mode is now finally obvious), but save the new design summary screen, the UI for 7.1 appears basicly unchanged from 6.x. > [...] my worst [Xilinx] grief > is that it's way too easy to have the focus on the wrong design entity :-) > This feature didn't exist in Synario, and it was much less error-prone. > Definitely minor, but irritating. With QII, you can > change your focal point, but you can't do it without noticing. I've already done that in 7.1.1i, several times. Agreed - quite irritating. > I find Impact's look and use a bit clumsy and old-looking, but it works. > I guess it has been improved in 7.1. > [...] I haven't used it to program devices directly, only to generate .hex files, it that appears unchanged from 6.x. I agree on your other observations of Impact. It would drive me absolutely crazy if it weren't for .cdf files to save your configuration! Have fun, MarcArticle: 81558
Is there any way to use the JTAG pins of an EPM7128S for user I/O, without permanently commiting them as I/O and thereby losing the JTAG capability? I want to download data from the PC, via a ByteBlaster cable, into a 2kx8 static RAM connected to the CPLD. I suppose I could add some jumpers for re-patching the 10-way header to standard I/O pins; or have a second, dedicated header for the RAM download; but I would prefer to use the JTAG pins if possible. TIAArticle: 81559
> Eric, why do you want to use many small FPGAs in bad packages, when you
> could reduce your device count by a factor 8 and use a package that
> guarantees better signal integrity?
> Spartan-3 has lower performance than Virtex-II, and the TQ144 is
> probably the worst available package from a signal-integrity point of
> view.
>
> I would use a few Virtex-II devices ( perhaps eight 2V2000 or two
> 2V6000 chips), and avoid most of the interconnect hassles that you
> mentioned. "Keep most of the routing on chip!"
> If this is a university research project, contact Xilinx University
> Support. They can be quite helpful...
> Peter Alfke, Xilinx Applications
Peter,
Xilinx University support has already been very helpful, supplying me
with an ISE license and the XC3S FPGAs I'm planning on using in this
project. The XC3S400 has 3584 slices, so for a 20-FPGA board I'd have 71k
slices available. I can get these for $400 total (nuhorizons). The
XC2V2000-4BG575C (again, nuho) costs $450, and has 10k slices. So to get
the same number of slices I'd be looking at $3150 in FPGA hardware. With
the XC2V6000, nuhorizons doesn't list a price, but I can imagine the
expense would be similar. I agree with your adveritising: spartan-3 is the
cheapest xilinx technology you can get.
Plus, there are additional costs when using the BGA packages -- need
for 6-mil traces and 10-mil vias, coupled with the high layer count needed
just to get at the inner balls, rules pcbexpress.com and friends right
out. Even better, you can't exactly attach a BGA component to a PCB by
hand (and I don't think I'd want to try with a $450 component and a
toaster oven). I know there are places that will do this for you, but they
have high setup fees (which for a one-time project like this really kills
the budget).
I know my approach is in many ways sub-optimal but I'll be able to build
it all for around $600. That's a lot of logic to play with for a
relatively small amount of cash. And it will let me play around with some
algorithms and whatnot to determine if it's really worth it. And if I can
find some places where it will let me speed up my daily computations,
maybe I'll have time to consider investing in the high-end FPGAs for the
next generation.
Thanks,
...Eric
Article: 81560Eric, the economics of a student project and a commercial project are obviously very different. In industry, a cost difference of $ 1000 or even $ 2000 would never jeopardize a research project. Industry values one engineer-day as at least $ 500, and I would bet that the larger parts and the reduced pc-board trouble would save many days of work and achieve more impressive performance. But when it's educational, and the labor is "free", the picture is obviously different. I just wanted to save you some headache with the PQ144s. Peter AlfkeArticle: 81561
Hello, I am interested in learning fpga. I want advice on which software/HW dev board should I pick. I have downloaded eval copies of Altera, Xilinx and Aldec. I am playing around with each to decide which I should stick too and now planning to buy a H/W borad I am also interested in embedded RTOS/ soft core procesors, DSP and communications area. Altera has Nios and Xlinx has Picoblaze/Microblaze softcore processors Which one is better suited for a newbie and will serve better to my interests as given above? Altera and Xilinx only supports their on CPLDs and FPGAs. I am planning to purchase a H/W dev board. I need advise on which board to buy (Xilinx specific or Altera specific) so as to protect my investment. I have found Spartan 3E board from Xilinx ($ 149) particularly tempting for the kind of projects I want to do and is relatively cheap with all hte features to do serious study. But I want a professional advice from you guys. Thanks in advance for your time Nirav RavalArticle: 81562
I agree with everything you've said about QII. The last few QII releases have been a joy to use. I upgraded twice in the middle of a major project without regret. SOPC Builder seems to be way ahead of the stuff for Microblaze too. My biggest remaining beef is that GUI-wise LogicLock and tracking down nets in the Timing Floorplanner (forget the real name) is so darn slow, and Phys Synth duplicates nodes it shouldn't have to (although it's a lifesaver if you really need to meet timing). I watched a demo video of PlanAhead for Xilinx which seems to have the same functionality as LogicLock and everything was zipping along at top speed. Maybe they were cheating in the video though. Anyways, eagerly awaiting QII 5.0 now. -- Pete info_ wrote: > Hi Antti, > > At ALSE, we design all kinds and brands of FPGAs and have been doing so for years and > years (the first FPGA I dealt with was a XC2000 under XDE,- 17? years ago-). Until > less than two years ago, we did design more Xilinx than Altera parts (we respect the > customer's decision when he wants a particular device or family). > And ISE is based on a technology (Synario & ECS) that I supported even before it had > a name -and I more than liked this tool, still use it occasionnally-. > When Quartus was launched, it was terrible, and stayed that way for a while. However... > > IMO and backed up by concrete experience, I would say that the progress made by > Altera with Quartus tools (and devices) over the last two years has been tremendous > and probably gone very much unnoticed, until recently. > > Quartus II has progressed a lot, and it's not over... > The new device architectures (like MaxII) are as surprising as they prove efficient > concretely. We love the Cyclone family : cheap, extremely low power and they are > usually faster than the usual applications require even in their lowest speed grades. > > - As of tool quality, I keep my fingers crossed, but I don't fear loading the latest > QII release (even beta) and start using it right away in the middle of challenging > designs. I usually let other tools "ripe" a bit. > > - As of integrated synthesis, both for QOR and language coverage (VHDL) I won't > comment, by fear of offending third party tools vendors. I've witnessed 30% smaller > designs with QII v4.2 as compared with older versions, and I have problem with > standard descriptions with XST which are perfectly supported by QII now. There are > still a few things I would like to see added in QII (like character'pos), but they > should be in 5.0 or 5.1 and I stopped asking for VHDL QOR improvement. > > - QII's Static Timing Analysis + constraint-driven P&R + Physical synthesis are > impressive. Most FPGA users need to be educated in order to take advantage of it. > Physical synthesis can for example fix design errors by automatically compensating > data or clock delays, it can precisely adjust delays for SDRam interfaces, etc... > I'm not saying other tools don't have this technology, just that users are often > unaware that it's in Quartus II. > > - Tcl/Tk and command-line tools are so easy to use ! (you find a Tcl console in > almost all tools now -yes: ModelSim too : just type parray env-). > You can build and download an FPGA with a single double click on a batch file and > never see the GUI if you want to, with a trivial script. This contributes greatly to > the ease of use of our Tornado FPGA Board and Tornado Education Kit. > > - SoPC is probably the strongest advantage I see as of now for Altera. The NIOS II > processor, the Avalon switch fabric, and the Tools around them have proved their > value. I know several companies even purchased the NIOS license... for ASICs. > > - RTL and Technology graphical Views are very decent, and the cross-probings between > all the different descriptions is handy when investigating. > > - The Constraints Editor, initially clumsy, is now very powerful & versatile. > You can for example easily import export CSV pin assignments (with PCB tools or > Excell). It is well organized and easy to use. > > - The GUI commands have their immediately visible Tcl counterpart, so it's a trivial > task to automate even the most complex settings. > When we deliver an FPGA design to a customer, we only have HDL source files and a > single "does-it-all" Tcl script (which also includes the pin & other assignments). > > - SignalTap and InSystem Memory Contents Editors are _VERY_ easy to use (and cheap if > not free). > > - LogicLock makes floorplanning (almost) easy when the need comes. > > - JTag (Jam) player is nice in some cases. Not sure Xilinx has the equivalent public > code. (well probably) > > - I think the cost is lower for the full version of QII compared with Foundation and > equivalent options (ChipscopePro) but prices move often. > > - It's very easy to integrate other tools within QII, or to integrate QII inside > other tools. I don't think any other tool is as open as QII. > > - OpenCore IP protection scheme is clever. It lets you play with IPs as you please. > The megawizzard is also easy to use. > > - Power estimation in 4.2 is now simple to use, both as an early tool, then along > when the design gets refined. > > - Early estimators, and fast assignment verifiers, Design assistant, Performance > advisors definitely make the designer's life easier. > > - Never used DSE nor distributed computing (hope I won't have to), but I know it's there. > > - More new features are announced. > > As far as I know, Altera bought a couple of small but very brilliant companies that > are behind these technology leaps. > > On the minus side for Altera I would mention : > - Truly incremental P&R is coming, but still not quite here yet. Many users are > impatient (it will be welcome for the big chips). > - For simple designs : Analysis & Elaboration must be run in order to view the > hierarchical dependencies (ISE does this automatically), not a real issue but it's a > bit unexpected for ISE users when they try QII. For big designs, you don't let the > tool guess what it should compile and in which order; we use scripts. > > It's very easy to use Quartus II and simply not unleash its power even when you need > it. That's why we made efforts to build and offer (with lots of help from Altera) an > extensive 2-days Training course in France, and we get an excellent feedback on it. > > What we try to say to our customers is that Quartus II now deserves spending some > time learning its many features and capabilities. For simple things, not much if > anything at all is necessary (a batch file can do everything), but challenging tasks > will be much simpler with a good understanding of the engine under the hood. > --- > As of Xilinx, I haven't tested 7.1 yet. Has anyone feedback & experience to share ? > > Obviously, we don't fear designing Xilinx chips (we design mostly very complex > applications now) and ISE is easy to use. Besides the lack -as far as I know- of easy > and well documented scripting (Tcl/tk), my worst grief is that it's way too easy to > have the focus on the wrong design entity :-) This feature didn't exist in Synario, > and it was much less error-prone. Definitely minor, but irritating. With QII, you can > change your focal point, but you can't do it without noticing. > VHDL synthesis (XST) has also some issues and weaknesses, and I sometimes have to > partially rewrite some of our IPs for this reason (I complained a couple of times > about poor support for qualified expressions for example). > I find Impact's look and use a bit clumsy and old-looking, but it works. I guess it > has been improved in 7.1. > I also hope they removed or rewrote these offending VHDL "examples" !!! (like j2c_vhd > on top of my head). > > On the X. side, I found Xilinx Tech Support outstanding (maybe only ModelSim's does > impress me even more). > > I loved ECS in Synario and first ISE versions, with the generic symbol library and > all the cool utilities related with HDL, but I don't like what it became in the > latest versions of ISE. But schematic editors are usually a matter of personal taste > (I'm not a huge fan of QII's schematic editor either) and we don't use them much if > at all (top levels only, if we find enough motivation). > > If you plan to stay with Xilinx, don't start using Quartus ;-) > > Things are very cyclic in this industry, so I expect an effort from the competition > to regain the lost terrain. It makes things interesting for us to watch. The good > news are that the end-user is usually the winner on the end, with powerful and > affordable tools and devices. But high-end FPGAs and applications are bringing us > lots of challenges : high level descriptions and modelling, ABV, high-speed design, > power issues, P&R challenges, IPs reuse, collaborative design... we'll see. > > > Bert Cuzeau > > --- The opinions above are my own only. > --- I may be wrong on some issues. > --- If you think so, or believe I am unfair in any way, let me know. > > > Antti Lukats wrote: > > Hi > > > > first - I am a very Xilinx biased (possible because I have way more Xilinx > > boards) > > but the latest Quartus seems really easy and in some cases better than X > > tools > > (at least the built in programmer is FASTER to use than impact) > > > > Story: > > After getting a nice application tested on Xilinx FPGA I just out of > > curiosity > > tried to port to Altera devices, the only problem I had was related to lack > > of documentation on the cyclone_jtag and maxii_jtag, after solving those > > the original xilinx code compiled without changes and worked too :) > > > > http://wiki.openchip.org/index.php/OpenChip:FpgaFreqMeter > > > > after first success with Cyclone, I tried it on MAX2 and worked again :) > > > > MAX2 is really nice well its not so much an PLD but more like > > Xilinx XC2K reinvented and made flash based ;) anyway it is > > really a heavy player on the flash device arena as the other > > suppliers Atmel and Lattice are not yet shipping their low-cost > > flash FPGAs > > > > Antti > > > > > > > >Article: 81563
In article <d272lg$80c$1$830fa7a5@news.demon.co.uk>, Andrew Holme <andrew@nospam.com> wrote: >Is there any way to use the JTAG pins of an EPM7128S for user I/O, without >permanently commiting them as I/O and thereby losing the JTAG capability? I >want to download data from the PC, via a ByteBlaster cable, into a 2kx8 >static RAM connected to the CPLD. I suppose I could add some jumpers for >re-patching the 10-way header to standard I/O pins; or have a second, >dedicated header for the RAM download; but I would prefer to use the JTAG >pins if possible. I believe that you can make the other pins of the CPLD go high and low via the JTAG port. I don't have my Altera data book here. It will be very slow. You could bring a couple more connections to the JTAG connector by adding a couple of pins and making it "non-standard" or comply with the "Holme standard" if you prefer. You can then put one program into the CPLD to load the static RAM and a different one to use it. BTW: I routinely program 7000S parts with a cable that just uses resistors and the parallel port of a PC. You don't need to specifically use the Byteblaster cable to work with the Altera parts. -- -- kensmith@rahul.net forging knowledgeArticle: 81564
Marc, Thanks a lot for the details ! When productivity is involved, scripting is the way to go, and this gets rid of the GUI irritations. That's why I am more and more sensitive to the scripting offered by tools, and I appreciate when I find extensive Tcl support.Article: 81565
You can change the reset embedded in the post-layout model : Reset On Configuration Pulse Width, 100 by default. BertArticle: 81566
On Sun, 27 Mar 2005 16:39:21 -0500, "Nirav Raval" <niravraval@yahoo.com> wrote: >Hello, >I am interested in learning fpga. I want advice on which software/HW dev >board should I pick. I have downloaded eval copies of Altera, Xilinx and >Aldec. >I am playing around with each to decide which I should stick too and now >planning to buy a H/W borad. I am planning to >purchase a H/W dev board. I need advise on which board to buy (Xilinx >specific or Altera specific) so as to protect my investment. >I have found Spartan 3E board from Xilinx ($ 149) particularly tempting for >the kind of projects I want to do and is relatively cheap with all hte >features to do serious study. But I want a professional advice from you >guys. >Nirav Raval A very extensive list of boards for you to peruse can be found in the FAQ: http://www.fpga-faq.org/FPGA_Boards.shtml Philip =================== Philip Freidin philip.freidin@fpga-faq.org Host for WWW.FPGA-FAQ.ORGArticle: 81567
Project > Cleanup then Project > Archive I personnaly use a modified cleanup batch since the Xilinx one does (did?) forget a number of useless files (log) & subdir...and it does erase the resulting files... But basically it works if source files is what you want to archive. The idea is that you should be able to rebuild the resulting files from the backup. If you want to save resulting files (like .bit or .hex), save them first ! Bert Brad Smallridge wrote: > What is the best backup procedure for Xilinx? > > I have used snapshot which seems to copy the whole > directory into the current director. You can attach > a description to it. Archive compresses the data. > And Save Project As seems to get rid of some of > the clutter in the directory. > > b r a d @ a i v i s i o n . c o m > >Article: 81568
Peter Alfke wrote: > Eric, > the economics of a student project and a commercial project are > obviously very different. > In industry, a cost difference of $ 1000 or even $ 2000 would never > jeopardize a research project. Industry values one engineer-day as at uh... unless this $1k-2k removes the research subject altogether ;o) say, someone's interested in constructing arrays of FPGAs ? And once happy with the results then intends to move into larger IC territory ? l > least $ 500, and I would bet that the larger parts and the reduced > pc-board trouble would save many days of work and achieve more > impressive performance. > But when it's educational, and the labor is "free", the picture is > obviously different. > I just wanted to save you some headache with the PQ144s. > > Peter Alfke >Article: 81569
I get this message when i synthesize my code "you may be trying to describe a RAM in a way that is incompatible with block and distributed RAM resources available on xilinx devices, or with a specific template that is not supported" I have this signal sram_data which is of type array(0 to 255) of std_logic_Vector(7 downto 0). I am assigning values to each element sram_data(N) inside a state machine and this message pops up when i synthesize. any comments on how i can fix this? thanksArticle: 81570
Try instantiating a block ram. You can then initialize the contents either in your .ucf file or in your VHDL source. For example of initialization syntax, refer to the lib.pdf available in installation directory of xilinx ie /xilinx/doc/usenglish/docs/lib/lib.pdf -- Regards, John Retta Owner and Designer Retta Technical Consulting Inc. email : jretta@rtc-inc.com web : www.rtc-inc.com "fpgawizz" <bhaskarstays@yahoo.com> wrote in message news:d5d884e8ab58fb26f00a0433cdb94894@localhost.talkaboutelectronicequipment.com... > I get this message when i synthesize my code > "you may be trying to describe a RAM in a way that is incompatible with > block and distributed RAM resources available on xilinx devices, or with a > specific template that is not supported" > > I have this signal sram_data which is of type array(0 to 255) of > std_logic_Vector(7 downto 0). I am assigning values to each element > sram_data(N) inside a state machine and this message pops up when i > synthesize. > any comments on how i can fix this? > > thanks > >Article: 81571
Remember that a Xilinx BlockRAM is clocked. Even to read, you must supply a clock. In that respect these BlockRAMs are different from "conventional" RAMs, where the reading is combinatorial. Peter AlfkeArticle: 81572
First.. Modelsim is designed to provide repeatable testing.. this means you write test benches and you don't toggle lines manually. You can force lines about but you are probably best served by learning how to create and use test benches. It is also OK to have several test benches each of which tests different functionality. If you want to graduate and be useful you will need to learn this methodology. Simon <hacka@wp.pl> wrote in message news:1111780104.805123.196680@g14g2000cwa.googlegroups.com... > Hi, I have downloaded Xilinx ISE 7.1 webpack and Modelsim 6 free > edition. > I need Xilinx for my digital circuits course. > During the course laboratory we were using Xilinx foundation 2.1. After > designing simple circuit I have attached some probes to inputs and > output and then in simulator bound some keys in order to change input > signals' from 0 to 1 and test the output. > > The problem is I don't know how to do the same in 7.1 + ModelSim. First > of all there is no such thing as "simulation toolbox" as in 2.1. > I was able to run Modelsim and apply clocks to input signal but it is > not what I want. Is it possible to change input signals from 0 to 1 etc > on the fly? With keyboard for example? > Cheers, > Mike, leet.geezerDONT_SPAM_ME_PLS@gmail.com >Article: 81573
For starters forget about the processor... Start with looking for hardware that suits you.. USB, Ethernet with MAC and PHY, DRAM, FLASH etc. Possibly even a display. That will give you a board you can start with, Altera or Xilinx doesn't matter when you are learning. Essentially they are the same just with different features. The main thing is to make sure you have the biggest and most affordable device that can be used by the free tools. The forget about the mac, phy, dram, flash, usb .... everything but the FPGA. Learn how to right simple VHDL or Verilog and create programs that can flash LED's and read switches... once you can understand that, start looking and reading about the processor.. just try simple things until you can make something useful... but I would ignore the Ethernet and USB until university where a professor can help.. protocol stacks are not for the faint hearted. neither is building a single chip processor. But it you persist and can sort out mappings, you can easily do it yourself and gain a good working knowledge of imbedded chip design, but I wouldn't expect that straight away. Simon "Nirav Raval" <niravraval@yahoo.com> wrote in message news:2uadncpdCceNtdrfRVn-1A@rogers.com... > Hello, > I am interested in learning fpga. I want advice on which software/HW dev > board should I pick. I have downloaded eval copies of Altera, Xilinx and > Aldec. > I am playing around with each to decide which I should stick too and now > planning to buy a H/W borad I am also interested in embedded RTOS/ soft > core procesors, DSP and communications area. > Altera has Nios and Xlinx has Picoblaze/Microblaze softcore processors Which > one is better suited for a newbie and will serve better to my interests as > given above? > Altera and Xilinx only supports their on CPLDs and FPGAs. I am planning to > purchase a H/W dev board. I need advise on which board to buy (Xilinx > specific or Altera specific) so as to protect my investment. > I have found Spartan 3E board from Xilinx ($ 149) particularly tempting for > the kind of projects I want to do and is relatively cheap with all hte > features to do serious study. But I want a professional advice from you > guys. > Thanks in advance for your time > > Nirav Raval > > > >Article: 81574
Folks, I'm looking at a design problem that may need a floating point unit (single precision is fine). Part of the unknown at this point is that it would be running with the Microblaze embedded soft core on a Spartan 3S400. Do you have any recommendations for an FPU? Does such a configuration leave room (system gates, on-chip resources, etc) for anything else in terms of running a DSP type calculations (e.g. adaptive filters) and device control? I've seen the core provided by Quixilica, but would prefer to go to something free or open source due to the fact that I may find out it's not the solution, esp for the prototying phase. Thanks, -HT
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