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paulw@mmail.ath.cx wrote: > Hi > > Someone must have ask this question before. Is it a good idea to use > verilog's reg > to declare a large block of memory and expect it will be synthesizable? > > > Thanks > Most synthesizers will infer such a block as FPGA block memory if the HDL is written in a certain way. Look at the user's guide of your synthesizer for more details. -KevinArticle: 81601
And before that HandelC but not sure about C++ aspect as I don't recall any class support. You have some learning curve in front of you which ever direction you go in as you will be touching real HW. Unless you are in a .edu environment you will be paying a pretty penny for any C/C++ to HW generation. You could just as easily take a look at any Verilog/VHDL text on DSP design and see if it wouldn't make more sense to go direct to HW that way. You only need to learn a very small subset of either language to get the results you might want, more if you use the language fully for verification, less if you use C. More if you want best performance possible. Upside is your tools will be almost free for X/A for either V/V language (upto modest size designs that is) and your results will be ultimately much better than any C/C++ path. Downside is you may be looking at multiple language representations of the same code. Thats not necessarily hard but it takes time to learn how to think HW and code appropriately while also wearing your C SW hat. One aproach I use is to use a cycle C form that essentially looks like Verilog line for line until you look close enough. Cycle C is obviously free for me and runs on any C like env, but doesn't take much time either to fix the syntax back into proper Verilog. It is limited in many ways (flattish hierarchies) but works well for DSP/cpu projetcs for me and test vectors used in the C model are easy to convert to Verilog. Another poster might suggest Confluence, or SystemC to look at too.. Once you choose the V/V HDL route you also get the benefit of a far larger NG base to call upon, here, verilog/vhdl and of course dsp NGs etc. And in particular a few experts around here and quite a bit of free source code from opencores and also X/A websites. If you use a proprietary C++HDL you are confined to a much smaller source of examples, free goodies and advice! If that tickles your fancy then Palnitkar, Doug Smith and a few others are very good HDL authors. regards johnjakson at usa dot comArticle: 81602
Hi- I am in the midst of bringing a Xilinx design to the lab. It is in a larger BGA package and is becoming hard to probe. In order to assist in the lab- I am trying to print out a huge plot that would show the balls and their associated signal with them. I am hoping there is an easy way to do this. We are using ISE 6.2 on a Solaris box. Tx, WPArticle: 81603
paulw@mmail.ath.cx wrote: > Is it a good idea to use verilog's reg to declare a large block of > memory and expect it will be synthesizable? There are two ways to synthesize a memory in an FPGA. One is to use verilog's reg as you suggested, the other one is to use Vendor Specific Primitive. Using verilog's reg is the most portable one. It works with all FPGAs with little or no modification. But it takes valuable space in your FPGA logic that otherwise can be used for other purposes. An alternative way is to instantiate Vendor Specific Primitive. This method is not portable. You must instantiate different primitive for different chips family and vendors. However, you will safe a lot of space in your chips since instantiating a Vendor Specific Primitive means you will use a dedicated memory in the chip, leaving the logic free to be used for other purposes. HendraArticle: 81604
Have you looked at Chipscope? Jim jimwu88NOOOSPAM@yahoo.com (remove capital letters) http://www.geocities.com/jimwu88/chips <wpiman@aol.com> wrote in message news:1112053196.838577.30050@l41g2000cwc.googlegroups.com... > Hi- > I am in the midst of bringing a Xilinx design to the lab. It is in a > larger BGA package and is becoming hard to probe. In order to assist > in the lab- I am trying to print out a huge plot that would show the > balls and their associated signal with them. I am hoping there is an > easy way to do this. We are using ISE 6.2 on a Solaris box. > > Tx, > WP >Article: 81605
"Hendra" <u1000393@email.sjsu.edu> wrote in message news:1112055725.715876.230210@l41g2000cwc.googlegroups.com... > paulw@mmail.ath.cx wrote: > > Is it a good idea to use verilog's reg to declare a large block of > > memory and expect it will be synthesizable? > > There are two ways to synthesize a memory in an FPGA. One is to use > verilog's reg as you suggested, the other one is to use Vendor Specific > Primitive. Using verilog's reg is the most portable one. It works with > all FPGAs with little or no modification. But it takes valuable space > in your FPGA logic that otherwise can be used for other purposes. Most of the synthesis tools are able to infer dedicated RAM blocks. Jim jimwu88NOOOSPAM@yahoo.com (remove capital letters) http://www.geocities.com/jimwu88/chips An > alternative way is to instantiate Vendor Specific Primitive. This > method is not portable. You must instantiate different primitive for > different chips family and vendors. However, you will safe a lot of > space in your chips since instantiating a Vendor Specific Primitive > means you will use a dedicated memory in the chip, leaving the logic > free to be used for other purposes. > > Hendra >Article: 81606
wpiman@aol.com wrote: > Hi- > I am in the midst of bringing a Xilinx design to the lab. It is in a > larger BGA package and is becoming hard to probe. In order to assist > in the lab- I am trying to print out a huge plot that would show the > balls and their associated signal with them. I am hoping there is an > easy way to do this. We are using ISE 6.2 on a Solaris box. > > Tx, > WP > You should be able to create such a plot with the PACE tool that comes with ISE. Probing the balls will be tough, though. There is a 'probe' feature in FPGA Editor that allows you to add a probes to nets without rerunning PAR. Then if you have a header connected to some unused pins, you can route nets to this header and probe them that way. As the other respondent said, ChipScope is also good for monitoring internal signals. -KevinArticle: 81607
fpgawizz wrote:
Good chance you are not using it as a synchronous RAM. Look at the
synthesis templates either in your synthesizer or on Xilinx's synthesis
guide. It would be helpful if you posted the code in question so that
we can see what you are doing.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 81608
On Tue, 29 Mar 2005 00:42:09 +0200, Piotr Wyderski wrote:
> Eric wrote:
>
>> Hello! I'm trying to build a 20-FPGA (spartan-3s, XC3S400-TQ144s) board
>> for a class project to investigate the use of FPGA arrays for accelerating
>> scientific competition.
>
> Forgive my curiosity, but why are you going to use a cluster of FPGAs
> to perform scientific computations? Wouldn't a bunch of high-speed
> floating-point DSP processors be better? FP calculations, which are
> not well supported by the low-cost FPGA chips (huge amount of shifting
> etc.), are the core of most scientific computations.
>
> Best regards
> Piotr Wyderski
Well, at this point it's all about experimentation. This is for a class on
parallelism and supercomputing (beowulfs and the like) and I've wanted to
build some arrays of FPGA-based hardware for a while. There are some
applications for which floating point is unnecessary (signal processing,
crypto, etc), and also it seems that at least single-precision FP might be
possible (I also want to address that).
My day job revolves around large-scale pattern detection (think lots of
FSMs) in neural data, so there's not much FP at all...
...Eric
Article: 81609On Sat, 26 Mar 2005 10:45:58 -0800, John Larkin <jjSNIPlarkin@highTHISlandPLEASEtechnology.XXX> wrote: >On Sat, 26 Mar 2005 17:04:30 GMT, "Bob" ><nimby1_notspamm_@earthlink.net> wrote: > >> >>"nospam" <nospam@nospam.invalid> wrote in message >>news:752b4191vjqonk09q53ufd5iltbjpthfap@4ax.com... >>> "Bob" <nimby1_notspamm_@earthlink.net> wrote: >>> >>> >The first problem is that the LVDS for Spartan 3 is only defined for VCCO >>of >>> >2.5V. So, a given IOB cannot run LVDS and, for example, LVTTL (3.3V I/O) >>at >>> >the same time. >>> >>> VCCO only supplies differential drivers the differential receivers run >>from >>> VCCAUX so I see no reason why you can't have LVDS receivers in a bank with >>> 3.3v VCCO. I have done this without problem but so far only on a >>prototype. >>> >>> For the OP I suggest you look at an IOB with the FPGA editor and see if >>you >>> can find a combination of checkboxes to give you what you want. I suspect >>> there isn't but if there is you will have to find out how to make the >>tools >>> give you what you want. >>> >>> >> >>I think you're correct about the LVDS input diff amp running from VCCAUX. >>However, since VCCAUX is 2.5V (for S3), I wonder if you could still >>overdrive the 2.5V input stage by the 3.3V topside output fet. It may work, >>but the long-term reliability may be in question. >> > >As I said, we did it with an external connection, and it worked great. > >Our only problem is the danged compiler. If you look at figure 1 of >the DS099-2.pdf thing, it sure looks like all the wires I want are >there. In fact, if we can take this diagram literally, the ttl >tristate driver is already connected to one pin of the LVDS receiver. > >>I'd still like to know why John needs to mix LVDS and a single-ended output. >>It's probably something evil or illegal ;-O > >Both. It's so terrible that if I told you, The Authorities would take >away my slide rule. > >John As suggested by nospam, you might get what you want using the FPGA editor. To minimize the amount of fudging, have your ISE schematic entry person do this: - Instantiate both pins as IOPAD - Instantiate IBUFDS with IOSTANDARD=LVDS_25 - instantiate OBUFTDS with IOSTANDARD=LVDS_25 - wire the diff sides of the IBUFDS and OBUFTDS to the IOPADs - wire the OBUFTDS inputs as if it is your desired OBUFT - after compilation use FPGA editor to tweak the IOB to make the output side an OBUFT. You can capture this as a macro for repeatability and documentation purposes. Let us know if this works. ================================ Greg Neff VP Engineering *Microsym* Computers Inc. greg@guesswhichwordgoeshere.comArticle: 81610
On Mon, 28 Mar 2005 21:52:51 -0500, Greg Neff <greg@nospam.com> wrote: >On Sat, 26 Mar 2005 10:45:58 -0800, John Larkin ><jjSNIPlarkin@highTHISlandPLEASEtechnology.XXX> wrote: > >>On Sat, 26 Mar 2005 17:04:30 GMT, "Bob" >><nimby1_notspamm_@earthlink.net> wrote: >> >>> >>>"nospam" <nospam@nospam.invalid> wrote in message >>>news:752b4191vjqonk09q53ufd5iltbjpthfap@4ax.com... >>>> "Bob" <nimby1_notspamm_@earthlink.net> wrote: >>>> >>>> >The first problem is that the LVDS for Spartan 3 is only defined for VCCO >>>of >>>> >2.5V. So, a given IOB cannot run LVDS and, for example, LVTTL (3.3V I/O) >>>at >>>> >the same time. >>>> >>>> VCCO only supplies differential drivers the differential receivers run >>>from >>>> VCCAUX so I see no reason why you can't have LVDS receivers in a bank with >>>> 3.3v VCCO. I have done this without problem but so far only on a >>>prototype. >>>> >>>> For the OP I suggest you look at an IOB with the FPGA editor and see if >>>you >>>> can find a combination of checkboxes to give you what you want. I suspect >>>> there isn't but if there is you will have to find out how to make the >>>tools >>>> give you what you want. >>>> >>>> >>> >>>I think you're correct about the LVDS input diff amp running from VCCAUX. >>>However, since VCCAUX is 2.5V (for S3), I wonder if you could still >>>overdrive the 2.5V input stage by the 3.3V topside output fet. It may work, >>>but the long-term reliability may be in question. >>> >> >>As I said, we did it with an external connection, and it worked great. >> >>Our only problem is the danged compiler. If you look at figure 1 of >>the DS099-2.pdf thing, it sure looks like all the wires I want are >>there. In fact, if we can take this diagram literally, the ttl >>tristate driver is already connected to one pin of the LVDS receiver. >> >>>I'd still like to know why John needs to mix LVDS and a single-ended output. >>>It's probably something evil or illegal ;-O >> >>Both. It's so terrible that if I told you, The Authorities would take >>away my slide rule. >> >>John > >As suggested by nospam, you might get what you want using the FPGA >editor. To minimize the amount of fudging, have your ISE schematic >entry person do this: > >- Instantiate both pins as IOPAD >- Instantiate IBUFDS with IOSTANDARD=LVDS_25 >- instantiate OBUFTDS with IOSTANDARD=LVDS_25 >- wire the diff sides of the IBUFDS and OBUFTDS to the IOPADs >- wire the OBUFTDS inputs as if it is your desired OBUFT >- after compilation use FPGA editor to tweak the IOB to make the >output side an OBUFT. You can capture this as a macro for >repeatability and documentation purposes. > >Let us know if this works. > Thanks, Greg. I'll have the boys try this. JohnArticle: 81611
Answering my own question: > Are the columns of the RAM permuted Yes :( dammit, I want to initialize them! "Peter Y" <nospam@thankyou.com> wrote in message news:hLe1e.38734$nK.1730747@news20.bellglobal.com... > For whatever reason, I need to be able to initialize the M-RAMs in Altera > chips, and I need to do this in a timing simulation, for which I use > Modelsim. > > So I've hacked the stratix_atoms simulation libraries to initialize them, > and that works fine. I can start a simulation, look in those memories and > everything they have is correct, but now the simulation is incorrect. > Anyone know why this might be? Are the columns of the RAM permuted for > timing reasons, is it endianness, or anything else? > > I need to do this with a lot of designs, so setting break points and using > the Update Embedded Memories in Quartus' simulator is annoying. Any other > suggestions? >Article: 81612
Thanks for the info. What is correct current limiting resistor size to use? Thank you "Peter Alfke" <peter@xilinx.com> wrote in message news:1112045758.666028.126300@l41g2000cwc.googlegroups.com... > You can use the FPGA I/O directly, if you apply some common sense. > The sink or source current should be limited to 20 mA ( this may be > overly conservative, but I like to play it safe), so LEDs must have a > current-limiting resistor. > Avoid pulling the pins higher than Vcc or lower than Ground, but there > are also protective diodes that prevent excessive voltages. > Use reasonable care against electrostatic discharge (walking over a > nylon carpet in low-humidity environments can easily generate 10 000 V > or more.) Do not discharge this directly into the pins. > Peter Alfke, Xilinx Applications. >Article: 81613
Eric wrote: >[...] > and the WAG best would be 3.85 ns. Ouch. And this is with using all the > tricks I know, like registers on all the IOBs, etc. > > Given that, and the very short distances (compared to before) these traces > are going, would it be wise to abandon lvds and DDR and just have adjacent > links be 125 MHz single-ended? [...] Howdy Eric, Except that I have no idea how bad the TQ package will muck the signals up, 125 MHz single-ended shouldn't be a problem for the PCB or the die. With a BGA package, even single-ended 125 MHz DDR should work fine. To get around the I/O timing problem that comes with system-synchronous, you can go back to the idea of using a source-synchronous clock to flop it on-chip (either use local routing, which should finally be available with 7.1 on an S3, or a DCM). Good luck, MarcArticle: 81614
In article <d28qta$8qs$1$8302bc10@news.demon.co.uk>, Andrew Holme <andrew@nospam.com> wrote: [...] >Does anyone know where I can find info on how to do this? I have the >"Altera ByteBlaster" device and the "Altera JTAG Server" service running on >Windows NT. Are the APIs documented? I also have Quartus II 4.1 Web >Edition installed. Google on "JAM" and "CPLD" you are likely to find stuff about the JAM STAPL downloading method. Alter supports this and, at least, had documentation about it. You can get the C source code. On an NT system, doing direct printer port I/Os requires special drivers. Even then the timing is a bit wobbly. If you have an old DOS machine, you may be better off than with the NT machine. You can also do it under Linux. I think the 7000 series data sheet has a little about its ISP lines. >Could someone Does anyone know how to do this? Basically, you shift in commands serially and it reacts to the command words. For each thing you do, you shift in a clump of bits. While you shift in, it also shifts results out. This is what the RDI and TDO lines are all about. You have to be careful to give the part clean signals. -- -- kensmith@rahul.net forging knowledgeArticle: 81615
In reference to the following code snippet:
always @(posedge ata_dior)
begin
dout = mem[ addr ];
dout_en = 1;
end
always @(posedge ata_dior)
begin
dout_en = 0;
end
I can't find any doco, tutorial etc that explains exactly what the
'dout_en' waveform will look like. Gut instinct tells me that it will
remain at 0, but it's only a guess.
Can any verilog gurus explain what will happen? And why something might
be coded like this?
TIA
Regards,
Mark
Article: 81616Hi folks, I'm facing one problem that is driving me crazy... The error is the following: Error: JTAG ID code specified in JEDEC STAPL Format File does not match any valid JTAG ID codes for device. I'm using one ALtera University Program with ByteBlaster MV Cable on a Windows XP machine. This is my first project in FPGA... I read almost everithing about ByteBlaster and Quartus II configuration, and nope... My cable is installed, and everytinh else... Thank you very much in advance. JL MartinsArticle: 81617
In article <pan.2005.03.28.14.27.13.726849@gmail.com>, Eric wrote: > > I can snake them around my board like: > > 4 5 14 15 > 3 6 13 16 > 2 7 12 17 > 1 8 11 18 > 0 9 10 19 > > MASTER > NIC 4 5 12 13 3 6 11 14 2 7 10 15 1 8 9 16 0 19 18 17 -- [100~Plax]sb16i0A2172656B63616820636420726568746F6E61207473754A[dZ1!=b]salaxArticle: 81618
> I do not have FPGA experience, and I am not sure if my question make sense. > > Assume that we have a set of C++ code of various set of signal processing, > filtering, decision making, neural network, fuzzy logic etc. > Is it possible to convert (some how) these C++ code to run in FPGA ? > Is there a tool to convert C++ to FPGA code? As others have mentioned, there *are* tools to convert C++ code to FPGA code, but your mileage may vary, and some effort will likely be required to make the generated VHDL/Verilog function properly. If the C++ code has already been written, a simpler solution might be for you to use a processor core (say, from http://opencores.org, or the Nios, etc.) .... Though perhaps not as fast as a pure hardware implementation, this might offer you a quicker/easier path to completion. KrisArticle: 81619
GT wrote: > Thanks for the info. > What is correct current limiting resistor size to use? > Thank you > Let's say that the voltage drop on LED is 1V, the FPGA/CPLD output voltage is 0.3V, and the LED current is 5 mA. The resistor would be (3.3-1-0.3)V/5 mA=0.4 kOhm vax, 9000Article: 81620
"John_H" <johnhandwork@mail.com> schrieb im Newsbeitrag news:wkW1e.1$4R6.126@news-west.eli.net... > "Antti Lukats" <antti@openchip.org> wrote in message > news:d2348g$cjb$04$1@news.t-online.com... > > < snip> > > > Hi John, > > > > nice :) ! > > would it be ok to add your code to the 'xilcores' project? > > http://gforge.openchip.org > > ? you are of course welcome todo it yourself, just register > > and I will add you to the project developers > > > > Antti > > Since I hadn't run a full simulation, I'd be hesitant to throw it in there > without a solid double-check but feel free to add the code yourself if you > like. Anyone is welcome to try to leverage this approach whether for your > contest or for commercial projects. > > Anyone working with SRLs in this sense should be aware: the global reset to > the Xilinx device could deassert asynchronously to different SRLs at > different clocks, knocking off the needed alignment between the SRLs. I'd > suggest working in a global enable for all the SRLs that waits a few clock > cycles before letting everything run. Another approach would be to use the > BUFGCE primitive in the newer families using the same delayed enable to gate > the clock to the entire FPGA rather than just the enables to the SRLs. Hi John, I think that isnt a problem (most cases) the SRL are not connected to global set/reset lines at all, the initial state is loaded from configuration memory and not dependant on any delay in set/reset. As the clock is not propagating to the SRL until all of them are configured then I think they all will start in proper sync. The only requirement is that the first CLK pulse comes to all SRL at the same time - if they CLK inputs are on the same GCLK I think this is always the case. Besides that Xilinx is using the SRL in seveal designs that require sync starting and there is nothing special done. So no worries. But it was a good think to bring to notice, in some cases this could be and issue. As example if the SRL shift loop includes flip-flop that use async reset, etc.. Antti PS thanks again for your Verilog code, I think I add this just as example of verilog coding - your header already contains the disclaimer that it is not fully tested/verified. As verilog example I think its brillant :)Article: 81621
Eric wrote: > I have enough pins (barely) that each FPGA n can have 14 DDR LVDS pairs in > from the n-1 fpga, and 14 DDR LVDS pairs out to the n+1 FPGA. We partition > these in the following way: > 1. 5 in / 5 out are used for the broadcast data bus > 2. 5 in / 5 out are used for the aggregate data bus Why not use a single bus for both? Simpler and higher bandwidth (or lower clock rate). For example you can allocate fixed bandwidth to each fpga by allocating slots in the data stream. The slot that is used to transfer data on the ring from FPGA N to the master FPGA will be unused between the master and and FPGA N so you can use the same slot to transfer data both ways. This static scheduling actually looks a little bit like a jtag shift register: The master shifts in data into the N fpgas. After N cycles each fpga reads the data from its register and replaces it by its own data that is to be sent to the master during the next shifting operation. Kolja SulimmaArticle: 81622
What about using mif-files (memory initialization files) ? Rgds AndréArticle: 81623
Mark McDougall wrote: > In reference to the following code snippet: > > always @(posedge ata_dior) > begin > dout = mem[ addr ]; > dout_en = 1; > end > > always @(posedge ata_dior) > begin > dout_en = 0; > end > Are you sure of the code ? It looks like something typically wrong (the result is impredictible -race condition- since it depends on the order the always blocks are evaluated. BertArticle: 81624
Make sure you selected the exact correct device. OTOMH, some old UP boards have two devices (cpld + fpga) and a switch to select which one is hooked to the JTag connector... There is a command to scan the JTag chain. Jos? Luiz Martins wrote: > Hi folks, > > > I'm facing one problem that is driving me crazy... > > The error is the following: > > Error: JTAG ID code specified in JEDEC STAPL Format File does not > match any valid JTAG ID codes for device. > > I'm using one ALtera University Program with ByteBlaster MV Cable on a > Windows XP machine. > > This is my first project in FPGA... I read almost everithing about > ByteBlaster and Quartus II configuration, and nope... > > My cable is installed, and everytinh else... > > Thank you very much in advance. > > > JL Martins
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