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I should develop a program for my embedded system based on microblaze. Where I can find a good manual with also Xilinx types? Thanks MarcoArticle: 81151
Hi Swamy, swamydp@yahoo.com wrote: > Hello Brendan > > Thanks for the reply. When we enter a frequency for the primary input > in Xpower, for example 1 Mhz, does it consider the input to be a square > wave ? Yes. > My primary inputs do not toggle every cycle, so the term > "frequency" is confusing to me. any clarification is greatly > appreciated. I'd suggest assessing your primary i/ps' average transition rate over a period of time and inferring frequencies from that. Brendan > > > Thanks > swamy > > Brendan Cullen wrote: > > Hi Swamy, > > > > swamydp@yahoo.com wrote: > > > > > Hi > > > > > > what algorithm does xpower use to calculate the freqency of > internal > > > nodes in a netlist ? is it some kind of transition density > propagation > > > but that method requires activity factor for primary inputs and > also > > > probabilities of primary inputs. > > > > > > Also is the interconnect power dissipation taken into account ? > > > > The most basic method is through user i/p. Others include importing > > simulation information and also the use of a probability algorithm in > how > > primary i/ps are propagated. > > > > The interconnect power dissipation is definitely taken into account. > > > > Brendan > > > > > > > > > > > Thanks for any help > > > swamyArticle: 81152
What you are missing is that serial distributed arithmetic has the
signal input presented serially. For an N bit input, it takes N clock
cycles per sample to compute the filter output. By using two similar
serial filters, you can process two bits per clock cycle, and therefore
achieve twice the sample rate for a given clock period. therefore by
roughly doubling the hardware (not quite doubled, but that is another
post), you get double the performance. This is the classic sample rate
vs area tradeoff. Note that the latency, measured in sample delays is
not appreciably changed. There is a tutorial on distributed arithmetic
on my website at http://www.andraka.com/distribu.htm which you may find
helpful to understanding what distributed arithmetic is, and why this is
true.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 81153
anup wrote:
Anup, in FPGAs, without going to extraordinary lengths, you get one
pipeline stage per add (those extraordinary lengths cost more area than
simply duplicating the adder and processing two samples at once). At
the time Greg's article was written, a highly optimized fpga design done
by someone very skilled in the craft, had a maximum clock rate quite a
bit less than 100 MHz, and that was for an extensively pipelined design.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 81154hi The address map will be (i think) depending on hardware implementation. What I need to implement is - BRAMS are shared to each uBLAZE. physical address will (preliminarily) be BRAM1 : 0x0000 - 0x3fff, BRAM2 : 0x4000 - 0x7fff. yes, logical address will (preliminarily) be uBlaze1 - BRAM1 0x0000-0x3fff - BRAM2 0x4000-0x7fff uBlaze2 - BRAM2 0x0000-0x3fff - BRAM1 0x4000-0x7fff For example, programmer writes 'ld rD, rA, 0x5000', then the MMU directs the path to BRAM2 (using the switch) and perform the load instruction. I am wondering and investigating if this is possible.......hope be possible. regardsArticle: 81155
pasacco wrote: > hi > > The address map will be (i think) depending on hardware implementation. > > What I need to implement is > - BRAMS are shared to each uBLAZE. > > physical address will (preliminarily) be BRAM1 : 0x0000 - 0x3fff, BRAM2 > : 0x4000 - 0x7fff. > yes, logical address will (preliminarily) be > > uBlaze1 > - BRAM1 0x0000-0x3fff > - BRAM2 0x4000-0x7fff > > uBlaze2 > - BRAM2 0x0000-0x3fff > - BRAM1 0x4000-0x7fff > > For example, programmer writes 'ld rD, rA, 0x5000', then the MMU > directs the path to BRAM2 (using the switch) and perform the load > instruction. > I am wondering and investigating if this is possible.......hope be > possible. > > regards > Hi, You don't need a MMU for this. You should only invert address bit 17 from uBlaze2. Although is not easy to do directly in .mhs file it's still possible. GöranArticle: 81156
RobJ wrote:
>I think the basic idea is that if you have a 51-tap FIR filter, for example,
>you need to do 51 multiplies per sample. The two extremes of the size/speed
>options are:
>
>1. Use one multiplier 51 times sequentially.
>2. Use 51 multipliers in parallel.
>
>
Rob, DA splits the problem up differently. With DA, you compute the sum
of all the 1 bit x N bit partial products for the first input bit, and
on the next clock the sum of all the 1xN partials for the second bit and
so on. The partials are then scaled and accumulated. The throughput is
increased by computing more than one 1xN partial product at a time.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 81157"Sea Squid" <Sea.Squid@hotmail.com> wrote in message news:423a48c8@news.starhub.net.sg... > Thank you Jim. > > I was aware that data2mem takes in a FULL bitstream of my compiled design, > and > output an updated FULL bitstream of the design. Since I am using a Virtex > 6000, the > time required to configure the FPGA becomes intolerable. > > I am able to wrtie automation scripts to employ the "small bit manipulation" > trick to > compare two bitstream and get a differential partial bitstream, but I am > concerned > whether this is the right approach. > > Besides that, is it possible to automate the Impact to configure the FPGA, > for example, > 1 configuration per 5 minutes, since I intend to do some exhaustive test of > all the 1000 > input vectors. You can run IMPACT in batch mode and control the time interval between configurations via a script. HTH, Jim jimwu88NOOOSPAM@yahoo.com (remove capital letters) http://www.geocities.com/jimwu88/chipsArticle: 81158
>> I don't think this is relevant Ben, the license file is generated against >> the 12 hex digit MAC address of the ethernet card, not the IP address. > > This is partly true. If an IP address hasn't been set through DHCP, the > interface gets an 169.x.y.z IP address. However, at the same time, the MAC > address for the interface can for some reason not reliably be obtained > anymore - at least not by FlexLM. If you look at an altera license file it's generated against the MAC address (or dongle ID), the IP address has nothing to do with it. Nial.Article: 81159
uh... Yes I am trying to design a system, and need to design off chip logic including interfacing to the chip. Later I will move to design the PCB, and try to fit the system to the lowest power consumption. I cannot at this point say, "I've had problems with signal noise using this part in past design xxx2000, so I'll go with this other part instead. Or say connecting the board components caused this failure last time, so I know to do it the other way." I would like to be able to say, "These sets of tools works really well, needing Chipscope for this, ModelSim for that, and Architecture Wizard, iMPACT for this that and the other ... and they helped me get the design done much faster for this situation." Anyway, I'll start with AND gates, and the ISE tutorials. One thing I don't really understand is what the EDK does for me aside from the fact that sources can be written in C and run using the on chip microblaze processor. This is still magic to since I don't really understand the underlying architecture of how instructions are being executed. I was hoping get a prototype within two months, so you get to laugh at how a clueless nob asks stupid questions and says stupid things as I progress. I'll try and do as much of the homework before pesting.. ;-). Thanks for your help, -HTArticle: 81160
First of all I do not have any experiance with FPGA's because my background is software programming. I wonder if anyone has some experiance with FPGA's AND image processing. What we would like to do in our diploma work is to get a stream from a dcam compatible cam and process the stream on an FPGA. The FPGA should be on a PCI board and our School only has the tools for Xilinx. As we do not have any money for our project we will have to look for a low cost PCI card, which should not be a problem but the board have some limitations of course. So we won't find a board with PCI and 1394 on it. We will therefore concentrate on a PCI board with a Xilinx FPGA, but the we do not jet know how to get the images from the cam to the FPGA and out. Has someone experience with 1394 IIDC (Dcam) and FPGA's? Does anyone about single chip that could handle both 1394/IIDC? If not would it be hard to handle the whole protocol ourselves? unexperianced on fpga and vhdl) Any suggestions welcome Thanx Nicolas SchwarzentrubArticle: 81161
On Fri, 18 Mar 2005 11:47:32 +0100, Winfried Salomon <salomon@uni-wuppertal.de> wrote: >>But I can see the "optimized" circuit in RTL-viewer. Very strange, there >>are 8 input and 8 output data lines, in between 8 D-FFS FDE. In Simulink >>I have only one line type boolean. When I change line type to 1 bit >>unsigned integer, it changes nothing. I don't know what to do. Sorry, your problem is unlike anything I've ever seen with System Generator. Probably best to get in touch with Xilinx. Good luck, GregArticle: 81162
On Wed, 16 Mar 2005 22:48:30 -0500, vax, 9000 wrote: > Hi list, > I don't have ethernet connection though I do have an ethernet card > installed. My computer can boot either with linux or win XP. I have dial up > connection under linux only. I downloaded ALTERA software version 4.2 > (yeah, overnight dialup), obtained the license (with an arbitrary ethernet > number), and copied the files to windows partition and installed. > The problem is now that under XP, when I run the software it does not > think the license is a valid one. My question is whether I really need > ethernet connection under XP to run ALTERA. If I obtain another license > with the correct ethernet card number I have, will this license be valid > when I don't really have ethernet connection? > Too tired today to do the experiment. I will appreciate it if you have a > quick answer. Otherwise I will have to do the experiment and report the > result here. > > vax, 9000 It's the MAC ID that is used. To get it under Linux all you have to do is ifconfig eth0 The HWaddr is the number you need. It doesn't matter if the card is up or not.Article: 81163
The Xilinx memory generator tool generates ucf files that have lines in them such as: NET "ddr1_top0/data_read0/fifo*_wr_addr(*)" MAXDELAY = 2350ps; I get parsing errors on both the / and (). I need to replace with _ and <> like: NET "ddr1_top0_data_read0_fifo*_wr_addr<*>" MAXDELAY = 2350ps; Is there a setting for this somewhere? Thanks SteveArticle: 81164
"Jezwold" <edad3000@yahoo.co.uk> schrieb im Newsbeitrag news:1111091786.492134.149610@f14g2000cwb.googlegroups.com... > I quite agree with John_H its a mistake to compare FPGA functionality > and CPU functionality,they are just fundamentaly different things.I > also think its a mistake to implement a CPU in a FPGA but I'll prolly > get flamed for saying that. Processing power isnt only defined by clock frequency. Regards FalkArticle: 81165
Hi, I'm evaluating low cost FPGA's for a new design starting end next month. Besides XC3S2000, EP1C20 and EC33 (I know, the EP1C20 is much smaller than the other 2), I was looking for other 90nm families. I found XC3S1500E, EP2C35, but no Lattice anymore. I wonder about the availability of the XC3S1500E and EP2C35. Has someone seen samples yet, knows something more how they compare (performance, pricewise). What about SW Tool support? Regards, LucArticle: 81166
On Thu, 17 Mar 2005 21:16:49 +0000, dave <dave@dave.dave> wrote:
>Contrary to what you may think there is a market for
> Ghz speed flexible FPGAs.
I don't doubt it, but I suspect the market is unlikely to be
satisfied with the cost/performance compromise.
Every gate in an FPGA costs...
- the gate itself (or LUT, or whatever)
- programming infrastructure to allow you to
configure it
- programmable routing - that means switching matrices
- probably, some unused stuff around the gate because your
chosen function doesn't fully occupy the FPGA cell (logic
block, slice, whatever)
All these increase die area and therefore cost-per-function;
some worsen signal delays as well. By contrast, a gate on
a custom device is just that: a gate and some hardwired
routing. It's sure to be faster than the FPGA equivalent.
There have been a few attempts, over the 20+year history
of FPGAs, to introduce more ASIC-like structures in FPGA
fabric. Most have failed horribly - remember Pilkington?
However, you can get amazing bang-per-buck in an FPGA if
you use it to solve the right sort of problems. Any DSP-ish
problem that keeps a lot of arithmetic units busy for a lot
of the time will be a good candidate. Simple bit twiddling
is always much faster in FPGAs than in programmable CPUs -
try writing a piece of C to do this...
reg [15:0] R;
...
R = {R[15:12], R[2:0], ~R[11:8], R[7:3]};
It's almost free in hardware, messy and slow in software.
And then the FPGA vendors have been very ingenious in adding
a few dedicated functions that make it easier to map common
problems on to the FPGA fabric. Embedded multipliers and
RAMs are obvious examples. SERDES on I/O pins allows you
to fan out a multi-GHz input to a much slower but wider
data path in the FPGA fabric, and achieve stuff that would
be impossible in software.
So, although I sense your frustration, things are probably
the way they are for a good reason; and if you want 2GHz CPU
then you better go and buy one from the usual suspects.
I imagine that there will always be a factor of 10 difference
between the fastest you can do a dedicated function in ASIC
and the speed you can do the same thing in regular FPGA fabric.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services
Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Article: 81167Hi Tommy Well I'm working on a Transputer cpu (which originally ran Occam) as well as the compiler for it. Occam later went to U.Oxford and turned into HandelC since they recognised that Occam could be used to model SW and HW processes. My view as I stated often in the NGs is that while Occam is good for Par message based programming, it wouldn't ever be my choice to describe HW except in a very general way at the spec stage or as a co HW-SW harness . I believe SystemC & other xxxCs also includes CSP basics. Also I realized that the Transputer process scheduler is a hop & skip from an event wheel but with a much more limited set of semantics so it never quite made it as a direct HW simulator but most Transputer projects were essentialy HW like and usually DSPish. I like the C syntax as a user, but as a compiler writer, the language is a total dog as it is far harder to describe than Verilog or VHDL although the Hanson-Fraser Lcc book helped me out on that. Still I am combining Verilog with Occam & C as the main language for the new Transputer. Generally C type seq programs would remain in C. The Verilog syntax comes into play to describe very par HW objects using the cycle model and later the event driven model. Occam comes into play more at a system level for combining message passing seq (C) /par (HDL) blocks. This is somewhat experimental and counters SystemC, SystemVerilog or VHDL to some extant. The parser essentially allows all constructs of Verilog, Occam & C to be interwtined in sometimes meaningless ways, so a mixed Verilog-C object would not be exportable to another Verilog or C tool, not sure if that matters, its probably inevitable. But you could import modules & functions. None of this would make any sense outside the Transputer env, as it pushes the idea that to some extent HW & SW form a continuum where algorithms can slide between HW & SW as performance demands. Esp useful to algorithms that naturally might fall into an FPGA as HW but might also be described as HDL or Occam code and just run as SW for lower cost but only possible if cpu supports processes, events, messages etc. The reverse is that SW can be moved from C to C-Occam and perhaps on up to HDL and synthesized into HW directly. Another alternative available only in Transputer systems is to increase the cpu count and spread SW process around to defer having to rewrite as HW. If you have a few 100 cpus, you might never want to rewrite as HW period. Now some might call that a HW simulator, but I might just call it an application. The alternative approach of trying to figure how to parallelize seq C directly into HW or onto fancy superscaler cpus makes no sense to me as it avoids using the par operator when it can be used in so many places. even if only to express "seq order don't care". Anyway I am in the middle of getting the compiler to emit asm for the Transputer and also to continue development of the C-ISA simulator, C-RTL simulator, and Verilog models. They are so intertwined that the C-ISA simulator is potentially the runtime for the compiler when hosted on a PC. It will be awhile before I can demonstrate the whole thing, but parts will come out soon enough. Looks like you are already convinced too, now another few more bods to go. regards johnjakson at usa dot comArticle: 81168
[...] >Hi henrik [...] Hello, design? :) >I am not sure but is this got something to do with the DONE pin not >going high. I dont know abt platform studio but then with Project >navigator there is a setting which drives the done pin high that is if >the done pin in the circuit is not connected to a pullup resistor. [...] Yeah, but I can't seen to find any settings that does this. I am pretty new to this. :) Anyways, I powered off the board and soldered a 10kOhm resistor from the DONE-pin to Vcc. And it actually worked after I powered it on again and programmed it. >Hope this helps. [...] I hope so too. Only time will show if the pull-up resistor did the trick. ;-) -- HenrikArticle: 81169
JJ wrote: > Hi Tommy > > Well I'm working on a Transputer cpu (which originally ran Occam) as > well as the compiler for it. Occam later went to U.Oxford and turned > into HandelC since they recognised that Occam could be used to model SW > and HW processes. -snip- > > johnjakson at usa dot com > Quote from a former co-worker, who had to maintain a legacy product that used transputers: "Oakum is something you stuff into cracks in boats, not a programming language". Not that I've ever actually _used_ Occam, it was just too good a quote to pass up. -- Tim Wescott Wescott Design Services http://www.wescottdesign.comArticle: 81170
Hi Luc, > I wonder about the availability of the XC3S1500E and EP2C35. > > Has someone seen samples yet, knows something more how they compare > (performance, pricewise). EP1C20 is in full production, the EP2C35 is sampling with about a 4-week lead time if the disti's don't have any stock, the XC3S1500E has only been specced yet and I haven't got a clue about the Lattice part. The EP2C35 will be more expensive than the EP1C20, with slightly higher performance in terms of routing and LE performance. The addition of HW multipliers is handy if you use them. That's all I can say at the moment. Don't know how this all stacks up against X and L. > What about SW Tool support? The EP1C20 is fully supported in Quartus, using final timing models, while the EP2C35 has preliminary support (i.e. no bitstream generation) in the standard version of Quartus 4.2. If you have a compelling reason to generate an EP2C35 bitstream right now there's ways to accomplish this already though. The EP2C35 will be fully supported in Quartus 5.0, released sometime end of April. The XC3S1500E may already be supported in Webpack 7.1, but I'm not sure. Best regards, BenArticle: 81171
Has anyone actually purchased an XC4VFX12 yet? They supposedly went on the market in January; parts don't show up in Xilinx online store, distributors don't stock them yet; Xilinx sales rep is "checking", but wasn't particularly encouraging or knowledgable. Paul Smith Indiana University PhysicsArticle: 81172
> Have you done aggressive field (impulse & RF burst) testing yet ? Again, yes. > This would be on as near a real field-install as practical. > > Do you have a stats map, of the failure count/installed unit/site/time ? > [ ie these are truly random failures ?] Again, yes they are random. > > When all else fails, you can always blame Alpha particles ? No, this is not an option. After running an automated test for the last 24 hours, finally one part on my test unit failed. Because the software would try and program the devices after a fixed amount of time in order to detect the fault, I am not sure if the pins were in this state at the time of the failure. However, Looking at the the control pins, HDC is high, LDC is low, done/pgm' is low and init is low. I increased the reset time to over a second with no luck. I tried reloading the device over 50 times with no luck. This is what we are seeing. I am not sure why it entered this mode and if it had anything to do with my testing, or was just its time. I have left the device in this state is anyone has ideas on further test.Article: 81173
board : Avnet Xilinx Virtex-II Development Kit fpga : Xilinx Virtex II Pro 20 ==> 2 ppc405, and so on ... problem : avnet includes a ucf file for this FPGA stating the physical pinning for an externally attached ddr sdram of 128MB With Base System Builder Wizzard in EDK/XPS I create a design for the virtex II Pro 7, they haven't got one for the 20 ... Since the 7 and the 20 FPGAs have the same package I suppose their pinning should also be the same, this I can conclude out of the UCF files Avnet gives with the board for either 7 or 20 ... After my design wizzard has finished and I have attached a ddr 64x16 controller for the DDR the UCF file doesn't match the one provided by avnet ... So far not so good ... I use the controller anyway, and bring out my signals out of the processor design towards the top level VHDL design created in ISE ... I bring out those pins with buffers attached to them out of the toplevel design and try both constraints ... the one BSB has created and the one discribed in the UCF given with the board. When I address the controller, it returns 0xffffffff .. meaning there is no connection with the DDR SDRAM Uptill now I have used the shared bus SDRAM, but since i need my PCI connection and I cannot transmit data into the Virtex without using the SRAM connected to the pci bridge, and since both 2MB SRAM and 32MB SDRAM are on a shared bus, this will affect speed, because I need a big memory to buffer in and output ... therefor I want to connect the 128MB DDR SDRAM to the PLB bus connected to the PPC controlling transfer In and Out the card. My question : how can I connect the DDR mem ... Did I do something worng, has someone encountered the same problem with this board thx in advance, PaoloArticle: 81174
In article <423699e0$1@clear.net.nz>, Jim Granville wrote: > Andrew Smallshaw wrote: >> On a slightly different note, does anyone know why most serial protocols >> use simple voltage levels to denote a logic 0 or 1? I admit I'm no expert >> but I recall from my A-level electronics an edge-triggered system where a >> '0' would be (say) low-followed-by-high whereas a '1' would be >> high-followed-by-low. Yes, this means _at_least_ twice as many voltage >> transitions per bit but I would have thought that given its greater resilience >> mismatched clocks or any stray capacitance it would be worth the trade off. > > This is used already, and is called Bi-Phase or Manchester encoding, > for the two phase variants of this Clock+Data Scheme. > -jg Thanks for that but I already knew it existed: I wasn't trying to pretend I had invented something. But my original question was why isn't it more widely used? Hmmm... Manchester encoding. Is that another great thing my old University came up with? The battery on this laptop is about to expire so I've not got time for a Google search now... -- Andrew Smallshaw andrews@sdf.lonestar.org
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