Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Our experience is that you are basically right. But the markets perception is that there is a bit error rate for any MGT link. Xilinx have XAPP762 to help there customers measure it! We recently added hamming codes to a system but it has proved untestable (no errors yet!). But I still have to assume that there will be some in the life of the product. So I need to know whether once the Aurora is working, with channel up at both ends, Aurora can cope with an error on the comma K characters it is using. Katherine. Duane Clark wrote: > katherine wrote: > > All > > > > Does anyone have a feel for how robust aurora is? > > > > I have worked out a packet based protocol to put on top of aurora which > > will re-send packets which are corrupt at the receiver but what is the > > chances of the aurora system itself falling over? > > > > That is really a signal integrity issue. If you get errors, then you > need to investigate where the signal intergrity problems are (of course > after you verify that you are not using the Aurora interface > incorrectly). I have run many GBytes through the links without any errors.Article: 86851
Martin, We choose to show the products in their best mode, not their worst, so that may be a valid assumption. It may also be that we used the tools that are shipped with the product, I just don't know. Generally speaking, the synthesis tool may also be a factor in performance variations. Hopefully over the large number of test cases, the choice of tools becomes a minor effect, but sensitivity to tool usage is definitely something very real. I have heard from customers that at various times, one tool or another has been "superior." Our policy is to share all performance improvements in our synthesis tool with our partners, as we are not in the business of selling synthesis tools, but rather using our own synthesis tool refine and evaluate our architectures. Just as for any individual customer, one FPGA or the other may be "superior" in terms of performance, they are close enough in performance that only by evaluating a large number of designs can the trend be seen. But my posting was not so much about the speed debate, but more about the overall product superiority: static power 1-5 watts less, SI for ground bounce up to 8X less, added features (SSIO, DSP48, E-MACs, PPC, MGT, FIFO-BRAM, FRAME_ECC, etc...). Austin Martin Thompson wrote: > Austin Lesea <austin@xilinx.com> writes: > > <snip> > >>http://www.xilinx.com/products/virtex4/overview/performance.htm >> >>is a good review of V4, which illustrate how we beat all other FPGAs >>in EVERY category. >> > > > Interesting - why did you not use Synplify for the Altera side of > things - was it worse than Altera's synthesiser? > > Cheers, > Martin >Article: 86852
Azam, There are demo pcb's I have seen for 333MHz DDR SDRAM. Austin azam wrote: > I was trying to determine the max frequency that can be clocked thru > the Virtex-4 FPGA pins. While referring the Virtex-4 User Guide the (DC > and Switching characteristics) Section of the book has blank columns. > Although the Virtex-4 FPGA Handbook mentions the capabiltiy to meet > different I/O standards, I was wondering has anyone been able to > exercise the I/Os of the Virtex Family above 300MHz. > > Thanks > -Azam >Article: 86853
Hi all, We are trying to implement QAM 64 modulation on a 1Gbps signal to fit in a 200MHz bandwidth using FPGA's. We are currently looking at using an FPGA to split the 1Gbps stream in two streams of 0.5Gbps using Serial-Parallel, and using another set of 2 Serial-Parallels to split the each of the 2 streams into 3 portions each. The three signals can then be fed into a 3 bit DAC (implemented within the FPGA) to receive an output signal from the FPGA. We are currently looking at buying the Altera UP3 education boards, or some inexpensive evaluation boards that can be used to implement this functionality. Can you make any recomendations on some boards for this application. Are there any tutorials for FPGA newbies that you know of, and specifically I need help with implementing the Serial-Parallel and the 3 bit DAC. I am also open to other suggestions/approaches, but we are hoping to keep this thing as simple as possible. Thanks in advance, KaaliaArticle: 86854
Kolja, You are correct. The capacitance of the interconnect certainly dominates as far as speed is concerned (over any advantage of a faster transistor in SOI). What is also interesting, is if you reduce the capacitance by 10% (ie using lo-K), the speed only goes up by 5%. Thus, the effect of lowering the K can actually be offset by pushing the transistor process in the fabs to get all the speed back again (as a 5% faster transistor is easy to do). That is why we are neither for, nor against lo-K. For us, it just doesn't matter! Toshiba uses lo-K. UMC does not (for V4). The processes are adjusted for equivalent performance. And, there is hardly any difference in dynamic power after all is said and done (one datasheet covers both fabs). Probably the biggest process technology improvement in V4 was the use of triple oxide: the thick mid-ox device used for memory resulted in much less static current, and also in superior SEU resistance to upset. Regular use of 90nm 6T cells for memory means that the probability of upset is worse than it was in 130nm. It also provided excellent speed performance and low leakage for the pass-gates. Additionally, the lifetime of the FPGA remains at 20 years, when Intel is quoting a 7 year life for their 90nm processors. By using all 90nm transistors, the reliability is compromised, as we are beginning to see "wear out" effects for the technologies below 90nm. By keeping the memory cells and pass gates at a thicker oxide, we also are using far fewer 90nm transistors, and increasing the reliability of the hardware itself. There are also substrate implantation techniques that can also be used for soft errors, which would cost far less that redesinging for SOI. Austin Kolja Sulimma wrote: > Austin Lesea schrieb: > > >>In order to remove or minimize the variation in timing in SOI from the >>floating wells, one needs to add taps. The addition of the taps to >>every well, results in the area increasing dramatically. That makes the >>FPGA cost too much, hence the process is not commercially viable. This >>has been one of the reasons for its non-use. > > > Also, without knowing as much detauls as austin, I suspect that in a > design as heavily dominated by interconnect as an FPGA the area increase > results in longer wires which increases capacitance and therefore power > consumption and delay. This mitigates the two main advantages of SOI. > > Kolja SulimmaArticle: 86855
Katherine,
A properly designed link using any Xilinx MGT has 0 errors.
That is how they are supposed to work.
If you are running at some fixed, but small dribbling error rate, the
link is broken, or not designed properly.
As soon as you near the edge of the error rate curve ('waterfall curve',
anything can then cause you to fall over into the 1E-3 region:
inoperable (temperature, voltage, etc.)
Again, properly designed and implemented links have NO errors.
Having a small but dribbling constant error rate is evidence of a bad
link, or a badly designed link (too much loss, for example).
That is why when EDN magazine asked Xilinx for the MGT error rate, it
was stated as 0.
Just because the specification for a standard is 1E-12, is no reason to
do sloppy engineering.
Austin
katherine wrote:
> Our experience is that you are basically right.
> But the markets perception is that there is a bit error rate for any
> MGT link. Xilinx have XAPP762 to help there customers measure it!
>
> We recently added hamming codes to a system but it has proved
> untestable (no errors yet!).
>
> But I still have to assume that there will be some in the life of the
> product.
>
> So I need to know whether once the Aurora is working, with channel up
> at both ends, Aurora can cope with an error on the comma K characters
> it is using.
>
> Katherine.
>
>
> Duane Clark wrote:
>
>>katherine wrote:
>>
>>>All
>>>
>>>Does anyone have a feel for how robust aurora is?
>>>
>>>I have worked out a packet based protocol to put on top of aurora which
>>>will re-send packets which are corrupt at the receiver but what is the
>>>chances of the aurora system itself falling over?
>>>
>>
>>That is really a signal integrity issue. If you get errors, then you
>>need to investigate where the signal intergrity problems are (of course
>>after you verify that you are not using the Aurora interface
>>incorrectly). I have run many GBytes through the links without any errors.
>
>
Article: 86856Hello All, I spent few weeks researching different books and my experience in verilog to write this detailed article. Hopefully, it will be useful to you. Please check it out and let me know your feedback. http://www.inno-logic.com/tech-forum/viewtopic.php?t=20 Regards, Pistony2kArticle: 86857
Hello, does anyone know what is the max Sample Rate used in the Signal Tap utility under Altera's Quartus? Thanks, joeArticle: 86858
On Wed, 29 Jun 2005 12:43:08 +0200, "Antti Lukats"
<antti@openchip.org> wrote:
>"Sylvain Munaut" <com.246tNt@tnt> schrieb im Newsbeitrag
>news:42c27a2c$0$29635$ba620e4c@news.skynet.be...
>>
>> Hi Antti,
>>
>> >
>> >
>> > if in hurry then you must either use TQFP100 package or BGA
>>
>>
>> Finally I think I wont use PLD at all.
>> A RC filter for "quick & dirty" pre-debounce and a simple 8bit µC
>> to handle to rest of the logic will do. It doesn't need to be very
>> fast anyway.
>>
>>
>> Sylvain
>
>HAHA, that is good optimization!!!! from 500LE down to 0!
>with proper firmware you may not need the external debounce but it all
>depends sometime the rc network is good choice
>
>sure if there is no direct need for high speed logic then small flash micro
>is better choice.
>
>my current favorite is ATmega8 in QFN32 package, but thats all a matter of
>taste
>
>Antti
>
Here is a neat debouncer for the Atmega's (It does 8 keys at a time ,
PORTD in this example) written for AVR-GCC / WinAVR
Rgds
Carsten
/****************************************************************************
Title: Debouncing 8 Keys
Author: Peter Fleury <pfleury@gmx.ch> http://jump.to/fleury,
based on algorithm of Peter Dannegger <danni@specs.de>
Date: December 2003
Software: AVR-GCC 3.3
Hardware: AT90S8515 at 4 Mhz, STK200 compatible starter kit
Description:
Demonstrates debouncing 8 keys. The state of the eight keys is
sampled
four times using a timer interrupt. If a key is pressed longer than
four seconds, the corresponding bit in the key_press global variable
is set.
The main loop checks if a bit is set in this global variable and
resets
the bit.
Pressing the key connected to PIND2 increments a counter, while
pressing
the key connected to PIND3 decrements the counter.
The value of this counter is displayed using LEDs on PORTB.
*****************************************************************************/
#include <inttypes.h>
#include <avr/io.h>
#include <avr/interrupt.h>
#include <avr/signal.h>
#ifndef CTC1
#define CTC1 WGM12 // for compatibility with ATmega
#endif
#define XTAL 4000000L // Crystal frequency in Hz
#define DEBOUNCE 200L // debounce clock 200Hz =
5msec
/*
* Module global variable, informs the main programm when a key is
pressed.
* This variable must be declared 'volatile, since it is accessed from
* both interrupt und main loop.
*/
static volatile uint8_t key_press;
SIGNAL (SIG_OUTPUT_COMPARE1A)
{
static uint8_t key_state; // debounced and inverted key
state:
static uint8_t ct0, ct1; // holds two bit counter for each key
uint8_t i;
/*
* read current state of keys (active-low),
* clear corresponding bit in i when key has changed
*/
i = key_state ^ ~PIND; // key changed ?
/*
* ct0 and ct1 form a two bit counter for each key,
* where ct0 holds LSB and ct1 holds MSB
* After a key is pressed longer than four times the
* sampling period, the corresponding bit in key_state is set
*/
ct0 = ~( ct0 & i ); // reset or count ct0
ct1 = (ct0 ^ ct1) & i; // reset or count ct1
i &= ct0 & ct1; // count until roll over ?
key_state ^= i; // then toggle debounced
state
/*
* To notify main program of pressed key, the correspondig bit
* in global variable key_press is set.
* The main loop needs to clear this bit
*/
key_press |= key_state & i; // 0->1: key press detect
}
int main( void )
{
uint8_t count = 0;
TCCR1B = _BV(CTC1) + _BV(CS10); // clear timer on compare match, no
prescaler
OCR1A = XTAL/DEBOUNCE; // timer = 5 msec
TIMSK = _BV(OCIE1A); // enable Output Compare 1 overflow
interrupt
DDRB = 0x00; // use all pins on PortD for input
PORTD = 0xff; // with pull-up enabled
DDRB = 0xff; // use all pins on PortB for output
PORTB = 0xff; // turn all LED off
sei(); // enable interrupt
for(;;)
{
if (key_press & _BV(2) )
{
// key 2 pressed, increment counter
count++;
PORTB = ~count;
key_press = 0;
}
else if ( key_press & _BV(3) )
{
// key 3 pressed, decrement counter
count--;
PORTB = ~count;
key_press = 0;
}
}
}
Article: 86859On Thu, 7 Jul 2005 18:57:09 +0200, "Elektro" <blabla@bredband.net> wrote: >Hello > >I’m looking for some good book about bit serial programming. I’m interested >in learning about it to implement functions bit serially in VHDL. > >The only book I have found is “VLSI Signal Processing: A Bit-Serial > Approach”, but I don’t think it’s available any more. > >Or if you know of some page on the web that has some info on the subject. Here is a search that found 4 copies when I ran it: http://dogbert.abebooks.com/servlet/SearchResults?y=10&tn=VLSI+Signal+Processing%3A+A+Bit-Serial+Approach&x=30 Philip Philip Freidin FliptronicsArticle: 86860
Elektro wrote:
>Hello
>
>
>
>I’m looking for some good book about bit serial programming. I’m interested
>in learning about it to implement functions bit serially in VHDL.
>
>
>
>The only book I have found is “VLSI Signal Processing: A Bit-Serial
> Approach”, but I don’t think it’s available any more.
>
>
>
>Or if you know of some page on the web that has some info on the subject.
>
>
>
>/Sweden
>
>
>
>
That is about the only book I've seen on bit serial. It is certainly the
only thing I've seen that has comprehensive coverage of the entire
topic. It is not really easy reading, but it does contain good
information. You can find it used if you look. It took me about 3 months
to find a copy, but when I did there were suddenly 4 or 5 available.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 86861Resampling with small integer ratios can be pretty staightforward, like a rate change of 3/2, upsample by 3 -> LPF -> decimate. However, it's not as simple when it's a ratio of large integers or some arbitrary new sample rate. I found one document on resampling: http://ccrma-www.stanford.edu/~jos/resample/ Is this how others are implementing resampling for these cases? Multiplying the input samples with a windowed, weighted sinc at the new sample frequency? Thanks for any insights, BradyArticle: 86862
Martin Schoeberl wrote:
>I'm playing around with sigma-delat ADC and DAC for audio. It's amazing
>how good this works without any active components. Just Rs and Cs.
>
>
The sigma-delta works really well, and the faster you clock it the more
equivalent bits you get. You'll have to parallel a bunch of pins to get
enough drive for an 8 ohm speaker, and you'll still end up with a
sizable loss due to the driver impedance. You could add a simple
transistor stage to each pin to boost the current up and still keep the
parts count low. The sigma-delta will drive a 600 ohm headset with no
problem (I did that with the shortwave radio demo shown on my website).
You can also drive a set of powered PC speakers through a single pin.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 86863Here it is: http://www.altera.com/niosrenewal --Alan remove.prefix.gcalac@altera.comArticle: 86864
On 7 Jul 2005 13:18:48 -0700, bgaughan@airnetcom.com wrote: >I found one document on resampling: >http://ccrma-www.stanford.edu/~jos/resample/ > >Is this how others are implementing resampling for these cases? I believe that polyphase filters are the method of choice at the moment. You might also post this on comp.dsp -- consistently high quality answers may be found there. GregArticle: 86865
Andy Peters wrote:
>I guess this is more of a Xilinx question than a VHDL question.
>Anyways, once again, I find myself wanting to set the value of a
>generic on the top-level of my chip design from the synthesis tool --
>XST, in this case -- either from the GUI or from the command line.
>
>I know I can do this in Precision ...
>
>So what's the magic incantation?
>
>Thanks,
>-a
>(devel (at) latke dot net)
>
>
>
Andy, for a long time none of the synthesis tools supported this. The
work-around I use is I create a separate file containing a VHDL package
with the parameters I want to be able to change in it, and then
reference the package in my main code. That way, you change the
parameters in the defaults.vhd package file and it gets reflected in the
real design. Here is an example:
in your design files that need the settings (just the top level design
if you then pass these down the hierarchy through generics) put the
library declarations:
library work;
use work.settings.all;
which makes all the constants (and functions too) defined in the package
available.
Then in settings.vhd you declare the package:
package settings is
constant in_coefs1:int_array(0 to 2):= (-4,-8,56); --v27
constant in_coefs0:int_array(0 to 2):= (-2,-4,32); --v27
-- constant in_coefs1:int_array(0 to 2):= (-4,-4,40); --v25,26
coefs
-- constant in_coefs0:int_array(0 to 2):= (-2,-2,24); --v25,26
coefs
-- constant in_coefs0:int_array(0 to 2):= (-1,-1,16);
-- constant in_coefs1:int_array(0 to 2):= (-2,-2,24);
-- constant out_coefs0:int_array(0 to 2):= (1,3,16); --v25,26
coefs
-- constant out_coefs1:int_array(0 to 2):= (1,4,12); --v25,26
coefs
constant out_coefs0:int_array(0 to 2):= (1,2,20); --v27
constant out_coefs1:int_array(0 to 2):= (1,3,16); --v27
constant in_matrix0: int_array(1 to 9):= (
in_coefs0(0), in_coefs0(1), in_coefs0(0),
in_coefs0(1), in_coefs0(2), in_coefs0(1),
in_coefs0(0), in_coefs0(1), in_coefs0(0));
constant in_matrix1: int_array(1 to 9):= (
in_coefs1(0), in_coefs1(1), in_coefs1(0),
in_coefs1(1), in_coefs1(2), in_coefs1(1),
in_coefs1(0), in_coefs1(1), in_coefs1(0));
constant out_matrix0: int_array(1 to 9):= (
out_coefs0(0), out_coefs0(1), out_coefs0(0),
out_coefs0(1), out_coefs0(2), out_coefs0(1),
out_coefs0(0), out_coefs0(1), out_coefs0(0));
constant out_matrix1: int_array(1 to 9):= (
out_coefs1(0), out_coefs1(1), out_coefs1(0),
out_coefs1(1), out_coefs1(2), out_coefs1(1),
out_coefs1(0), out_coefs1(1), out_coefs1(0));
constant cbits : integer := 7;
constant ibits : integer := 8;
constant in_divide_by : integer := 3;
constant out_divide_by : integer := 5;
end settings;
This gives you far more flexibility than generics do. I've even gone as
far as writing a 'C' application to automatically generate the
settings.vhd file as a result of entries in a windoze dialog box. A
package file generated by C, matlab or some other language capable of
trig functions or whatnot, or from an excel spreadsheet even is a way to
get tables of constants that are not easy to generate in synthesizable
VHDL into the design. That comes up when you have a synthesis tool that
doesn't recognize reals and you need a table of trig values to
initialize a ROM, for example. You can also use a VHDL testbench to
generate such a file, since the generating program doesn't go through
the synthesis (which means you can use reals).
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 86866
Paul Leventis (at home) wrote:
<basically, "mine is bigger">
*Sigh*, here we go again. Raw device speed isn't the whole answer, and
neither is
the list of device features. I could easily design a suite of test
circuits that could
'definitively' show either the stratixII or the virtex4 as being the
faster device, depending
on which one I wanted to 'win'. All that really proves is what I've
said for the past 12
years, which is if you really want to wring out the most performance
from a device you
MUST tailor your design to that device. Doing so will get you the
maximum speed in/ that/
device, but at the same time will generally hurt the performance in the
other devices that it
wasn't tailored to.
When deciding on a device, chose based on your comfort level with the
family and its tools,
and how well the feature set of that chip augment your design. Both are
good products, and
you won't go wrong with either as long as you pay attention to the
device architecture as you
develop your design.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 86867"greenplanet" <greenplanet@hotmail.com> wrote in news:1120716400.871859.69220@g49g2000cwa.googlegroups.com: > I've visited the xess website; however, there's only one example for > mouse and the source codes are in Spanish. Anyways, I tried to figure > out what those codes mean and downloaded the bitstream to the fgpa; > however, that doesn't work. I am not sure whether the code is not > working or I have set something wrong. Anybody has experience using > the PS/2 port of XSA-3S1000 board with XST 3.0? > If I just wanna read the mouse, do I have to initialize the mouse > first? If then, how? > > Yes, you have to initialize the mouse. Read this document for information on the PS/2 mouse protocol: http://www.computer-engineering.org/ps2mouse/ -- ---------------------------------------------------------------- Dave Van den Bout XESS Corp. PO Box 33091 Raleigh NC 27636 Phn: (919) 363-4695 Fax: (801) 749-6501 devb@xess.com http://www.xess.comArticle: 86868
Hi Joe, Since SignalTap is just like any other circuit in your FPGA, the answer would be the same as for, "How fast can a circuit run in my device?" It entirely depends on what else is part of the FPGA design, on what embedded memory SignalTap uses for buffers, how many signals you are watching, the device itself, and so on. SignalTap can slow down, or be slowed down by, the circuit it is inspecting. Practically, I haven't had much problem with SignalTap not being fast enough. Even in the cases where timing isn't met, I slow down the design sufficiently so it's not a problem, since SignalTap is only used in the debug phase for me. HTH -- Pete jjlindula@hotmail.com wrote: > Hello, does anyone know what is the max Sample Rate used in the Signal > Tap utility under Altera's Quartus? > > Thanks, > joeArticle: 86869
SELV = Safety Extra Low Voltage It's basically a set of safety standards that the transformer should meet. "vssumesh" <vssumesh_asic@yahoo.com> wrote: :Hello i bought a development board frm the ARM. It says that for safety :use SELV (safety extra low power supply). Whats mean by SELV. Can i use :home made power( using 7805 and 3.3V zener) supplies insted of SELV.Article: 86870
Hi, I'm using the Verilog-2001 exponential operator to do the following: `define NUM_COUNTER_BITS 8; parameter NUM_COUNTER_CYCLES = 2 ** (`NUM_COUNTER_BITS); When I simulate this in ModelSim 6.0a, launched from Project Nav. (ISE 7.1 SP3), NUM_COUNTER_CYCLLES = 5. However, if I use a parameter for NUM_COUNTER_BITS instead of `define, as shown below, NUM_COUNTER_CYCLES = 256, which is the desired result. parameter NUM_COUNTER_BITS = 8; parameter NUM_COUNTER_CYCLES = 2 ** (`NUM_COUNTER_BITS); What are the inherent differences between a parameter and `define directive that could this problem to occur. Thanks, NNArticle: 86871
Nju Njoroge wrote:
> Hi,
>
> I'm using the Verilog-2001 exponential operator to do the following:
>
> `define NUM_COUNTER_BITS 8;
> parameter NUM_COUNTER_CYCLES = 2 ** (`NUM_COUNTER_BITS);
>
> When I simulate this in ModelSim 6.0a, launched from Project Nav. (ISE
> 7.1 SP3), NUM_COUNTER_CYCLLES = 5. However, if I use a parameter for
> NUM_COUNTER_BITS instead of `define, as shown below, NUM_COUNTER_CYCLES
> = 256, which is the desired result.
>
> parameter NUM_COUNTER_BITS = 8;
> parameter NUM_COUNTER_CYCLES = 2 ** (`NUM_COUNTER_BITS);
>
> What are the inherent differences between a parameter and `define
> directive that could this problem to occur.
>
I tried it with ncverilog, and didn't get the bad answer. Is it
posssible that the ; at the end of `define is causing the problem?
Try this in your module:
initial
$display ("NUM_COUNTER_BITS = %d", `NUM_COUNTER_BITS);
Article: 86872Also kind of funny that they used a Quartus version three revisions old, and the latest ISE and Synplify? "Martin Thompson" <martin.j.thompson@trw.com> wrote in message news:uackzkp64.fsf@trw.com... > Austin Lesea <austin@xilinx.com> writes: > > <snip> >> http://www.xilinx.com/products/virtex4/overview/performance.htm >> >> is a good review of V4, which illustrate how we beat all other FPGAs >> in EVERY category. >> > > Interesting - why did you not use Synplify for the Altera side of > things - was it worse than Altera's synthesiser? > > Cheers, > Martin > > -- > martin.j.thompson@trw.com > TRW Conekt, Solihull, UK > http://www.trw.com/conektArticle: 86873
Yes, I read the document about the PS/2 mouse protocol. I wonder is that true that I must send all those commands as shown on the document to the mouse for initialization? In the example on xess website, it only sends the $F4 command to enable the mouse.Article: 86874
Jason Zheng wrote:
> Nju Njoroge wrote:
> > Hi,
> >
> > I'm using the Verilog-2001 exponential operator to do the following:
> >
> > `define NUM_COUNTER_BITS 8;
> > parameter NUM_COUNTER_CYCLES = 2 ** (`NUM_COUNTER_BITS);
> >
> > When I simulate this in ModelSim 6.0a, launched from Project Nav. (ISE
> > 7.1 SP3), NUM_COUNTER_CYCLLES = 5. However, if I use a parameter for
> > NUM_COUNTER_BITS instead of `define, as shown below, NUM_COUNTER_CYCLES
> > = 256, which is the desired result.
> >
> > parameter NUM_COUNTER_BITS = 8;
> > parameter NUM_COUNTER_CYCLES = 2 ** (`NUM_COUNTER_BITS);
> >
> > What are the inherent differences between a parameter and `define
> > directive that could this problem to occur.
> >
> I tried it with ncverilog, and didn't get the bad answer. Is it
> posssible that the ; at the end of `define is causing the problem?
>
> Try this in your module:
>
> initial
> $display ("NUM_COUNTER_BITS = %d", `NUM_COUNTER_BITS);
Thanks for the suggestion. I tried this below:
$display("NUM_COUNTER_CYCLES=%d", 2 ** `NUM_COUNTER_BITS);
and it does print out "NUM_COUNTER_CYCLES=256" in ModelSim. However, in
the actual waveform, the value is still 5 and the logic uses that
incorrect value.
The main reason I want to use `define directive is because I'm using a
`include file since this constant is used in many other modules.
NN
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z