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After reading every message I thought: 1) Use OPB_BRAM_IF_CONTROLLER 2) Generate a Dual Port Ram with Coregenerator of 19200 addresses with 4bit, and 9600 addresses with 8 bit. 3) Connect the 9600 addresses with 8bit ram to the controller. 4) Write the logic blocks to syncronize lcd display with 19200 addr. with 4 bit ram (already made). Now I have the following questions: 1) In what way could I connect controller with dual port ram??? EDK does it automatically, but I'm not able to view or edit ram hdl file and I can't customize it with logic block for syncronization. 2) When point 1 is done which C function should I use to perform read or write into ram? Xio_in8 and Xio_out8 ???? Many Thanks to everyone, specially for your patience! MarcoArticle: 84826
Hello, I've got some VHDL courses at university, i worked on rael time embedded design for years and i lost most of this knowledge. Anny one have a good links about how to re-start learnning VHDL Assic and Altera ? or anny low cost boards to start ? Regards. -- T.AArticle: 84827
"TA" <e2ext@free.fr> wrote in news:4299647c$0$6996$636a15ce@news.free.fr: > Hello, > I've got some VHDL courses at university, i worked on rael time embedded > design for years and i lost most of this knowledge. > Anny one have a good links about how to re-start learnning VHDL Assic and > Altera ? or anny low cost boards to start ? > Regards. I found some really good links by typing "VHDL Tutorial" into Google, it's got me upto speed quite quickly whilst waiting for books to arrive. In fact, I think I should have ordered some more advanced books now as I now know pretty much the basics. As for boards, I use this one: http://shop.trenz- electronic.de/catalog/product_info.php?products_id=64 but of course, there are many others to choose from.Article: 84828
My two cents are that i like to do breakup up my design in to modules first and come up with their interfaces and a rough schematic diagram then the deeper design and implementation is done in HDLs each module simulated tested etc then i fit them in the original schematic design. In this way i get a birds eye view of the whole design and the beauty of the schematic diagrams as well as abstraction of HDLs.Article: 84829
Ok, Thnx MichaelArticle: 84830
"TA" <e2ext@free.fr> wrote in news:4299647c$0$6996$636a15ce@news.free.fr: > Hello, > I've got some VHDL courses at university, i worked on rael time > embedded design for years and i lost most of this knowledge. > Anny one have a good links about how to re-start learnning VHDL Assic > and Altera ? I like the VHDL tutorial at http://www.acc-eda.com/vhdlref/index.html. It seems to cover VHDL more completely than most beginner's tutorials. > or anny low cost boards to start ? > Regards. > > -- > T.A > > -- ---------------------------------------------------------------- Dave Van den Bout XESS Corp. PO Box 33091 Raleigh NC 27636 Phn: (919) 363-4695 Fax: (801) 749-6501 devb@xess.com http://www.xess.comArticle: 84831
I dissagree with everyone else, and firmly believe that you should NOT learn VHDL and should just stick with schematic capture. Reasons: 1. I don;t need the competition; by not knowing VHDL you'll be stuck doing simple designs and will need my consulting services to do anything remotely complex. 2. WHy bother learn something new on your own? Now that you have your degree, you should just stick with learning new "team building paradigms" to make the MBA's in your company's work easilier. 3. The fact that all engineering curriculae now have a requirement to know vhdl (at least in the eastern US) shouldn''t worry you. Just make all the new hires do everything using s(c)hamtic capture., and they'll soon forget everything they learned about vhdl by the time they get their first layoffs. 4. By using schematic capture, you participate in the great globalization trends of outsourcing currently underway. Your management will soon realize that their native US design engineers are two decades behind the times and will immediately increase their bonuses by outsourcing your job to either India or preferably China, where the communist party can keep the chinese engineers in line. 5. Lastly, but not learning VHDL, one day your idiot vice president will get the briliant idea that all his engineers will learn systemC, just based on management-oriented marketing. Since he probably knows C, he figures by forcing everyone to use systemC (1) he'll finally be able to figureout and and thereby "help" everyone with their designs. (2) be able to hire a bunch of low paided and layed off software engineers to do hardware, and finally (3) just give the project to some REALLY low paid software engineers in India just becaise they know C. Allways glad to help (don't call us - we'll call you) Gary Pace wrote: > Hi Y'all : > > I have many years of experience with hardware design, software design & > implementation etc (i.e. I'm comfortable with C++, soldering or anything in > between) > > I'm using FPGA"s more and more. > > So far, I've used schematic capture exclusively. I use Altera's Megawizard, > so I know someone wrote some parameterizable VHDL behind this, but I still > think in hardware terms. > > I never learned VHDL, and wonder if it's worth it. > > My take has been that I am designing hardware - configuring the LE's and > interconnects and not writing algorithms. This seems to me to be mind-set > that best fits what I'm doing. > > I notice that a lot of people here refer to "code" - suggesting they have an > algorithmic mind-set > > What am I missing ? What would be some examples of something better done in > VHDL ? Are there examples of stuff that cannot be done in schematic ? > > Any comments will be appreciated. > > Gary > >Article: 84832
Greetings.
I did take time to search the archives, but nothing came up. I have
installed the base ISE WebPack for Linux on Debian using the file
'WebPACK_71_fcfull_i.sh'. I also did the update using the file
'ise_71i_ip_update1.gnutar.gz'. I think that was redundant, but it
should not matter. Here are some questions I have:
1) I am attempting to due the sample 'Traffic' VHDL tutorial found
in the Xilinx "Introduction to Programmable Logic'. When I get
to the Functional Simulation, I am suppost to select the item
'Test Bench Waveform'. As you can see in the screenshot *A*, that
item does not exist. Looking in the Xilinx install directory, I
do not see an executable or directory that corresponds to this.
I went ahead and selected 'VHDL Test Bench' and then received
some errors *B*. What am I missing?
2) I also attempted to do a web update and got the error dialogue
shown in *C*. I verified that the browser (Mozilla Firefox) is
in the dialogue box.
3) I also do not have the 'State Diagram' selection item. Why is
this not showing up for Linux?
4) Is there a Linux/WebPack FAQ somewhere that Google is not picking
up? I have got to believe someone else has ran into these.
Thanks in advance.
-Steve
*A*
ftp://ftp.realitydiluted.com/xilinx/webpack/errors/test-bench-selection.png
*B*
ftp://ftp.realitydiluted.com/xilinx/webpack/errors/test-bench-errors.png
*C*
ftp://ftp.realitydiluted.com/xilinx/webpack/errors/webupdate.png
Article: 84833Hi all, I want to implement a 6x6 keypad decoder in FPGA,i have got a reference design for that, but the limitation with this reference design is that it scans for only one key pressed at a time.It dosen't have the capabality of scanning for multiple keys at the same time. Can anybody help me out on this , how to go about this( any reference design) Thanks in advance, PraveenArticle: 84834
Subroto, I think the link you wanted is to Volume 2, Chapter 7 of the Quartus II Handbook: http://www.altera.com/literature/hb/qts/qts_qii52005.pdf See the Early Timing Estimate section in that document. Most users will want to use the default "realistic" estimate mode. This gives a best guess about the timing of a design with much lower CPU time than a full place and route. Error bars are +/-10% for a typical design vs. what you'll actually achieve after full place and route (and optionally physical synthesis). If you want bounds on "will the design almost certainly be this fast" and "is there any chance the design could be this fast", you can use the pessimistic and optimistic modes, respectively. The Early Timing Estimate is integrated with the same place and route engine we use for full fitting of a design, and it also models the impact of physical synthesis. It also obeys any floorplan constraints, pin-out, etc, in your design. For both these reasons, it is considerably more accurate than the typical post-synthesis speed estimate. As well, you can view where it thinks your logic should go in the Quartus floorplan editor, so it can help you optimize a floorplan quickly as well. Regards, Vaughn Altera [v b e t z (at) altera.com]Article: 84835
Hi Joe, I'd strongly recommend that you upgrade to Quartus 5.0 to use incremental compilation. Quartus 4.2 supported only incremental synthesis. That is the synthesis engine was incremental, but it wasn't integrated with an incremental capability in the fitter. In Quartus 5.0, both the fitter and synthesis support incremental compilation. Vaughn Altera [v b e t z (at) altera.com] <jjlindula@hotmail.com> wrote in message news:1117223974.687356.191100@g44g2000cwa.googlegroups.com... > Hi, I've recently upgraded to Quartus 4.2 and discovered the > Incremental Compilation feature. Has anyone had any problems using this > feature, anything I should know before trying it out? If anyone has > anything to share please let me know. I'm using Quartus 4.2 for my > Stratix design. > > Thanks, > joe >Article: 84836
Hi, I would like to use the Xilinx Spartan 3 DCI series source termination feature but the SSO guidelines from Pg25 of "DC and Switching Characterisics"(from the datasheet) leaves me thinking DCI is not supported for my IO standard and package. The IO standard is LVDCI_33. I.e. I want to use series termination for 3.3V LVCMOS signals. The part we are considering is XC3S50 TQ144. The table on pg25 shows a "-" for the number of SSO (simultaneously switching outputs) for LVDCI_33. Does this "-" mean 0 are supported, or it hasn't been characterised yet, or ?? Questions: 1) Is LVDCI_33 supported for the TQFP144 package? Also would be interested to know why it isn't supported.(extra pin inductance of the leaded packages??) Regards AndrewArticle: 84837
Hi Wenchang, > Quartus often gives amazing results. Yes, I mean that. Very > amazing. For example, when synplify shows that several muxes and > two 26-bit additions in series can only run at 66MHz in Startix II, > the post-Quartus results show that this design can run at 160MHz. > When synplify shows that a SRT Radix-4 divider can run at 160Mhz, > the Quartus results show that it can only run at 87MHz. Last wednesday though friday I ported a design to Stratix II. After I had finally converted all the technology-specific blocks to their Stratix II equivalents I compiled the design and got it to run at 55MHz. Bummer, I thought, my customer wants to have it running at 60MHz. Then I remembered: as of Quartus 4.2, the fitter runs in Auto mode, which means that it will fit as long as timing constraints are not met, and as soon as timing constraints are met, will stop and produce results. And I hadn't put in any timng constraints yet. So, Quartus had generated the netlist, semi-randomly emptied its bag of gates over the FPGA structure, did timing analysis, saw that the design was completely unconstrained, thought "Cool, I'm done", and reported 55MHz back to me. I already thought that 7 minutes of synthesis plus P&R for a 20.000 LE design was a bit fast... So, I just put in a clock constraint of 60MHz on the main clock, and fitted again. Had some coffee, came back after 10 minutes, and had a design running at 85MHz. So, it may very well be that you ran into the same trap. The adders are regular structures in the FPGA that are stitched together by hard-wired carry chains. These, by nature, will always be fast. I have no idea what the structure of an SRT Radix-4 divider looks like or what your pipeline level is, but if Quartus was in Auto-Fit mode and you hadn't put in any timing constraints, your end result would have been optimized for fastest fitter runtime, and not for best performance. Thus, my suggestion is to set a timing constraint when you're fitting in Auto mode (putting in timing constraints is always a good idea, of course), or to set the fitter to "Standard effort". Both can be done from Assignments->Settings. Clock and IO constraints can then be set from the "Timing Requirements and options" page, and the fitter mode from the "Fitter Settings" page. Hope this is useful to you. Best regards, BenArticle: 84838
While I have updated my project directories from ISE webpack 5.1 to ISE 6.1i , the following error occurs during MAP & there is no such error for new projects created in 6.1i.Please provide me the root cause & solution for the issue. Thank you. ERROR: FATAL_ERROR:Portability:PortDynamicLib.c:278:1.17 - dll open of library <C:/Xilinx_WebPACK/xilinx/bin/nt/libxildr.dll> failed due to an unknown reason. Process will terminate.Article: 84839
Haiii all,While I have updated my project directories from ISE webpack 5.1 to ISE 6.1i , the following error occurs during MAP & there is no such error for new projects created in 6.1i.Please provide me the root cause & solution for the issue. Thank you. ERROR: FATAL_ERROR:Portability:PortDynamicLib.c:278:1.17 - dll open of library <C:/Xilinx_WebPACK/xilinx/bin/nt/libxildr.dll> failed due to an unknown reason. Process will terminate.Article: 84840
"ANANTHARAJ.T.V." <anan_tv@rediffmail.com> schrieb im Newsbeitrag news:ee8e937.-1@webx.sUN8CHnE... > While I have updated my project directories from ISE webpack 5.1 to ISE 6.1i , the following error occurs during MAP & there is no such error for new projects created in 6.1i.Please provide me the root cause & solution for the issue. Thank you. > > ERROR: FATAL_ERROR:Portability:PortDynamicLib.c:278:1.17 - dll open of library <C:/Xilinx_WebPACK/xilinx/bin/nt/libxildr.dll> failed due to an unknown reason. Process will terminate. haaa! the 'Portability' appears in most cases where something goes BADLY wrong. its usually a dead end for the customer. get the latest version, or latest stable version and try again. the reason is 'unknown' you can only try some later version or service pack and hope the unknown reason doesnt exist any more anttiArticle: 84841
Hi all, In an SPI interface i have got 4 slaves and one master What i wanted to know is wether the master can assert two slave selects(SS_N) simultaneously OR is there a restriction that master can assert only one slave select. Does SPI standard dictate anything!!! Any comments on this would be appreciated. Regards, PraveenArticle: 84842
<praveen.kantharajapura@gmail.com> wrote in message news:1117455803.884889.181670@g44g2000cwa.googlegroups.com... > Hi all, > > In an SPI interface i have got 4 slaves and one master > What i wanted to know is wether the master can assert two slave > selects(SS_N) simultaneously OR is there a restriction that master can > assert only one slave select. > > Does SPI standard dictate anything!!! > > Any comments on this would be appreciated. > > Regards, > Praveen > I'm assuming that you have a common transmit and receive data line for all the slaves. If you simultaneously assert multiple chip selects what do you think is going to happen to the receive data line? Don't you think that there would be contention and thus garbage? If you want to broadcast to all slaves and have a mechanism to disable the receive data path from the slaves ... you could do that. SPI is not a standard ... it is a Motorola protocol that has become common place in the industry and as such you will get a lot of minor differences from implementation to implementation ... much like I2C. MikeArticle: 84843
Andrew, Don't know, but I'll find out when I get back into work tomorrow (Memorial Day tody in US). Austin Andrew FPGA wrote: > Hi, > I would like to use the Xilinx Spartan 3 DCI series source termination > feature but the SSO guidelines from Pg25 of "DC and Switching > Characterisics"(from the datasheet) leaves me thinking DCI is not > supported for my IO standard and package. > > The IO standard is LVDCI_33. I.e. I want to use series termination for > 3.3V LVCMOS signals. The part we are considering is XC3S50 TQ144. The > table on pg25 shows a "-" for the number of SSO (simultaneously > switching outputs) for LVDCI_33. Does this "-" mean 0 are supported, or > it hasn't been characterised yet, or ?? > > Questions: > 1) Is LVDCI_33 supported for the TQFP144 package? > > Also would be interested to know why it isn't supported.(extra pin > inductance of the leaded packages??) > > Regards > Andrew >Article: 84844
The TQ144 package is one of the worst packages for SSO. In the datasheet I happened to check (v1.4) there is a figure for LVDCI_33 although the TQ144 is not listed in the table heading. There are VRP and VRN connections there on the TQ144 to support DCI so I can only think that it will work to some extent. Generally mixing very high speed I/O and the TQ144 package is not good practise. If your I/O operates at lower speeds then setting the current drive on outputs to a lower value amy give nearly as good results as the DCI. Also does not increase the power consumption, and heat, like the DCI does. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "Andrew FPGA" <andrew.newsgroup@gmail.com> wrote in message news:1117432925.950059.58900@o13g2000cwo.googlegroups.com... > Hi, > I would like to use the Xilinx Spartan 3 DCI series source termination > feature but the SSO guidelines from Pg25 of "DC and Switching > Characterisics"(from the datasheet) leaves me thinking DCI is not > supported for my IO standard and package. > > The IO standard is LVDCI_33. I.e. I want to use series termination for > 3.3V LVCMOS signals. The part we are considering is XC3S50 TQ144. The > table on pg25 shows a "-" for the number of SSO (simultaneously > switching outputs) for LVDCI_33. Does this "-" mean 0 are supported, or > it hasn't been characterised yet, or ?? > > Questions: > 1) Is LVDCI_33 supported for the TQFP144 package? > > Also would be interested to know why it isn't supported.(extra pin > inductance of the leaded packages??) > > Regards > Andrew >Article: 84845
I've just moved from Quartus 4.0 to 5.0, re-generated a Nios design under SoPC Builder, and run the design through Quartus. The timing has gone from almost 90Mhz before to 72Mhz now. Anyone experienced similar speed-downs? AlanArticle: 84846
I was about to post that you should check that Quartus P&R is being
run with the same constraints that you synthesized with but
Ben did it for me. Both tools are strongly timing driven so
constraint differences can yield wildly different results.
Synplify produces a tcl file for you to source in Quartus that
will import the Synplify constraints. My memory is that the
file name is <design>_cons.tcl .
Synplify is doing it's best to estimate a constrained Quartus run.
Depending on the structure and routing load of your design, this
estimate can be low or high. Synplify has a very useful
constraint option for syncing up synthesis and P&R timing.
the "-route <delay>" option to define_clock can be used to squeeze (or
relax with a negative delay) the period of a clock for synthesis.
This additional routing estimation adjustment for the clock
domain is not passed through the <design>_tcl.cons file so the
P&R constraints remain correct. We recommend using up to about
a 10% of period value for the -route option. -route can also
be applied to individual paths using define_reg_{input,output}_delay.
- Ken McElvain
CTO, Synplicity, Inc.
Ben Twijnstra wrote:
> Hi Wenchang,
>
>
>> Quartus often gives amazing results. Yes, I mean that. Very
>> amazing. For example, when synplify shows that several muxes and
>> two 26-bit additions in series can only run at 66MHz in Startix II,
>> the post-Quartus results show that this design can run at 160MHz.
>> When synplify shows that a SRT Radix-4 divider can run at 160Mhz,
>> the Quartus results show that it can only run at 87MHz.
>
>
> Last wednesday though friday I ported a design to Stratix II. After I had
> finally converted all the technology-specific blocks to their Stratix II
> equivalents I compiled the design and got it to run at 55MHz. Bummer, I
> thought, my customer wants to have it running at 60MHz.
>
> Then I remembered: as of Quartus 4.2, the fitter runs in Auto mode, which
> means that it will fit as long as timing constraints are not met, and as
> soon as timing constraints are met, will stop and produce results. And I
> hadn't put in any timng constraints yet.
>
> So, Quartus had generated the netlist, semi-randomly emptied its bag of
> gates over the FPGA structure, did timing analysis, saw that the design was
> completely unconstrained, thought "Cool, I'm done", and reported 55MHz back
> to me. I already thought that 7 minutes of synthesis plus P&R for a 20.000
> LE design was a bit fast...
>
> So, I just put in a clock constraint of 60MHz on the main clock, and fitted
> again. Had some coffee, came back after 10 minutes, and had a design
> running at 85MHz.
>
> So, it may very well be that you ran into the same trap. The adders are
> regular structures in the FPGA that are stitched together by hard-wired
> carry chains. These, by nature, will always be fast. I have no idea what
> the structure of an SRT Radix-4 divider looks like or what your pipeline
> level is, but if Quartus was in Auto-Fit mode and you hadn't put in any
> timing constraints, your end result would have been optimized for fastest
> fitter runtime, and not for best performance.
>
> Thus, my suggestion is to set a timing constraint when you're fitting in
> Auto mode (putting in timing constraints is always a good idea, of course),
> or to set the fitter to "Standard effort". Both can be done from
> Assignments->Settings. Clock and IO constraints can then be set from the
> "Timing Requirements and options" page, and the fitter mode from the
> "Fitter Settings" page.
>
> Hope this is useful to you.
>
> Best regards,
>
>
> Ben
>
Article: 84847Michael, Another thread on the fpga-cpu group discussed creating such a gated write strobe by using the DDR output registers found in S3 & V2: http://groups.yahoo.com/group/fpga-cpu/message/2076 I also posted a first pass at a memory test using this technique for the Xilinx S3 starter kit here: http://groups.yahoo.com/group/fpga-cpu/message/2177 BrianArticle: 84848
IT took me quite a lot of time to realize that the newer webpack versions produces a fitter error without an error message. The newer versions (tried 6.3 and 7.1 with service packs) sometimes ignores one loc constraint in the ucf file. Foudation4.1 works perfekt with the same sources (vhdl & ucf). Any instance during the building process renames one output pin from touch_rx to touch_rx3, and the fitter places this pin to an unconstrained location (touch_rx has an ucf loc definition, touch_rx3 not). What a BS. Tried to open a webcase, and i got the following: Error May-30-2005 Registration is temporarily unavailable due to maintenance. Estimated downtime is 12 hours beginning at 6am PST. We apologize for the inconvenience. Does anybody has made similar experiences with the fitter ? The V7.1 GUI is worse, e.g. in 6.3 the sources could be enlarged and minimized easily. Boolean equations of the fitter report are less readable than in earlier Versions. MIKEArticle: 84849
Hi John, Thanks for your points, yes indeed we have chosen the TQ144 package for cost reasons at the expense of performance. In our application we generate a few clocks at 2 and 4 MHz. As standard practice I was going to series source terminate these clocks output from the FPGA. I was aware of the Spartan 3 DCI feature, so I thought it would be nice to make use of it to remove these resistors off the PCB. It would seem that I should do some IBIS simulations to show that reducing drive strength may allow me to remove the series source terminations completly? (I know there have been several posts in the past on how to do this). However, because of time constraints though I will stay in the 'dark ages' and just fit the series terminators to the PCB anway. I would be interested to know why the TQ144 package has a "-" for LVDCI_33 though? Regards Andrew John Adair wrote: > The TQ144 package is one of the worst packages for SSO. In the datasheet I > happened to check (v1.4) there is a figure for LVDCI_33 although the TQ144 > is not listed in the table heading. There are VRP and VRN connections there > on the TQ144 to support DCI so I can only think that it will work to some > extent. > > Generally mixing very high speed I/O and the TQ144 package is not good > practise. If your I/O operates at lower speeds then setting the current > drive on outputs to a lower value amy give nearly as good results as the > DCI. Also does not increase the power consumption, and heat, like the DCI > does. > > John Adair > Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development > Board. > http://www.enterpoint.co.uk > > > "Andrew FPGA" <andrew.newsgroup@gmail.com> wrote in message > news:1117432925.950059.58900@o13g2000cwo.googlegroups.com... > > Hi, > > I would like to use the Xilinx Spartan 3 DCI series source termination > > feature but the SSO guidelines from Pg25 of "DC and Switching > > Characterisics"(from the datasheet) leaves me thinking DCI is not > > supported for my IO standard and package. > > > > The IO standard is LVDCI_33. I.e. I want to use series termination for > > 3.3V LVCMOS signals. The part we are considering is XC3S50 TQ144. The > > table on pg25 shows a "-" for the number of SSO (simultaneously > > switching outputs) for LVDCI_33. Does this "-" mean 0 are supported, or > > it hasn't been characterised yet, or ?? > > > > Questions: > > 1) Is LVDCI_33 supported for the TQFP144 package? > > > > Also would be interested to know why it isn't supported.(extra pin > > inductance of the leaded packages??) > > > > Regards > > Andrew > >
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