Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
in its edk (embedded system development kit), xilinx provide a micro kernel for the microblaze/ppc405 core in some types of its fpgas. based on xilinx's doc, this micro kernel is like an rto, provide a services (such as preemptive scheduler, posix interface, etc) to the application. i am thinking about using this micro kernel to develope my application. i have a couple of general questions here: 1. anybody has experence with this micro kernel? how is it? 2. there are a doze of (very expensive) rtos developed for microblaze/ppc405, such as mv linux and vxworks, if xilinx micro kernel can do the same thing, why should i pay for these rtos? any inputs are highly appreciated. chongArticle: 85851
Thanks a lot to everybody for your help, now my task is much more evident GiovanniArticle: 85852
Xilinx is doing it again. http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=s3e_overview "Spartan-3E FPGA devices with 100K system gates are available for under US$2.00*" Later in the text we learn that the pricing is for 2H2006. The current price is higher. There are three correct formulations possible for these facts: - The devices will be be available for under US$2. - The devices are not available for under US$2. - The devices are available for <insert real price> The formulation chosen by Xilinx marketing definetly is illegal in Germany under UWG. (Last time these text were distributed in Germany by distributors). And it probably is illegal in the US. I do not understand why a big company with a good product again and againg ressorts to unfair and illegal marketing that is designed to confuse customers? This really is bad style. Kolja Sulimma (Otherwise a happy Xilinx user)Article: 85853
"Jon Harris" <jon_harrisTIGER@hotmail.com> writes: > Are you taking pictures of stationary things from a stationary camera? > That's what the astronomy case involves. But since you are concerned > with a moving camera, I assumed you were talking about pictures taken > with a hand-held camera. In that case, the reason the shake creates > blur is that the exposure is too long. And the reason for the long > exposure is lack of light (due to lens limitations, ambient light > conditions, or both). If you were to shorted the exposure, you would > end up with a picture that is too dark. So - comp.dspers - does anybody know what algorithms hand-held cameras and hand-held video recorders use to reduce camera shake? Surely some estimation of movement and compensation is possible in the same way as astronomy? But does your average digital camera have enough CPU? So what is used in practice - anything at all? TonyArticle: 85854
Hi John,
> the structure. It would be easier if the VHDL language standard was
> modified to support "return generic values" that are computed during
> component elaboration and returned as a compile time constant to the upper
> level code that instantiates the component.
Yup, that gets said about once a week in this office. :-)
> Since VHDL doesn't let you do this, the only other solution I can think of
> is to write functions in a package that perform the latency calculation at
> the top level, and then pass the latency as a parameter to the lower level
> components.
Well, the other possibility is to use flow control handshakes at each
pipeline
stage and put up with non-deterministic latency. That has its own problems,
of course - but I've found both approaches useful in certain contexts.
> It's a pain to have to write the functions that calculate exactly where to
> place the registers, since you have to take the latency as a given and
> put it where it will do the most good.
As another poster indicated, if you have a bunch of sites where a register
could be placed, then it's a piece of cake to have an array of booleans
as a generic parameter to control the register placement. The problem
of finding optimal register placement can usually be solved by brute force:
write a script to implement the component using every possible vector with
N bits set, for every value of N you're interested in. In fact, you don't
even
need to do every possible vector (which is a binomial-type thing) because
you can easily prove that certain vectors will always be worse than other
vectors. This narrows the search space quite a bit (which matters if you're
talking about a 10-deep pipeline, but not so much if it's 3 or 4!).
Of course, you have to do this every time your design changes significantly;
but if your project is headed for a library which will be used many times
by many people, it shouldn't change (and the effort should be justified).
> Having said all this, I'll close with the assertion that I can see the day
> coming when it won't be just the logic that needs pipelining... Someday
> we'll have to pipeline the routing too. Probably in the 45 nm node.
It's happening already. When you're designing for 300MHz plus, those
previously-innocuous net delays of 900ps are a massive chunk out of
your cycle budget. More than once I've ended up with a critical path
having no levels of logic...
Cheers,
-Ben-
> P.S. I'm a Xilinx FAE, but writing this in my "off hours".
P.S. I'm a Xilinx design engineer, and I don't get "off hours". :)
Article: 85855
HB wrote:
> Hi,
> I 'm trying to use UART with NIOS2 (Stratix).
> I would like to send a message to Hyperterminal.
> (not with JTAG_UART, and not with NIOS IDE console)
>
> Could you help me ?.
> (free example could be perfect !).
>
> Regards,
>
> BH.
>
>
Add a UART peripheral to the Nios2, connect the signals to fpga pins,
connect these fpga pins to an RS-232 driver chip, connect the driver
chip to a serial cable, connect the serial cable to the PC. In the
Nios2 software, use your new UART just like the JTAG_UART. On the PC,
run Tera Term Pro ("Hyperterminal" is a piece of XXXX, and can easily
cause more problems than it solves).
If you need more help, you'll have to come up with far more specific
questions, and give more information as to your setup.
mvh.,
David
Article: 85856I have a implemented a PCI 66Mhz master/target design on an Fpga, using an IP core from one of the well known suppliers. The core does not support PCI-X. The card works fine in 33Mhz and 66Mhz PCI slots. However, it sometimes fails to be seen by the PC when inserted in a PCI-X slot. I drive the PCIXCAP and M66EN pins on the card from the Fpga to signal that the card supports 66Mhz PCI but not PCI-X. Here's my question. On power-up, a PCI-X slot expects the card to wake up within 100ms, whereas a PCI slot allows 2^25 clock ticks which is about 500ms. By the time my Fpga wakes up (exits power-on reset and is configured) I'm thinking that I might have missed the 100ms reset window? If I miss that window, and the Fpga hasn't driven PCIXCAP to signal that the card doesn't support PCI-X, then the PC won't see the card. Is that correct? Now here's the complicated (to me) bit. If I power-cycle the PC, then "sometimes" the card will be recognised. What I'm thinking is that perhaps when the card wakes up after the 100ms window, the PC thinks a 66Mhz PCI card has been hot-plugged, and on power-down it stores that information such that when the PC is switched back on it expects that the PCI-X bus will have a conventional PCI card on it and therefore it uses a 2^25 clock reset window. Am I on the right track here at all? I'm going to tie-off PCIXCAP on the board, rather than driving it from the Fpga, and the same for M66EN. I'm just wondering why the card sometimes works and sometimes doesn't. All intelligent comments welcomed. AlanArticle: 85857
Kolja Sulimma wrote:
> Xilinx is doing it again.
>
> http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=s3e_overview
> "Spartan-3E FPGA devices with 100K system gates are available for under
> US$2.00*"
> Later in the text we learn that the pricing is for 2H2006. The current
> price is higher.
>
> There are three correct formulations possible for these facts:
> - The devices will be be available for under US$2.
> - The devices are not available for under US$2.
> - The devices are available for <insert real price>
>
> The formulation chosen by Xilinx marketing definetly is illegal in
> Germany under UWG. (Last time these text were distributed in Germany by
> distributors). And it probably is illegal in the US.
>
> I do not understand why a big company with a good product again and
> againg ressorts to unfair and illegal marketing that is designed to
> confuse customers?
> This really is bad style.
Yes, and it annoys their user base, but they are not the only ones
doing it. [tho that is no excuse!]
Looking at
http://www.altera.com/corporate/news_room/releases/products/nr-ultimate-products.html
The headline claims :
" Altera's HardCopy II Structured ASICs and MAX II CPLDs Named Ultimate
Products by eeProductCenter "
Hmmm, not my choice for Ultimate Products, but let's read on....
"Both Altera® products were ranked in the top five in the logic and
programmable logic category."
So "Ultimate" [1.Furthest or highest in degree or order; utmost or
extreme; 2.Being the last or concluding element of a series]
has suddenly spin-morphed to actually meaning - "Hey, we made the top FIVE!"
Now let's see, top five in the logic and programmable logic category ??
So that could be, as an example that fits that claim :
1. Atmel
2. Actel
3. Lattice
4. Xilinx
5. Altera
If it was any better, surely they would have said the top three, or top
two ?
And further on, we see
...described MAX II CPLDs as "as the industry's lowest-cost CPLD
available now," and "ideal for volume-driven, price-sensitive applications."
Reality check time - quick look at their own web site
http://www.buyaltera.com/scripts/partsearch.dll/showfilter?lookup=1,30,3074
shows the Cheapest MAX II is listed at $6.00 - lowest cost ? - hmm,
there are over 43 other CPLDs from Altera that clearly have
lower prices {and many over at Xilinx too... ) !?.
So what can "lowest cost CPLD" actually mean ?
-jg
Article: 85858Hey, is there any way to alter stuff *inside* a cell (like the LUT table or muxes) using Figaro/IDS? It's really cool that you can drag around the inter-cell routing resources, but I can't figure out how to edit the other stuff. Is there any other tool that lets you do this, sort of like Xilinx's FPGA Editor does?Article: 85859
Hi there, I'm trying to build a new core that will use a IPIF PLB interface to connect to the PLB. Most of my logic is ready to roll and tested independantly, but when I came to add the IPIF interface I fell over at the first hurdle :( I'm using ISE 7.1, and I started a new project, and had guessed that the IPIF logic block would be something I could generate with CoreGen, but apparently not. A search of xilinx.com with IPIF related terms didn't present me with a getting started guide. Any pointers on how I instantiate an IPIF block. My top level will be produced with VHDL (unless I really have to switch to verilog), and I want to use the IPIF on the PLB and use the DMA capabilities. Cheers, -- Michael, sure he's missing something obvious hereArticle: 85860
I see a lot of posts here that are specific to a single vendor's
devices or that device-vendor's tools. I think it would make things a
bit more organized if we had a few subgroups beneath comp.arch.fpga
for the specific vendors (just like comp.os), and kept comp.arch.fpga
itself for vendor-agnostic (or vendor-comparative) discussions.
Traffic has been pretty high lately (~50 posts/day).
If you support this (or if you don't), please post in this thread.
Also let me know what vendors you'd like to see listed. Off the top
of my head, alphabetically,
Actel
Altera
Atmel
Cypress
Lattice
Quicklogic
Xilinx
I think it would be wise to keep the list short by limiting it to
vendors currently producing and selling chips, and which are available
from distributors at the retail level (ie EOL'ed or a specialty
device).
If there is sufficient support, I will RFD the matter over on
news.announce.newgroups and reference this thread as justification.
The call for votes will be crossposted here.
Thanks,
- a
--
"I didn't see it then, but it turned out that getting fired was the
best thing that could have ever happened to me. The heaviness of
being successful was replaced by the lightness of being a beginner
again, less sure about everything. It freed me to enter one of the
most creative periods of my life."
-- Steve Jobs, commencement speech at Stanford, June 2005
Article: 85861On Thu, 16 Jun 2005 22:08:13 -0700, "Jon Harris" <jon_harrisTIGER@hotmail.com> wrote: >Are you taking pictures of stationary things from a stationary camera? That's >what the astronomy case involves. But since you are concerned with a moving >camera, I assumed you were talking about pictures taken with a hand-held camera. >In that case, the reason the shake creates blur is that the exposure is too >long. And the reason for the long exposure is lack of light (due to lens >limitations, ambient light conditions, or both). If you were to shorted the >exposure, you would end up with a picture that is too dark. > [Stuff snipped] I have read a bit about the astronomical image processing mention in one of the other posts. One thing that came up quite often, is that CCD sensors are linear. i.e. double the exposure time gives double the energy recieved. (They do not mention CMOS, but it is probably the same.) I agree that blurring occurs when taking a single photo when the camaera is moved and the exposure is to long. If one can say take in stead of 1x 2sec exposure, take 20x 0.1 sec exposures, and stack them into a single picture in software, one should end up close to the exposure level of the 2sec picture, but without the blur. In the astronomical case, the "short" exposure pictures are in minutes for a total exposure time of hours. Of course the subject must not move during the "short" exposure time. If one scaled this down so that the "short" exposure time is in milli-seconds or even micro-seconds depending on what the sensors can do, then one can do the same thing just at a much faster scale. What is the minimum exposure time for a current CMOS sensor before one just see the inherant sensor noise ? Regards Anton ErasmuArticle: 85862
On Thu, 16 Jun 2005 22:08:13 -0700, "Jon Harris" <jon_harrisTIGER@hotmail.com> wrote: >Are you taking pictures of stationary things from a stationary camera? That's >what the astronomy case involves. Have you ever wondered why stars twinkle or looked at the Moon with a large magnification (100x or more) ? While the target and the telescope are both stationary (or actually moving in a predictable way) the target appears to be bouncing around a lot due to the atmospheric turbulence. The effect would be similar as if the telescope was shaking. Thus, the tricks used in astronomy should be applicable also for photographic camera stabilisation. PaulArticle: 85863
Hi,
I 'm using Stratix(10) Altera Develop KIT with UART "console" DB9.
File ".pin" of the Quartus project is ok (only RXD and TXD signals, we don't
use CTS etc..).
In the Nios software, the test (in 'file.c' => printf "test uart") with
jtag_uart is OK, I receive this message in NIOS IDE console.
How could I obtain this result with "uart" and a terminal (now, I'm using
"tera term pro" as terminal) ?.
Can I use 'jtag_uart' and 'uart' in same project (Is it an irq problem ?.) ?
How can I do choices ('jtag_uart' and/or 'uart') to write this message ('IDE
console' and/or 'terminal') ?.
Thanks in adance.
BH.
"David Brown" <david@westcontrol.removethisbit.com> a écrit dans le message
news: d8tvq7$6jp$1@news.netpower.no...
> HB wrote:
> > Hi,
> > I 'm trying to use UART with NIOS2 (Stratix).
> > I would like to send a message to Hyperterminal.
> > (not with JTAG_UART, and not with NIOS IDE console)
> >
> > Could you help me ?.
> > (free example could be perfect !).
> >
> > Regards,
> >
> > BH.
> >
> >
>
> Add a UART peripheral to the Nios2, connect the signals to fpga pins,
> connect these fpga pins to an RS-232 driver chip, connect the driver
> chip to a serial cable, connect the serial cable to the PC. In the
> Nios2 software, use your new UART just like the JTAG_UART. On the PC,
> run Tera Term Pro ("Hyperterminal" is a piece of XXXX, and can easily
> cause more problems than it solves).
>
> If you need more help, you'll have to come up with far more specific
> questions, and give more information as to your setup.
>
> mvh.,
>
> David
Article: 85864We have a product coming to assist in this area. Based on Spartan-3 in FG456 it consists of a PGA style board with the Spartan-3 in the middle. This module is aimed at hobby or small run board builders that don't want the setup charges of BGA lines. Currently sitting about 5th in our planned product release schedule it can be brought forward it we get a lot of potential demand. So let us know if you might want this product. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "James Morrison" <spam1@stratforddigital.ca> wrote in message news:p5ise.10538$5u4.34021@nnrp1.uunet.ca... > (This was originally posted on sci.electronics.design and was intended > to be cross-posted to these groups but that got missed before sending. > So here it is posted to these groups but not sci.electronics.design--if > you like please cross-post your reply to that newsgroup. Sorry for the > inconvenience). > > ------------- > > Hello, > > Does anyone else find themselves in the position I often find myself in: > It is a royal pain to get prototype quantities populated with BGA > components. If an assembly house has BGA machinery they are typically > too big to care about the little guy like me who doesn't need all that > many boards assembled but is willing to pay for the service for a few > boards. > > For the first few boards I often like to populate in blocks and do tests > at each stage so if there is a problem it is much easier to isolate the > problem. If you populate the whole board and then find a problem (if > you can) fixing it often means removing components that you've already > populated. > > It would also be very expensive to populate a small run using an > SMT-line and then find out that the power supply is going to blow up > parts (especially a worry if you have a boost power supply). > > Does anyone know of anywhere that will take a few boards and populate a > few BGA's by hand? In Canada? In southern Onatrio? > > If there is nothing out there, is anyone interested in this type of > service. I need this service so I was considering purchasing a rework > station and then making the service available for a fee to pay for the > station and to provide a service to the design world. Would anyone use > this? > > Thanks for your input, > > James. > > >Article: 85865
On Fri, 17 Jun 2005 02:34:48 -0700, Adam Megacz <megacz@cs.berkeley.edu> wrote: > >I see a lot of posts here that are specific to a single vendor's >devices or that device-vendor's tools. I think it would make things a >bit more organized if we had a few subgroups beneath comp.arch.fpga >for the specific vendors (just like comp.os), and kept comp.arch.fpga >itself for vendor-agnostic (or vendor-comparative) discussions. >Traffic has been pretty high lately (~50 posts/day). > >If you support this (or if you don't), please post in this thread. >Also let me know what vendors you'd like to see listed. Off the top >of my head, alphabetically, > > Actel > Altera > Atmel > Cypress > Lattice > Quicklogic > Xilinx > >I think it would be wise to keep the list short by limiting it to >vendors currently producing and selling chips, and which are available >from distributors at the retail level (ie EOL'ed or a specialty >device). > >If there is sufficient support, I will RFD the matter over on >news.announce.newgroups and reference this thread as justification. >The call for votes will be crossposted here. > >Thanks, > > - a I don't see that there is enough traffic to justify it, and it will ineviably reduce the readership as many users will not bother looking in all the NGs, therefore reducing the usefulness. Most of us are busy, and the difference in time and effort between speed-reading a few dozen headers a day on one NG, and reading a handful of headers in several NGs will undoubtedly mean that fewer people will bother. The busiest people are quite likely to be those most valuable to the NG in terms of experience and expertise, and nothing should be done to discourage them from participating. Many questions asked by a user of a specific FPGA may actually be fairly generic, so they may miss useful answers from people who only look in one of the maker-specific NGs. It will also be the case that the useful 'experts' will only subscribe to the NG for the maker they are actively using, but they may well have useful knowledge of others. So in a word, NO!Article: 85866
Kris Neot wrote: > Correct, my idea is much liks multiple short time exposure then > combine them while taking into account of the displacement. If > similar techniques have been done in the telescopes, then it is > a baked bean. No need to explore it further. Amateur astromoners are now doing it routinely with modest hardware to get stunning results from "lucky" exposures. Do a search on "registax" and Toucam and something like QUAICG (I forget the spelling). http://members.dialstar.com/asrc/T_Davis6.htm Correlate, stack and add the highest contrast images and bin the dross works amazingly well if you have enough signal to noise. Regards, Martin Brown > "Paul Keinanen" <keinanen@sci.fi> wrote in message > news:sjh3b15dd6l1ppd9i4oilql87nlfis7mpo@4ax.com... > >>On Thu, 16 Jun 2005 08:58:16 -0500, Chuck Dillon <spam@nimblegen.com> >>wrote: >> >> >>>I believe he's talking about a single frame exposure not video. He's >>>talking about motion during the exposure and I assume a problem of >>>varying affects of the motion on the different sensors (e.g. R,G and B) >>>that combine to give the final image. >> >>If the end product is a single frame, what prevents from taking >>multiple exposures and combine the shifted exposures into a single >>frame ? >> >>In ground based optical astronomy, the telescope is stable, but the >>atmospheric turbulence deflect the light rays quite frequently to >>slightly different directions. Taking a long exposure would cause >>quite blurred pictures. Take multiple short exposures, shift each >>exposure according to the atmospheric deflection and combine the >>exposures. Look for "stacking" and "speckle-interferometer". >> >>To do the image stabilisation in a camera, the MPEG motion vectors >>could be used to determine the global movement between exposures, but >>unfortunately getting reliable motion vectors from low SNR exposures >>is quite challenging. Of course if 3 axis velocity sensors are >>available, these can be used to get rid of any ambiguous motion >>vectors and also simplify searching for motion vectors. >> >>With reliable motion vectors for these multiple low SNR exposures, the >>exposures can be shifted accordingly, before summing the exposures to >>a single high SNR frame. >> >>Paul You don't need to record the motion vectors. They can be derived after the event by cross correlating the images.Article: 85867
<amyler@eircom.net> schrieb im Newsbeitrag news:1118998997.082942.110340@g49g2000cwa.googlegroups.com... > I have a implemented a PCI 66Mhz master/target design on an Fpga, using > an IP core from one of the well known suppliers. The core does not > support PCI-X. > > The card works fine in 33Mhz and 66Mhz PCI slots. However, it sometimes > fails to be seen by the PC when inserted in a PCI-X slot. > > I drive the PCIXCAP and M66EN pins on the card from the Fpga to signal > that the card supports 66Mhz PCI but not PCI-X. > > Here's my question. > > On power-up, a PCI-X slot expects the card to wake up within 100ms, > whereas a PCI slot allows 2^25 clock ticks which is about 500ms. By the > time my Fpga wakes up (exits power-on reset and is configured) I'm > thinking that I might have missed the 100ms reset window? If I miss > that window, and the Fpga hasn't driven PCIXCAP to signal that the card > doesn't support PCI-X, then the PC won't see the card. Is that correct? > > Now here's the complicated (to me) bit. If I power-cycle the PC, then > "sometimes" the card will be recognised. What I'm thinking is that > perhaps when the card wakes up after the 100ms window, the PC thinks a > 66Mhz PCI card has been hot-plugged, and on power-down it stores that > information such that when the PC is switched back on it expects that > the PCI-X bus will have a conventional PCI card on it and therefore it > uses a 2^25 clock reset window. > > Am I on the right track here at all? > > I'm going to tie-off PCIXCAP on the board, rather than driving it from > the Fpga, and the same for M66EN. > > I'm just wondering why the card sometimes works and sometimes doesn't. > > All intelligent comments welcomed. > > Alan > well you answered yourself, 1 the M66EN and PCIXCAP should defenetly not be driven by FPGA but be hardwired 2 there is no information stored on power down when the PC doesnt see the card is it still visible as uninitialied card? PCI card is accessed several times during boot up process, if you miss the first accesses to it then the card will not be enumerated but it would still show up if just try PCIscope or PCItree to see if they see the card in those cases where the OS doesnt enumerate it BTW there can by multiply resets, like resetting in PCI mode then quering the PCIx capability list and resetting again. but multiply resets can also be seen when no PCIx card is inserted. also make sure that if any DCM are used then the logic clocked from DCM will not mixup the PCI logic I have a system with PCIx FPGA board and PCI FPGA board where I reconfigure both devices 'live' and reenable the bars after reconfiguration using special sw for it, it saves a lot of time when you dont need to reboot after FPGA reconfing I tried to use ChipScope but unfortunatly chipscope ILA cores makes the PCIx design to non working :( but you can try to insert some smaller chipscope ILA and trace the reboot process (I used 128 bit wide ILA maybe that was too much) anttiArticle: 85868
Have you got the time to rework your PCB? You could consider double footprinting to give bigger range of parts that can be used. FG256 and FG456 will sit within a PQ208 set of pads or put some pins in for an add-on module. Not an optimal solution for production but if you are in a must ship situation it might solve your delema. We have done this before for "critical" projects as a way out of a delivery issue. We can certainly help with an initial FG456 package of XC3S400 if that gets you out of the problem. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "xilinx_user" <barrinst@ix.netcom.com> wrote in message news:1118963267.294058.266260@g49g2000cwa.googlegroups.com... >I called NuHorizon today - at their 800 number -and was told that there > was an order placed June 9 with expected delivery August 30th. This was > using the added suffix suggested by Steve Knapp and Peter Alfe. > > My interpretation of this is that there are, in effect, virtually no > parts available for customers like me who only order 35-50 at a time. > > I will look forward to Peter Alfke working the system inside Xilinx. > Hopefully he will accomplish something and have better news to report. > > The net result of this is that my product is in jeopardy. I've used > Xilinx parts for nearly 15 years and would hate to move over to Altera, > but I am getting fearful I might have to consider that in order to > protect the investment my company has in its product development. > > I think Xilinx is a great company, so I am really hoping there is news > fairly soon to restore my confidence. > > > John_H wrote: >> "User" <tech3@cavelle.com> wrote in message >> news:1118958956.419423.83120@g14g2000cwa.googlegroups.com... >> > I heard back from the major distributor today, who said that there are >> > indeed no parts available for prototype / pre-production and certainly >> > not larger quantities. They thought there might be a possibility of >> > obtaining something in an industrial temperature grade, but otherwise >> > nothing, magic 300mm suffix or no magic suffix. Otherwise there >> > appears to be nothing anywhere. >> >> <snip> >> >> Could you mention for those in-the-know (since it's not in this thread): >> 1) what part, package, and speed grade >> 2) which distributor is giving you the info (city may help) >> >> I love to see things get solved but I don't like to see people get upset >> without providing the information needed to help them through the "side >> channels" here on the newsgroup. If there's bad info getting around, >> that >> info should be squashed. >Article: 85869
ROTFL
ROTFL
this time really
TOP 5 listed !!
"Jim Granville" <no.spam@designtools.co.nz> schrieb im Newsbeitrag
news:42b292ea$1@clear.net.nz...
> Kolja Sulimma wrote:
> > Xilinx is doing it again.
> >
> > http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=s3e_overview
> > "Spartan-3E FPGA devices with 100K system gates are available for under
> > US$2.00*"
> > Later in the text we learn that the pricing is for 2H2006. The current
> > price is higher.
> >
> > There are three correct formulations possible for these facts:
> > - The devices will be be available for under US$2.
> > - The devices are not available for under US$2.
> > - The devices are available for <insert real price>
> >
> > The formulation chosen by Xilinx marketing definetly is illegal in
> > Germany under UWG. (Last time these text were distributed in Germany by
> > distributors). And it probably is illegal in the US.
> >
possible yes, US has some laws too.
> > I do not understand why a big company with a good product again and
> > againg ressorts to unfair and illegal marketing that is designed to
> > confuse customers?
> > This really is bad style.
>
> Yes, and it annoys their user base, but they are not the only ones
> doing it. [tho that is no excuse!]
>
> Looking at
>
http://www.altera.com/corporate/news_room/releases/products/nr-ultimate-products.html
>
> The headline claims :
> " Altera's HardCopy II Structured ASICs and MAX II CPLDs Named Ultimate
> Products by eeProductCenter "
>
> Hmmm, not my choice for Ultimate Products, but let's read on....
>
> "Both Altera® products were ranked in the top five in the logic and
> programmable logic category."
>
> So "Ultimate" [1.Furthest or highest in degree or order; utmost or
> extreme; 2.Being the last or concluding element of a series]
> has suddenly spin-morphed to actually meaning - "Hey, we made the top
FIVE!"
>
> Now let's see, top five in the logic and programmable logic category ??
>
> So that could be, as an example that fits that claim :
> 1. Atmel
> 2. Actel
> 3. Lattice
> 4. Xilinx
> 5. Altera
BIG ROTFL !!!
> If it was any better, surely they would have said the top three, or top
> two ?
>
> And further on, we see
> ...described MAX II CPLDs as "as the industry's lowest-cost CPLD
> available now," and "ideal for volume-driven, price-sensitive
applications."
>
> Reality check time - quick look at their own web site
>
http://www.buyaltera.com/scripts/partsearch.dll/showfilter?lookup=1,30,3074
>
> shows the Cheapest MAX II is listed at $6.00 - lowest cost ? - hmm,
> there are over 43 other CPLDs from Altera that clearly have
> lower prices {and many over at Xilinx too... ) !?.
>
> So what can "lowest cost CPLD" actually mean ?
>
> -jg
>
all marketing BS
MAX2 is nice non volatile version of Xilinx XC2K
nothing in common what is considered CPLD (as Complex PLD)
its really nice, but it doesnt at all compete in the low range PLD market
the low range is 1USD and sub 1USD devices available from many vendors
Antti
Article: 85870Hi due to the fact that Xilinx EDK 7.1 Debugger does not support Xilinx platform USB cable and Virtex 4 I was forced to overcome the lack of Printer port on my development PC, and the solution was done, completed this morning in time frame 0400-0700AM - its just a .POF file for Altera MAX2 Starterkit that emulates standard PCI - LPT port and Xilinx DLC5 Cable. works like magic - no special driver required the PCI LPT card is silently accepted as normal LPT by windows XP and all Xilinx tools. the .POF file and description is available for anyone interested please just email me, I will send the files ASAP I may later make it all available from web download as well, at the moment its only available on request it really is what the subject says, if you have MAX2 Starterkit then you also can 'change it' to be Xilinx DLC5 compatible JTAG card, or to some other LPT based cable/dongle - more to be released whenever I have time or there is extra interest Antti PS during all the development on Quartus I did not have any tool related issues at all, everything just worked. PPS for those who manufacture and sell PCI based FPGA boards (no matter what vendor) branded versions of this IP core and others can be made, please inquiry - I would like to see some applications for Xilinx based PCI boards as well, but I dont have any suitable for that purpose.Article: 85871
comp.arch.fpga.cpu might be a good idea. Somewhere for all the NIOS & MicroBlaze queries. Cheers, JonArticle: 85872
"Jon Beniston" <jon@beniston.com> wrote in message news:1119008115.592497.325850@g14g2000cwa.googlegroups.com... > comp.arch.fpga.cpu might be a good idea. Somewhere for all the NIOS & > MicroBlaze queries. > > Cheers, > Jon > Which newsgroup would I post my question relating to my implementation of a 6805 core in an fpga? The .cpu group or the parent group or both. At an average of 10 topics per day, I'd prefer to keep it in one place, like Mike. Cheers, AlfArticle: 85873
Hi All, EDK6.2 sp2 generated VxWorks comes up with following warning when the cache is enabled.OPB_Ethernet is used. emac: device requires cache coherent memory for BD's Please help. Regards, IvanArticle: 85874
Kris Neot wrote: > Found a flaw in my idea after a little test. > > My deer is a perfectly exposed picture and my trick is applied to it, > I ended up with a very dull pic, thus, I believe, with a picture that > has motion blur, the outcome will be even more worse after application > of my idea. To improve my idea, I need the image sensor to run at > 1000fps, which is impossible. Well, if you are just filming a swinging ball, have a look at this: http://www.2d3.com/jsp/products/product-examples.jsp?product=11 download the dolphin movie. Not sure is any help, but the result (improvement) is spectacular.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z