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On Jan 26, 8:45=A0am, Emanuele83 <emanuele83katam...@googlemail.com> wrote: > On Jan 26, 6:44=A0am, rickman <gnu...@gmail.com> wrote: > > > > > > > > > > > On Jan 25, 9:48=A0am, n...@puntnl.niks (Nico Coesel) wrote: > > > > Emanuele83 <emanuele83katam...@googlemail.com> wrote: > > > >Good day to everybody, > > > > >Chipscope core to debug my modifications, the design was no more abl= e > > > >to perform correct operations nor to communicate with some external > > > >chips creating corrupted data. Even if ALL the constraints at 40MHz > > > > IMHO this is a problem with unconstrained paths. Did you constrain > > > input to ff and ff to output paths? Did you constrain paths between > > > unrelated clock domains? > > > > >Some info: > > > >1_I have no possibility to check if the FPGA HW is broken or not. X- > > > >ray or what else. I just wait for a new board which should be backed > > > >carefully > > > >2_I have no chances to perform post route simulations for the whole > > > >project (I am in a hurry) and with my old design I did not do it > > > >(SPARTAN 2) and everything was perfectly working (also without setti= ng > > > >any constraint over PERIOD or OFFSET) > > > >3_I have 3 boards, when I program them with the same bitstream they > > > >behave sometimes differently. > > > > This may be due to FPGA variations. I'd get the constraints sorted ou= t > > > first. Perhaps you could buy a development board and verify your > > > design on that so you have a proper reference. > > > That is one of the things I have always felt was lacking, a way to > > verify timing constraints. =A0I've talked to FPGA vendors and their > > attitude is just that an engineer should be able to write the > > constraints correctly, period. =A0No need to verify! =A0Boy, that goes > > against everything I've ever learned about engineering. =A0You can have > > problems with ANY part of a design. =A0Being able to verify all aspects > > of your design is much better than "testing". =A0Testing can prove the > > existence of faults, but it can't prove the absence... at least not > > without a LOT of effort and analysis. =A0In fact, testing is a lot like > > constraints, you have to do it "right" and how do you prove that you > > have done the testing "right"? > > > Rick > > Holy words, fellow, holy words! :) We use more time to writing the > correct test (that must be done carefully) than to design the logic... > > I am going to test the power supply section, but I've already tested > yesterday that compiling the same code, setting the drive strength of > I/Os to a safer value (from 6 to 2) the behaviour of the system is no > more consistent. I left all the timing constraints unchanged, always > met, @40Mhz speed, but it does not work.... 1_ I checked the power supply of the board. I fixed some minor stuff, and I checked the layout. My colleague has forgot to split the power plan for VCCAUX and VCC_0 so I thought that maybe the noise introduced by switching I/Os on the VCCAUX could create problems with the DCMs that I was using. take a look to the clock architecture: http://forums.xilinx.com/xlnx/attachments/xlnx/Spartan/8738/1/dcm_arch.jpg this was the one at the very beginning (at 80MHz) and now I changed using the same DCM structure but with 40MHz (output of first DCM is not clk_2x anymore) and everything now works with 40Mhz. The second DCM has the only purpose to deskew the RAM chips (which work at 40MHz now) Thinking that the problem was on DCM's noisy power supply I just removed the DCM and bypassed the 40 MHz clock input directly to the ram output, the external feedback is no more used and the logic is clocked directly with the external clock. it seems better, but if I change the compiling settings (optimizing for area and not for speed for example) the system does not work... The design seems less affected from the settings modifications but it is not yet stable, and the goal of 80Mhz is still far away :( 2_ I find sometimes this WARNING in the map log: Pack:266 - The function generator inst_arbiter_core/hist_box_ch_0/ state_m_1_FSM_Out21 failed to merge with F5 multiplexer inst_arbiter_core/hist_box_ch_0/i_FSM_FFd2-In21_f5. There is a conflict for the FXMUX. The design will exhibit suboptimal timing. I am not able to link it to the abnormal behaviour yet, but i found no explanation in the Xilinx website. Does somebody know something about it? I usually use some VARIABLES in my processes, also in the state machine which gives the PACK:266 error. they are not SHARED VARIABLES and are modified only synchronously, but sometimes i use them as a trick to save some clock cycles of latency (implementing real instantaneous assignments). Is a practice that should be avoided in a good VHDL code? Thanks, EmanueleArticle: 150551
Hey all. I'm trying to interface a Spartan 3 with a 5 volt avr. In some of Xilinx's documentation, (www.xilinx.com/support/answers/19146.htm) it is suggested that to make the S3s IO 5v tolerant, a 300 ohm resistor be used to protect the port from reverse current damage. However, instill might face logic high problems as read from the avr. What would you suggest for a (small footprint if possible) logic level converter? Thanks in advance.Article: 150552
<snip> >2_ I find sometimes this WARNING in the map log: >Pack:266 - The function generator inst_arbiter_core/hist_box_ch_0/ >state_m_1_FSM_Out21 failed to merge with F5 multiplexer >inst_arbiter_core/hist_box_ch_0/i_FSM_FFd2-In21_f5. There is a >conflict for the FXMUX. The design will exhibit suboptimal timing. >I am not able to link it to the abnormal behaviour yet, but i found no >explanation in the Xilinx website. Does somebody know something about >it? >I usually use some VARIABLES in my processes, also in the state >machine which gives the PACK:266 error. they are not SHARED VARIABLES >and are modified only synchronously, but sometimes i use them as a >trick to save some clock cycles of latency (implementing real >instantaneous assignments). Is a practice that should be avoided in a >good VHDL code? > Post that code! --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150553
Seems to be a problem of MUX extraction but only with AREA optimization set in synthesis options the code is long as hell... more than 1400 codelines But here you are an example of what i do with a variable in a state of the state machine STATE_M_1 read_meas is a state, synchronous with clock, i and j are variable declared in the process. i is always 1 when the machine comes in the read_meas state when read_meas => -- STOP condition already managed in each step before j := 0; -- important for latency wr_en_0 <= '0'; -- disable writing in fifo if i = 1 then -- i is 1 only at the first read of measurement meas.coar_t <= indata_meas_in(24 downto 17); meas.fine_t <= indata_meas_in(16 downto 0); rd_en_meas <= '0'; -- don't read anymore i := 2; state_m_1 <= fill; else -- if i is not 1 (should be 2) the machine save data meas.coar_t <= indata_meas_in(24 downto 17); meas.fine_t <= indata_meas_in(16 downto 0); rd_en_meas <= '0'; -- don't read anymore state_m_1 <= check; -- data are ready to be checked in oputput end if; -------------Article: 150554
>Seems to be a problem of MUX extraction but only with AREA optimization set in synthesis options > > >the code is long as hell... more than 1400 codelines But here you are an example of what i do with a variable in a state of the state machine STATE_M_1 >read_meas is a state, synchronous with clock, i and j are variable declared in the process. i is always 1 when the machine comes in the read_meas state > >when read_meas => -- STOP condition already managed in each step before > j := 0; -- important for latency > wr_en_0 <= '0'; -- disable writing in fifo > if i = 1 then -- i is 1 only at the first read of measurement > meas.coar_t <= indata_meas_in(24 downto 17); > meas.fine_t <= indata_meas_in(16 downto 0); > rd_en_meas <= '0'; -- don't read anymore > i := 2; > state_m_1 <= fill; > else -- if i is not 1 (should be 2) the machine save data > meas.coar_t <= indata_meas_in(24 downto 17); > meas.fine_t <= indata_meas_in(16 downto 0); > rd_en_meas <= '0'; -- don't read anymore > state_m_1 <= check; -- data are ready to be checked in oputput > end if; >------------- > Is that the process that cause the Packing error? Post the whole of that process, with the signal definitions that are relevant, and the package use declarations. As a rule of thumb, if your processes are > 100 lines long, they are too big for maintainability. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150555
Yes it cause the packing error, but not always... WHAT??? 100 lines? What do you mean with maintainability? My process has more than 900 lines... Sorry, but how can I separate a process in so small packages and do not go crazy with latency, synchronization and so on? I wold implement the whole design in schematics, it will be much easier...Article: 150556
On Jan 26, 9:32=A0am, Jay <jpt03...@engr.uconn.edu> wrote: > Hey all. > > I'm trying to interface a Spartan 3 with a 5 volt avr. In some of Xilinx'= s > documentation, (www.xilinx.com/support/answers/19146.htm) it is suggested > that to make the S3s IO 5v tolerant, a 300 ohm resistor be used to protec= t > the port from reverse current damage. However, instill might face logic > high problems as read from the avr. What would you suggest for a (small > footprint if possible) logic level converter? > > Thanks in advance. There are so many chips for level shifting that the best fit will really depend on your particular design. How many signals do you connect between the FPGA and the 5V micro? How many are inputs to the FPGA, how many outputs from the FPGA and how many are bidirectional? Going from 3V to 5V, you probably want to look at 74ACT series or something similar that can work with a 5V supply but has "TTL" compatible Vih and Vil specs. Going from 5V to 3V you could use the resistor (unidirectional). For bidirectional signals there are some parts with dual power supply that can provide active drive to both sides. If the signals are relatively slow, then you can use "Quickswitch" style FET switches and pullup resistors to do level shifting bidirectionally without any added control signals. Regards, GaborArticle: 150557
On Jan 26, 11:07=A0am, Gabor <ga...@alacron.com> wrote: > On Jan 26, 9:32=A0am, Jay <jpt03...@engr.uconn.edu> wrote: > > > Hey all. > > > I'm trying to interface a Spartan 3 with a 5 volt avr. In some of Xilin= x's > > documentation, (www.xilinx.com/support/answers/19146.htm) it is suggest= ed > > that to make the S3s IO 5v tolerant, a 300 ohm resistor be used to prot= ect > > the port from reverse current damage. However, instill might face logic > > high problems as read from the avr. What would you suggest for a (small > > footprint if possible) logic level converter? > > > Thanks in advance. > > There are so many chips for level shifting that the best fit > will really depend on your particular design. =A0How many > signals do you connect between the FPGA and the 5V > micro? =A0How many are inputs to the FPGA, how many > outputs from the FPGA and how many are bidirectional? > Going from 3V to 5V, you probably want to look at 74ACT > series or something similar that can work with a 5V supply > but has "TTL" compatible Vih and Vil specs. =A0Going from > 5V to 3V you could use the resistor (unidirectional). =A0For > bidirectional signals there are some parts with dual power > supply that can provide active drive to both sides. =A0If the > signals are relatively slow, then you can use "Quickswitch" > style FET switches and pullup resistors to do level shifting > bidirectionally without any added control signals. > > Regards, > Gabor One more point I forgot to add. The resistor trick doesn't work with the newer Spartan 3A and 3AN series parts. Those FPGA's don't have clamp diodes to Vcco. -- GaborArticle: 150558
>Yes it cause the packing error, but not always... > >WHAT??? 100 lines? What do you mean with maintainability? http://www.google.co.uk/search?q=what+is+maintainability > >My process has more than 900 lines... Sorry, but how can I separate a process in so small packages and do not go crazy with latency, synchronization and so on? >I wold implement the whole design in schematics, it will be much easier... > I spent many months trying to verify another engineer's PCI Bridge. His 'style' included all-in-one processes several hundred lines long. Most of the time when he corrected a bug that I found he stuck a different one in! And that was in RTL simulation, not post-P&R, or on the hardware! Perhaps you need to envisage the hardware implementation that you are trying to achieve a little more deeply. Split it into counters, muxes, adders, pipelining stages, and so on. But it's up to you, it's your job on the line. Do whatever you need to get your design working at the required speed... --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150559
Gabor <gabor@alacron.com> wrote: > On Jan 26, 11:07 am, Gabor <ga...@alacron.com> wrote: >> On Jan 26, 9:32 am, Jay <jpt03...@engr.uconn.edu> wrote: >> >>> Hey all. >> >>> I'm trying to interface a Spartan 3 with a 5 volt avr. In some of Xilinx's >>> documentation, (www.xilinx.com/support/answers/19146.htm) it is suggested >>> that to make the S3s IO 5v tolerant, a 300 ohm resistor be used to protect >>> the port from reverse current damage. However, instill might face logic >>> high problems as read from the avr. What would you suggest for a (small >>> footprint if possible) logic level converter? >> >>> Thanks in advance. >> >> There are so many chips for level shifting that the best fit >> will really depend on your particular design. How many >> signals do you connect between the FPGA and the 5V >> micro? How many are inputs to the FPGA, how many >> outputs from the FPGA and how many are bidirectional? >> Going from 3V to 5V, you probably want to look at 74ACT >> series or something similar that can work with a 5V supply >> but has "TTL" compatible Vih and Vil specs. Going from >> 5V to 3V you could use the resistor (unidirectional). For >> bidirectional signals there are some parts with dual power >> supply that can provide active drive to both sides. If the >> signals are relatively slow, then you can use "Quickswitch" >> style FET switches and pullup resistors to do level shifting >> bidirectionally without any added control signals. >> >> Regards, >> Gabor > > One more point I forgot to add. The resistor trick doesn't > work with the newer Spartan 3A and 3AN series parts. > Those FPGA's don't have clamp diodes to Vcco. > > -- Gabor Yeah in saw that. I'm not using the 3a, but i do need bi directional IO. There will be a total of 13 pins to the uC that need this treatment. Thanks for your help.Article: 150560
On Jan 25, 12:50=A0pm, ghelbig <ghel...@lycos.com> wrote: > On Jan 25, 6:13=A0am, Gabor <ga...@alacron.com> wrote: > > > > > > > On Jan 24, 5:21=A0pm, ghelbig <ghel...@lycos.com> wrote: > > > > On Jan 24, 12:23=A0pm, Gabor <ga...@alacron.com> wrote: > > > > > On Jan 24, 1:50=A0pm, ghelbig <ghel...@lycos.com> wrote: > > > > > > I think that iMpact is messing with me. > > > > > > Here's what I do: > > > > > > 1) Create a bit file with ISE 11.5 > > > > > 2) Downloading the bit file to my Virtex-5 via JTAG. =A0(I'm usin= g a > > > > > DLC9G and WinXP) > > > > > 3) Run a regression test on the system. > > > > > > If the regression test passes I do the following: > > > > > > 4) Create a MCS file with iMpact. > > > > > 5) Load the MCS into the attached SPI chip (again, with the DLC9G= ) > > > > > 6) Power cycle the board. > > > > > 7) Re-run the regression test. > > > > > > Here's my issue: > > > > > > I have two bit files for this project. =A0One was created last mo= nth, > > > > > one was created last week. =A0The steps above are repeated EXACTL= Y for > > > > > the two bit files. =A0There are no warnings or errors generated w= ith > > > > > steps 2 through 6. > > > > > > Step 7 fails for one bit file, and passes for the other. =A0With = one bit > > > > > file, and chip never leaves the DONE state. =A0Keep in mind that = both > > > > > bit files load and run "just fine" when I load them through the J= TAG > > > > > port. > > > > > > Has anyone seen this before? =A0I haven't gotten any help from th= e > > > > > factory yet. > > > > > > Regards, > > > > > G. > > > > > The first thing I look for is whether the .mcs file was really crea= ted > > > > correctly. > > > > I have been burned by the ISE GUI grabbing an existing impact proje= ct > > > > that > > > > built a new .mcs file from an old .bit file. > > > > > If you look in the directory where the .mcs file was built, there > > > > should also > > > > be a .prm file with the same base file name. =A0In this file you ca= n see > > > > the > > > > name and modification date of the .bit file(s) that were used in > > > > creating > > > > the .mcs file. > > > > > Also I have had some issues with indirect SPI programming using > > > > impact. =A0However usually these show up as an error when you go to > > > > verify the .mcs file in SPI flash. =A0When you say "never leaves th= e > > > > DONE state" do you mean that DONE never goes high? =A0Or does > > > > DONE go high, but the chip never comes out of reset. =A0The latter > > > > condition can be bitstream-dependent although I've never seen > > > > this behavior when using Master-SPI config mode. =A0Just be sure > > > > that you use the default startup clock (CCLK) when you run > > > > BitGen. > > > > > -- Gabor > > > > It is the "DONE goes high, but the chip never comes out of reset" > > > case. =A0It seems to be bit-stream dependent, I can make good MCS fil= es > > > from old BIT files. > > > > I'm stumped. =A0The only thing I can see different in the two cases > > > (works, does not work) from start to finish is the Verilog code. > > > > G. > > > Is there anything in the Verilog code that changes that might affect > > the reset? =A0Does your reset depend on PLL or DCM lock? =A0That > > can often be affected by seemingly unrelated changes especially > > if there is a noisy clock input or insufficient power supply bypass. > > > -- Gabor- Hide quoted text - > > > - Show quoted text - > > I changed the ISERDES from asynch to synch reset. =A0I added and removed > ILA's. =A0Everything else was just bug fixes. > > The bit-file works if JTAG-ed into the FPGA. =A0I can Write/Verify/Read > the SPI flash all day long. =A0The bit-file does not work when loading > from SPI. > > Thanks for helping! =A0Seriously, there are not bad ideas right now. > > G. Follow up: I get an '_impact4' error message when loading the bit file with iMPACT version 11.5 Searching the web, the only work-around I have found is: "This issue is scheduled to be resolved in iMPACT 11.4." And there is an implication that this only happens with Virtex-6 and Spartan-6. I'm using a Virtex-5. Does anyone have a suggestion? My hereditary alopecia is getting some serious competition. g.Article: 150561
On Jan 26, 4:56=A0am, Michael <michael_laaja...@yahoo.com> wrote:
> Hi,
>
> I am trying a design that is from ISE 9.2 on the latest 12.4 using
> CentOS 64 bit and receive the following error, I can't find anything
> on Xilinx that refers to it.
>
> Anyone seen the same and know a solution?
>
> INTERNAL_ERROR:Portability:basutencodeimp.c:229:1.24 - Number of bytes
> peeked
> =A0 =A0 does not match number of bytes requested. =A0Corrupted file?
> INTERNAL_ERROR:Portability:basutencodeimp.c:229:1.24 - Number of bytes
> peeked
> =A0 =A0 does not match number of bytes requested. =A0Corrupted file?
> FATAL_ERROR:NgdBuild:basnbbuspin.c:87:1.20 - Empty or missing BUS_SYNTAX
> for PM
> =A0 =A0 base =A0 Process will terminate. For technical support on this is=
sue,
> please
> =A0 =A0 open a WebCase with this project attached athttp://www.xilinx.com=
/support.
> Release 12.4 - Map M.81d (lin64)
>
> /michael
Did you translate the project or start a new one fresh? I have seen
poor results translating ("upgrading") projects.
The error sounds like a "unix EOL vs/ DOS EOL" type of problem. Was
the 9.2 project created in Windows?
CentOS is so similar to Fedora that I would not be looking at OS
issues; odds are it is an ISE issue.
Do you have access to 9.2 on Linux? That might be an interesting
test. (Or 12.4 on Windows...)
Another question is "Why are you changing ISE versions?" I am seeing
less than stellar results with version 12 (or version 11 for that
matter).
$.02,
G.
Article: 150562On Jan 26, 1:20=A0pm, ghelbig <ghel...@lycos.com> wrote: > On Jan 25, 12:50=A0pm, ghelbig <ghel...@lycos.com> wrote: > > > > > On Jan 25, 6:13=A0am, Gabor <ga...@alacron.com> wrote: > > > > On Jan 24, 5:21=A0pm, ghelbig <ghel...@lycos.com> wrote: > > > > > On Jan 24, 12:23=A0pm, Gabor <ga...@alacron.com> wrote: > > > > > > On Jan 24, 1:50=A0pm, ghelbig <ghel...@lycos.com> wrote: > > > > > > > I think that iMpact is messing with me. > > > > > > > Here's what I do: > > > > > > > 1) Create a bit file with ISE 11.5 > > > > > > 2) Downloading the bit file to my Virtex-5 via JTAG. =A0(I'm us= ing a > > > > > > DLC9G and WinXP) > > > > > > 3) Run a regression test on the system. > > > > > > > If the regression test passes I do the following: > > > > > > > 4) Create a MCS file with iMpact. > > > > > > 5) Load the MCS into the attached SPI chip (again, with the DLC= 9G) > > > > > > 6) Power cycle the board. > > > > > > 7) Re-run the regression test. > > > > > > > Here's my issue: > > > > > > > I have two bit files for this project. =A0One was created last = month, > > > > > > one was created last week. =A0The steps above are repeated EXAC= TLY for > > > > > > the two bit files. =A0There are no warnings or errors generated= with > > > > > > steps 2 through 6. > > > > > > > Step 7 fails for one bit file, and passes for the other. =A0Wit= h one bit > > > > > > file, and chip never leaves the DONE state. =A0Keep in mind tha= t both > > > > > > bit files load and run "just fine" when I load them through the= JTAG > > > > > > port. > > > > > > > Has anyone seen this before? =A0I haven't gotten any help from = the > > > > > > factory yet. > > > > > > > Regards, > > > > > > G. > > > > > > The first thing I look for is whether the .mcs file was really cr= eated > > > > > correctly. > > > > > I have been burned by the ISE GUI grabbing an existing impact pro= ject > > > > > that > > > > > built a new .mcs file from an old .bit file. > > > > > > If you look in the directory where the .mcs file was built, there > > > > > should also > > > > > be a .prm file with the same base file name. =A0In this file you = can see > > > > > the > > > > > name and modification date of the .bit file(s) that were used in > > > > > creating > > > > > the .mcs file. > > > > > > Also I have had some issues with indirect SPI programming using > > > > > impact. =A0However usually these show up as an error when you go = to > > > > > verify the .mcs file in SPI flash. =A0When you say "never leaves = the > > > > > DONE state" do you mean that DONE never goes high? =A0Or does > > > > > DONE go high, but the chip never comes out of reset. =A0The latte= r > > > > > condition can be bitstream-dependent although I've never seen > > > > > this behavior when using Master-SPI config mode. =A0Just be sure > > > > > that you use the default startup clock (CCLK) when you run > > > > > BitGen. > > > > > > -- Gabor > > > > > It is the "DONE goes high, but the chip never comes out of reset" > > > > case. =A0It seems to be bit-stream dependent, I can make good MCS f= iles > > > > from old BIT files. > > > > > I'm stumped. =A0The only thing I can see different in the two cases > > > > (works, does not work) from start to finish is the Verilog code. > > > > > G. > > > > Is there anything in the Verilog code that changes that might affect > > > the reset? =A0Does your reset depend on PLL or DCM lock? =A0That > > > can often be affected by seemingly unrelated changes especially > > > if there is a noisy clock input or insufficient power supply bypass. > > > > -- Gabor- Hide quoted text - > > > > - Show quoted text - > > > I changed the ISERDES from asynch to synch reset. =A0I added and remove= d > > ILA's. =A0Everything else was just bug fixes. > > > The bit-file works if JTAG-ed into the FPGA. =A0I can Write/Verify/Read > > the SPI flash all day long. =A0The bit-file does not work when loading > > from SPI. > > > Thanks for helping! =A0Seriously, there are not bad ideas right now. > > > G. > > Follow up: > > I get an '_impact4' error message when loading the bit file with > iMPACT version 11.5 > > Searching the web, the only work-around I have found is: "This issue > is scheduled to be resolved in iMPACT 11.4." > > And there is an implication that this only happens with Virtex-6 and > Spartan-6. =A0I'm using a Virtex-5. > > Does anyone have a suggestion? =A0My hereditary alopecia is getting some > serious competition. > > g. You could always update to the latest Impact. We're mostly using Impact 21.1 here, and found that it has some better features, at least for SPI indirect mode programming. Still not bug free, though. Still I would suggest going through your bitgen options one more time. Check in particular the startup settings for the correct clock and also see if release of "global WE" is possibly set very late or depends on DCM lock. If you don't have more than one device in the chain, there is no reason you can't have DONE go high after the other startup events. Then if DONE goes high but the chip isn't running, there are non-configuration start-up issues. -- GaborArticle: 150563
On Tue, 25 Jan 2011 11:26:06 +0100, David Brown <david@westcontrol.removethisbit.com> wrote: >On 24/01/2011 23:17, John Larkin wrote: >> On Mon, 24 Jan 2011 11:51:12 -0800 (PST), rickman<gnuarm@gmail.com> >> wrote: ><snip> >>> But none of this has to do with nationality. >>> >>> Rick >> >> > >It is important to distinguish between nationality and a country's laws >and bureaucracy - the regulations in John's quotation are about a >country's regulations, not an issue with the people. > >> http://www.eetimes.com/electronics-news/4212317/Xilinx--sales-fall-short-of-estimates >> >> "Xilinx recorded $4.3 million worth of restructuring charges during >> the recently concluded quarter. Olson said the charges were greater >> than expected because the company is closing its software development >> operation in France, where regulations make eliminating jobs >> difficult." >> >> John >> > >Clearly we don't know /what/ regulations are at issue here, as there >could be many. > >In general, you have to have good reason for firing people in Europe, >and normally you have to give significant notice (I don't know the >details for France, but 3 months is standard here in Norway. Of course, >this also means you can't quit your job without giving 3 months notice - >it works both ways). Does the law require that you remain productive during those three months? But cutting staff because you are downsizing /is/ >a good reason, though you might have to pay some sort of severance pay >or other compensation. You can't just tell employees to clear their >desks on the day, but you certainly can eliminate jobs. Here in California, an employer can ask an employee to take their stuff and leave, this very day or this very instant. I did that last week. And an employee can quit without notice. I've had people walk into my office, say "I quit", and walk out. JohnArticle: 150564
rickman <gnuarm@gmail.com> wrote: >On Jan 25, 9:48=A0am, n...@puntnl.niks (Nico Coesel) wrote: >> Emanuele83 <emanuele83katam...@googlemail.com> wrote: >> >Good day to everybody, >> >> >Chipscope core to debug my modifications, the design was no more able >> >to perform correct operations nor to communicate with some external >> >chips creating corrupted data. Even if ALL the constraints at 40MHz >> >> IMHO this is a problem with unconstrained paths. Did you constrain >> input to ff and ff to output paths? Did you constrain paths between >> unrelated clock domains? >> >> >Some info: >> >1_I have no possibility to check if the FPGA HW is broken or not. X- >> >ray or what else. I just wait for a new board which should be backed >> >carefully >> >2_I have no chances to perform post route simulations for the whole >> >project (I am in a hurry) and with my old design I did not do it >> >(SPARTAN 2) and everything was perfectly working (also without setting >> >any constraint over PERIOD or OFFSET) >> >3_I have 3 boards, when I program them with the same bitstream they >> >behave sometimes differently. >> >> This may be due to FPGA variations. I'd get the constraints sorted out >> first. Perhaps you could buy a development board and verify your >> design on that so you have a proper reference. > >That is one of the things I have always felt was lacking, a way to >verify timing constraints. I've talked to FPGA vendors and their Sorry but the timing report and the timing analyzer provide that information. -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------Article: 150565
On 26/01/2011 20:05, John Larkin wrote: > On Tue, 25 Jan 2011 11:26:06 +0100, David Brown > <david@westcontrol.removethisbit.com> wrote: > >> On 24/01/2011 23:17, John Larkin wrote: > >> In general, you have to have good reason for firing people in Europe, >> and normally you have to give significant notice (I don't know the >> details for France, but 3 months is standard here in Norway. Of course, >> this also means you can't quit your job without giving 3 months notice - >> it works both ways). > > Does the law require that you remain productive during those three > months? It can't and that is part of the problem. Some good guys do and others lounge around - there obviously isn't much you can do about it. My boss didn't work anything like as hard after he handed in his notice but he still did a decent job. Sometimes it is easier and better for all concerned to negotiate an early split by mutual consent. But a contract of employment is a contract and either side can choose to enforce it to the letter. I object to the employment contracts that top merchant bankers have which say that even if they wreck the company they are still entitled to full pay for their entire term, golden parachutes and pension pots to go with it. Fred the Shred being the most egregious example. > But cutting staff because you are downsizing /is/ >> a good reason, though you might have to pay some sort of severance pay >> or other compensation. You can't just tell employees to clear their >> desks on the day, but you certainly can eliminate jobs. > > Here in California, an employer can ask an employee to take their > stuff and leave, this very day or this very instant. I did that last > week. And an employee can quit without notice. I've had people walk > into my office, say "I quit", and walk out. In the UK you would only do that if someone was moving to a competitor, was guilty of gross misconduct, endangering life or serious criminal acts. You would have to pay the three months compensation and holiday allowance too. These days with multi GB media smaller than the size of a thumbnail secrets walking is virtually impossible to prevent. I have had a couple of employees escorted off the site that way. On the flip side although you can in principle enforce the three month notice on an employee it generally isn't worth the effort except possibly at more senior levels. Most people are reasonable about it in the UK, but if they are not then the employer doesn't really have much leverage against someone who is planning to leave anyway. Regards, Martin BrownArticle: 150566
OK. I finally got the display working. WOOO HOOO... Now my understanding is that to get characters on the display I have to create a character rom, and a frame buffer. The character rom I understand. I plan on making a rom that bisically contains 1's where ever a pixel is on for each character. I plan on a 8x8 font. This should give me 34 lines with 60 characters. I am a little confused on the frame buffer portion. Any pointers on where to look for information on this?Article: 150567
"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message news:bfv0k6ldmvka2jrkijvsm0af1m2tturev3@4ax.com... > Here in California, an employer can ask an employee to take their > stuff and leave, this very day or this very instant. I did that last > week. I've read stories of where a group of folks were asked to come out to the parking lot for a "meeting" and then told... oh, hey, you're laid off -- we'll be sending your personal effects to you via mail! That's pretty brutal, but I suppose it's meant to insure there's absolutely no chance someone starts to sabotage their employer... although you have to wonder what sort of relationship management has with their employees when that sort of thing crosses their minds; it kinda implies that the relationship was more one of "we're each out to exploit the other as much as possible" rather than one closer to "everyone wins." > And an employee can quit without notice. I've had people walk > into my office, say "I quit", and walk out. That's when you say, "You can't quit, because I've already fired you!" :-) ---JoelArticle: 150568
On 26 Jan., 21:05, John Larkin <jjlar...@highNOTlandTHIStechnologyPART.com> wrote: > On Tue, 25 Jan 2011 11:26:06 +0100, David Brown > > > > <da...@westcontrol.removethisbit.com> wrote: > >On 24/01/2011 23:17, John Larkin wrote: > >> On Mon, 24 Jan 2011 11:51:12 -0800 (PST), rickman<gnu...@gmail.com> > >> wrote: > ><snip> > >>> But none of this has to do with nationality. > > >>> Rick > > >It is important to distinguish between nationality and a country's laws > >and bureaucracy - the regulations in John's quotation are about a > >country's regulations, not an issue with the people. > > >>http://www.eetimes.com/electronics-news/4212317/Xilinx--sales-fall-sh..= . > > >> "Xilinx recorded $4.3 million worth of restructuring charges during > >> the recently concluded quarter. Olson said the charges were greater > >> than expected because the company is closing its software development > >> operation in France, where regulations make eliminating jobs > >> difficult." > > >> John > > >Clearly we don't know /what/ regulations are at issue here, as there > >could be many. > > >In general, you have to have good reason for firing people in Europe, > >and normally you have to give significant notice (I don't know the > >details for France, but 3 months is standard here in Norway. =A0Of cours= e, > >this also means you can't quit your job without giving 3 months notice - > >it works both ways). > > Does the law require that you remain productive during those three > months? here in Denmark it is the same 3 month minimum notice for employer after first 6 months, and it goes up by one month for ever 3 years of emplyment. It is only one month for employees. The law says you have to do you jobs as you normally would but you have the right to spend some time for job interviews etc. and an employer can't make you do jobs that you normally wouldn't. > > =A0But cutting staff because you are downsizing /is/ heres special rule that if you fire more that ~10 there has to be collective negotiations of how it is to be done and what the terms will be > > >a good reason, though you might have to pay some sort of severance pay > >or other compensation. =A0You can't just tell employees to clear their > >desks on the day, but you certainly can eliminate jobs. > > Here in California, an employer can ask an employee to take their > stuff and leave, this very day or this very instant. I did that last > week. And an employee can quit without notice. I've had people walk > into my office, say "I quit", and walk out. > > John well you can tell an employee to leave immediately you'll just have to keep paying the him for the severance period. an employer can "expel" an employee, but that'll be in real serious case like stealing, spying, working for a competitor, not showing up for work without and valid reason etc. it doesn't happen very often and usually ends up in court technically I don't think an employee has the right to just leave, but you can't someone to show up for work -LasseArticle: 150569
On 26 Jan., 18:41, Jay <jpt03...@engr.uconn.edu> wrote: > Gabor <ga...@alacron.com> wrote: > > On Jan 26, 11:07 am, Gabor <ga...@alacron.com> wrote: > >> On Jan 26, 9:32 am, Jay <jpt03...@engr.uconn.edu> wrote: > > >>> Hey all. > > >>> I'm trying to interface a Spartan 3 with a 5 volt avr. In some of Xil= inx's > >>> documentation, (www.xilinx.com/support/answers/19146.htm) it is sugge= sted > >>> that to make the S3s IO 5v tolerant, a 300 ohm resistor be used to pr= otect > >>> the port from reverse current damage. However, instill might face log= ic > >>> high problems as read from the avr. What would you suggest for a (sma= ll > >>> footprint if possible) logic level converter? > > >>> Thanks in advance. > > >> There are so many chips for level shifting that the best fit > >> will really depend on your particular design. =A0How many > >> signals do you connect between the FPGA and the 5V > >> micro? =A0How many are inputs to the FPGA, how many > >> outputs from the FPGA and how many are bidirectional? > >> Going from 3V to 5V, you probably want to look at 74ACT > >> series or something similar that can work with a 5V supply > >> but has "TTL" compatible Vih and Vil specs. =A0Going from > >> 5V to 3V you could use the resistor (unidirectional). =A0For > >> bidirectional signals there are some parts with dual power > >> supply that can provide active drive to both sides. =A0If the > >> signals are relatively slow, then you can use "Quickswitch" > >> style FET switches and pullup resistors to do level shifting > >> bidirectionally without any added control signals. > > >> Regards, > >> Gabor > > > One more point I forgot to add. =A0The resistor trick doesn't > > work with the newer Spartan 3A and 3AN series parts. > > Those FPGA's don't have clamp diodes to Vcco. > > > -- Gabor > > Yeah in saw that. I'm not using the 3a, but i do need bi directional IO. > There will be a total of 13 pins to the uC that need this treatment. > > Thanks for your help. you can't change the supply for the AVR to something lower within the specs of the FPGA? -LasseArticle: 150570
Hi,
On 01/26/11 07:30 PM, ghelbig wrote:
> On Jan 26, 4:56 am, Michael<michael_laaja...@yahoo.com> wrote:
>> Hi,
>>
>> I am trying a design that is from ISE 9.2 on the latest 12.4 using
>> CentOS 64 bit and receive the following error, I can't find anything
>> on Xilinx that refers to it.
>>
>> Anyone seen the same and know a solution?
>>
>> INTERNAL_ERROR:Portability:basutencodeimp.c:229:1.24 - Number of bytes
>> peeked
>> does not match number of bytes requested. Corrupted file?
>> INTERNAL_ERROR:Portability:basutencodeimp.c:229:1.24 - Number of bytes
>> peeked
>> does not match number of bytes requested. Corrupted file?
>> FATAL_ERROR:NgdBuild:basnbbuspin.c:87:1.20 - Empty or missing BUS_SYNTAX
>> for PM
>> base Process will terminate. For technical support on this issue,
>> please
>> open a WebCase with this project attached athttp://www.xilinx.com/support.
>> Release 12.4 - Map M.81d (lin64)
>>
>> /michael
>
> Did you translate the project or start a new one fresh? I have seen
> poor results translating ("upgrading") projects.
Its an old projekt no ISE using a Makesystem so no GUI.
>
> The error sounds like a "unix EOL vs/ DOS EOL" type of problem. Was
> the 9.2 project created in Windows?
No on Solaris
>
> CentOS is so similar to Fedora that I would not be looking at OS
> issues; odds are it is an ISE issue.
>
Correct.
> Do you have access to 9.2 on Linux? That might be an interesting
> test. (Or 12.4 on Windows...)
>
Yes, runs fine.
> Another question is "Why are you changing ISE versions?" I am seeing
> less than stellar results with version 12 (or version 11 for that
> matter).
>
> $.02,
> G.
I agree with you to not change ISE version thats why we are still on 9.2
and Solaris which is rocksolid, cant say they same for the GUIs on
Linux, they really suck.
But the reason is a test to see if we can gain something from
performance point of view(speed)
/michael
Article: 150571Hi, On 01/26/11 02:53 PM, RCIngham wrote: >> Hi, >> >> I am trying a design that is from ISE 9.2 on the latest 12.4 using >> CentOS 64 bit and receive the following error, I can't find anything >> on Xilinx that refers to it. >> >> Anyone seen the same and know a solution? >> >> >> >> INTERNAL_ERROR:Portability:basutencodeimp.c:229:1.24 - Number of bytes >> peeked >> does not match number of bytes requested. Corrupted file? >> INTERNAL_ERROR:Portability:basutencodeimp.c:229:1.24 - Number of bytes >> peeked >> does not match number of bytes requested. Corrupted file? >> FATAL_ERROR:NgdBuild:basnbbuspin.c:87:1.20 - Empty or missing BUS_SYNTAX >> for PM >> base Process will terminate. For technical support on this issue, >> please >> open a WebCase with this project attached at >> http://www.xilinx.com/support. >> Release 12.4 - Map M.81d (lin64) >> >> >> /michael >> > > Is "CentOS 64bit" a supported operating system for ISE 12.4? No, but RH is and its as close as it gets. > > You could try opening a WebCase for it at http://www.xilinx.com/support, > unless you are a student, in which case I suspect your supervisor has to do > it. > > > --------------------------------------- > Posted through http://www.FPGARelated.com Yes thats done, and Xilinx has responded very promptly :) /michaelArticle: 150572
On Wed, 26 Jan 2011 13:21:14 -0800, "Joel Koltner" <zapwireDASHgroups@yahoo.com> wrote: >"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message >news:bfv0k6ldmvka2jrkijvsm0af1m2tturev3@4ax.com... >> Here in California, an employer can ask an employee to take their >> stuff and leave, this very day or this very instant. I did that last >> week. > >I've read stories of where a group of folks were asked to come out to the >parking lot for a "meeting" and then told... oh, hey, you're laid off -- we'll >be sending your personal effects to you via mail! > >That's pretty brutal, but I suppose it's meant to insure there's absolutely no >chance someone starts to sabotage their employer... although you have to >wonder what sort of relationship management has with their employees when that >sort of thing crosses their minds; it kinda implies that the relationship was >more one of "we're each out to exploit the other as much as possible" rather >than one closer to "everyone wins." > >> And an employee can quit without notice. I've had people walk >> into my office, say "I quit", and walk out. > >That's when you say, "You can't quit, because I've already fired you!" :-) > >---Joel Nope, you always let them quit. If you fire them, they have a chance at getting unemployment, which can cost you. If they quit, they are SOL! CharlieArticle: 150573
"langwadt@fonz.dk" <langwadt@fonz.dk> wrote: > On 26 Jan., 18:41, Jay <jpt03...@engr.uconn.edu> wrote: >> Gabor <ga...@alacron.com> wrote: >>> On Jan 26, 11:07 am, Gabor <ga...@alacron.com> wrote: >>>> On Jan 26, 9:32 am, Jay <jpt03...@engr.uconn.edu> wrote: >> >>>>> Hey all. >> >>>>> I'm trying to interface a Spartan 3 with a 5 volt avr. In some of Xilinx's >>>>> documentation, (www.xilinx.com/support/answers/19146.htm) it is suggested >>>>> that to make the S3s IO 5v tolerant, a 300 ohm resistor be used to protect >>>>> the port from reverse current damage. However, instill might face logic >>>>> high problems as read from the avr. What would you suggest for a (small >>>>> footprint if possible) logic level converter? >> >>>>> Thanks in advance. >> >>>> There are so many chips for level shifting that the best fit >>>> will really depend on your particular design. How many >>>> signals do you connect between the FPGA and the 5V >>>> micro? How many are inputs to the FPGA, how many >>>> outputs from the FPGA and how many are bidirectional? >>>> Going from 3V to 5V, you probably want to look at 74ACT >>>> series or something similar that can work with a 5V supply >>>> but has "TTL" compatible Vih and Vil specs. Going from >>>> 5V to 3V you could use the resistor (unidirectional). For >>>> bidirectional signals there are some parts with dual power >>>> supply that can provide active drive to both sides. If the >>>> signals are relatively slow, then you can use "Quickswitch" >>>> style FET switches and pullup resistors to do level shifting >>>> bidirectionally without any added control signals. >> >>>> Regards, >>>> Gabor >> >>> One more point I forgot to add. The resistor trick doesn't >>> work with the newer Spartan 3A and 3AN series parts. >>> Those FPGA's don't have clamp diodes to Vcco. >> >>> -- Gabor >> >> Yeah in saw that. I'm not using the 3a, but i do need bi directional IO. >> There will be a total of 13 pins to the uC that need this treatment. >> >> Thanks for your help. > > you can't change the supply for the AVR to something lower within the > specs of > the FPGA? > > -Lasse No, I'm supporting an existing system. I've looked onto the 74act's and so far they look like what I was looking for. I was just seeing if someone had dealt with this before.Article: 150574
On Wed, 26 Jan 2011 12:05:51 -0800, the renowned John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote: >On Tue, 25 Jan 2011 11:26:06 +0100, David Brown ><david@westcontrol.removethisbit.com> wrote: > >>On 24/01/2011 23:17, John Larkin wrote: >>> On Mon, 24 Jan 2011 11:51:12 -0800 (PST), rickman<gnuarm@gmail.com> >>> wrote: >><snip> >>>> But none of this has to do with nationality. >>>> >>>> Rick >>> >>> >> >>It is important to distinguish between nationality and a country's laws >>and bureaucracy - the regulations in John's quotation are about a >>country's regulations, not an issue with the people. >> >>> http://www.eetimes.com/electronics-news/4212317/Xilinx--sales-fall-short-of-estimates >>> >>> "Xilinx recorded $4.3 million worth of restructuring charges during >>> the recently concluded quarter. Olson said the charges were greater >>> than expected because the company is closing its software development >>> operation in France, where regulations make eliminating jobs >>> difficult." >>> >>> John >>> >> >>Clearly we don't know /what/ regulations are at issue here, as there >>could be many. >> >>In general, you have to have good reason for firing people in Europe, >>and normally you have to give significant notice (I don't know the >>details for France, but 3 months is standard here in Norway. Of course, >>this also means you can't quit your job without giving 3 months notice - >>it works both ways). > >Does the law require that you remain productive during those three >months? > > > But cutting staff because you are downsizing /is/ >>a good reason, though you might have to pay some sort of severance pay >>or other compensation. You can't just tell employees to clear their >>desks on the day, but you certainly can eliminate jobs. > >Here in California, an employer can ask an employee to take their >stuff and leave, this very day or this very instant. I did that last >week. And an employee can quit without notice. I've had people walk >into my office, say "I quit", and walk out. > >John There are more restrictive federal rules for things of the scale of the Xilinx closing:- http://ecfr.gpoaccess.gov/cgi/t/text/text-idx?c=ecfr&tpl=/ecfrbrowse/Title20/20cfr639_main_02.tpl (60 day written notice) Best regards, Spehro Pefhany -- "it's the network..." "The Journey is the reward" speff@interlog.com Info for manufacturers: http://www.trexon.com Embedded software/hardware/analog Info for designers: http://www.speff.com
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