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Threads Starting May 2004
69234: 04/05/01: William: Nexar for FPGA Design?
69235: 04/05/01: David Brown: Connecting a crystal to a Cyclone or Max PLD
69236: 04/05/01: Marc Guardiani: Re: Connecting a crystal to a Cyclone or Max PLD
69237: 04/05/02: glen herrmannsfeldt: Re: Connecting a crystal to a Cyclone or Max PLD
69238: 04/05/02: Jim Granville: Re: Connecting a crystal to a Cyclone or Max PLD
69242: 04/05/02: Kasper Pedersen: Re: Connecting a crystal to a Cyclone or Max PLD
69246: 04/05/03: David Brown: Re: Connecting a crystal to a Cyclone or Max PLD
69269: 04/05/03: Greg Steinke: Re: Connecting a crystal to a Cyclone or Max PLD
69271: 04/05/03: Peter Alfke: Re: Connecting a crystal to a Cyclone or Max PLD
69275: 04/05/04: glen herrmannsfeldt: Re: Connecting a crystal to a Cyclone or Max PLD
69281: 04/05/04: Peter Alfke: Re: Connecting a crystal to a Cyclone or Max PLD
69289: 04/05/05: glen herrmannsfeldt: Re: Connecting a crystal to a Cyclone or Max PLD
69304: 04/05/05: Peter Alfke: Re: Connecting a crystal to a Cyclone or Max PLD
69240: 04/05/02: Jim: frequency multiplication
69259: 04/05/03: Peter Alfke: Re: frequency multiplication
69267: 04/05/03: MM: Re: frequency multiplication
69268: 04/05/03: Peter Alfke: Re: frequency multiplication
69307: 04/05/05: Walter Dvorak: Re: frequency multiplication
69243: 04/05/02: Florian Student: Cheap SRAM?
69247: 04/05/03: Dave Garnett: Re: Cheap SRAM?
69253: 04/05/03: john jakson: Re: Cheap SRAM?
69258: 04/05/03: John_H: Re: Cheap SRAM?
69244: 04/05/02: Josh Graham: Behavioural Simulation of a RPM using ModelSim XE
69248: 04/05/03: Martin Schoeberl: [ANN] Altera Cyclone EP1C12 FPGA Board
69250: 04/05/03: Jan Losansky: XILINX System Generator "fatal error"
69265: 04/05/03: Matthew E Rosenthal: Re: XILINX System Generator "fatal error"
69274: 04/05/04: Jan Losansky: Re: XILINX System Generator "fatal error"
69251: 04/05/03: Joe: Fast multiplication with Nios and C (Altera Stratix)
69255: 04/05/03: Frank van Eijkelenburg: timing constraints
69260: 04/05/03: Symon: Re: timing constraints
69273: 04/05/04: Frank van Eijkelenburg: Re: timing constraints
69282: 04/05/04: Symon: Re: timing constraints
69256: 04/05/03: George: Best way to handle multiple common data busses in Altera FPGA (and others)
69262: 04/05/03: Gary Pace: Re: Best way to handle multiple common data busses in Altera FPGA (and others)
69263: 04/05/03: Andy Peters: Re: Best way to handle multiple common data busses in Altera FPGA (and others)
69266: 04/05/03: Mike Treseler: Re: Best way to handle multiple common data busses in Altera FPGA (and others)
69270: 04/05/03: Gabor Szakacs: Re: Best way to handle multiple common data busses in Altera FPGA (and others)
69280: 04/05/04: George: Re: Best way to handle multiple common data busses in Altera FPGA (and others)
69285: 04/05/04: Jesse Kempa: Re: Best way to handle multiple common data busses in Altera FPGA (and others)
69276: 04/05/04: Ken: [ANN] DSP for FPGAs 4-Day Course
69277: 04/05/04: Christian Haase: ASIC design
69279: 04/05/04: Adarsh Kumar Jain: Stratix - Virtex2Pro Co-Simulation using modelsim !
69283: 04/05/04: raj: synthsizing multi-dimensional array XST
69288: 04/05/05: Petter Gustad: Altera SoPC builder command line system generator
69300: 04/05/05: Jesse Kempa: Re: Altera SoPC builder command line system generator
69315: 04/05/06: Petter Gustad: Re: Altera SoPC builder command line system generator
69290: 04/05/04: Joe Vanderwall: How to drive record fields from procedure AND testbench?
69306: 04/05/05: Jim Lewis: Re: How to drive record fields from procedure AND testbench?
69308: 04/05/05: Mike Treseler: Re: How to drive record fields from procedure AND testbench?
69313: 04/05/05: Peter Sommerfeld: Re: How to drive record fields from procedure AND testbench?
69329: 04/05/06: Mike Treseler: Re: How to drive record fields from procedure AND testbench?
69333: 04/05/06: Peter Sommerfeld: Re: How to drive record fields from procedure AND testbench?
69335: 04/05/06: Jim Lewis: Re: How to drive record fields from procedure AND testbench?
69337: 04/05/06: Jim Lewis: Re: How to drive record fields from procedure AND testbench?
69342: 04/05/07: Peter Sommerfeld: Re: How to drive record fields from procedure AND testbench?
69348: 04/05/07: Jim Lewis: Re: How to drive record fields from procedure AND testbench?
69352: 04/05/07: Tom Hawkins: Re: How to drive record fields from procedure AND testbench?
69376: 04/05/09: Peter Sommerfeld: Re: How to drive record fields from procedure AND testbench?
69291: 04/05/04: Matthew E Rosenthal: chipscope nuance question?
69299: 04/05/05: Symon: Re: chipscope nuance question?
69301: 04/05/05: Matthew E Rosenthal: Re: chipscope nuance question?
69292: 04/05/05: Student: Wire crossing in a large partially reconfigurable design.
69330: 04/05/06: Kevin Neilson: Re: Wire crossing in a large partially reconfigurable design.
69332: 04/05/06: Ray Andraka: Re: Wire crossing in a large partially reconfigurable design.
69334: 04/05/07: Student: Re: Wire crossing in a large partially reconfigurable design.
69293: 04/05/05: javid: Max7000s: how to use the enable of the dffe flip-flop?
69296: 04/05/05: Marc Randolph: Re: Max7000s: how to use the enable of the dffe flip-flop?
69318: 04/05/06: javid: Re: Max7000s: how to use the enable of the dffe flip-flop?
69320: 04/05/06: Marc Randolph: Re: Max7000s: how to use the enable of the dffe flip-flop?
69321: 04/05/06: Luc Braeckman: Re: Max7000s: how to use the enable of the dffe flip-flop?
69328: 04/05/06: Symon: Re: Max7000s: how to use the enable of the dffe flip-flop?
69297: 04/05/05: Thomas Reinemann: ChipScope Core Generator Flow
69358: 04/05/07: Jim Wu: Re: ChipScope Core Generator Flow
69360: 04/05/07: Symon: Re: ChipScope Core Generator Flow
69394: 04/05/10: Thomas Reinemann: Re: ChipScope Core Generator Flow
69298: 04/05/05: John Providenza: XST, Virtex2-Pro, odd PAR counter timing failure
69302: 04/05/05: Ray Andraka: Re: XST, Virtex2-Pro, odd PAR counter timing failure
69303: 04/05/05: Symon: Re: XST, Virtex2-Pro, odd PAR counter timing failure
69326: 04/05/06: John Providenza: Re: XST, Virtex2-Pro, odd PAR counter timing failure
69305: 04/05/05: viswanath: costal loop question
69322: 04/05/06: Rajeev: Re: costal loop question
69309: 04/05/05: Matthew E Rosenthal: V2p block ram clock -> Q delay help
69311: 04/05/05: Peter Alfke: Re: V2p block ram clock -> Q delay help
69312: 04/05/05: Matthew E Rosenthal: Re: V2p block ram clock -> Q delay help
69327: 04/05/06: Brian Philofsky: Re: V2p block ram clock -> Q delay help
69550: 04/05/13: thangkho: Re: V2p block ram clock -> Q delay help
69553: 04/05/13: Ray Andraka: Re: V2p block ram clock -> Q delay help
69558: 04/05/13: Matthew E Rosenthal: Re: V2p block ram clock -> Q delay help
69561: 04/05/13: Ray Andraka: Re: V2p block ram clock -> Q delay help
69310: 04/05/05: fhleung: bitgen progarm in ISE
69314: 04/05/06: Jim Wu: Re: bitgen progarm in ISE
69316: 04/05/06: fhleung: Re: bitgen progarm in ISE
69317: 04/05/06: Sean Durkin: Re: bitgen progarm in ISE
69319: 04/05/06: Petter Gustad: Re: bitgen progarm in ISE
69323: 04/05/06: Tom: headers linker script
69325: 04/05/06: Kenneth Land: Mutiple Quartus Instances?
69338: 04/05/07: Petter Gustad: Re: Mutiple Quartus Instances?
69347: 04/05/07: George: Re: Mutiple Quartus Instances?
69341: 04/05/07: Subroto Datta: Re: Mutiple Quartus Instances?
69350: 04/05/07: Kenneth Land: Re: Mutiple Quartus Instances?
69336: 04/05/06: Joel Hardy: Which board to buy? Status of open source tools?
69339: 04/05/07: Jon Beniston: Re: Which board to buy? Status of open source tools?
69346: 04/05/07: David Brown: Re: Which board to buy? Status of open source tools?
69405: 04/05/10: Tom Hawkins: Re: Which board to buy? Status of open source tools?
69421: 04/05/10: rickman: Re: Which board to buy? Status of open source tools?
69427: 04/05/11: David Brown: Re: Which board to buy? Status of open source tools?
69452: 04/05/11: rickman: Re: Which board to buy? Status of open source tools?
69474: 04/05/11: David Brown: Re: Which board to buy? Status of open source tools?
69428: 04/05/11: Martin Thompson: Re: Which board to buy? Status of open source tools?
69437: 04/05/11: Tom Hawkins: Re: Which board to buy? Status of open source tools?
69456: 04/05/11: rickman: Re: Which board to buy? Status of open source tools?
69640: 04/05/17: Chuck McManis: Re: Which board to buy? Status of open source tools?
69340: 04/05/07: john jakson: Re: Which board to buy? Status of open source tools?
69365: 04/05/08: Alex Gibson: Re: Which board to buy? Status of open source tools?
69366: 04/05/08: Alex Gibson: Re: Which board to buy? Status of open source tools?
69370: 04/05/08: Martin Schoeberl: Re: Which board to buy? Status of open source tools?
69385: 04/05/09: Vaughn Betz: Re: Which board to buy? Status of open source tools?
69410: 04/05/10: Anna Acevedo: Re: Which board to buy? Status of open source tools?
69464: 04/05/11: nospam: Re: Which board to buy? Status of open source tools?
69343: 04/05/07: Jerzy: Virtex2 (500) DCM Frequency Synthesize
69345: 04/05/07: Austin Lesea: Re: Virtex2 (500) DCM Frequency Synthesize
69351: 04/05/07: Peter Alfke: Re: Virtex2 (500) DCM Frequency Synthesize
69368: 04/05/08: Jerzy: Re: Virtex2 (500) DCM Frequency Synthesize
69344: 04/05/07: J?rgen: Error while simulation with XILINX DCM
69357: 04/05/07: Jim Wu: Re: Error while simulation with XILINX DCM
69386: 04/05/10: J?rgen: Re: Error while simulation with XILINX DCM
69389: 04/05/10: J?rgen: Re: Error while simulation with XILINX DCM
69393: 04/05/10: news.utanet.at: Re: Error while simulation with XILINX DCM
69651: 04/05/17: Alan Fitch: Re: Error while simulation with XILINX DCM
69349: 04/05/07: David Rogoff: Where did Altera tech support go?????
69353: 04/05/07: Gary Olson: Muxes : 64X1
69354: 04/05/07: Gary Olson: Re: Muxes : 64X1
69355: 04/05/07: Symon: Re: Muxes : 64X1
69356: 04/05/07: Gary Olson: Re: Muxes : 64X1
69372: 04/05/08: Ray Andraka: Re: Muxes : 64X1
69359: 04/05/07: Kenneth Land: SignalProbe in Quartus...
69362: 04/05/08: Gary Pace: Re: SignalProbe in Quartus...
69369: 04/05/08: Subroto Datta: Re: SignalProbe in Quartus...
69361: 04/05/07: ram: OPB IPIF user logic
69375: 04/05/09: Antonio Di Stefano: Re: OPB IPIF user logic
69363: 04/05/07: Jim Carlock: Re: How to remove an unintended Right-click menu?
69364: 04/05/08: Kelly: Re: How to remove an unintended Right-click menu?
69367: 04/05/08: GL: downloading a non-volitle design (xilinx)
69371: 04/05/08: LK Allen: Director of Applications/FPGA
69373: 04/05/09: rat: is it possible to design usb only with fpga?
69423: 04/05/11: jtw: Re: is it possible to design usb only with fpga?
69465: 04/05/11: Antonio Pasini: Re: is it possible to design usb only with fpga?
69470: 04/05/11: Symon: Re: is it possible to design usb only with fpga?
69635: 04/05/17: Chuck McManis: Re: is it possible to design usb only with fpga?
69377: 04/05/09: Martin Maurer: VHDL Beginner: Reset a counter (instead of "000000000....000000") - better way ?
69380: 04/05/09: Jason Berringer: Re: VHDL Beginner: Reset a counter (instead of "000000000....000000") - better way ?
69381: 04/05/10: Allan Herriman: Re: VHDL Beginner: Reset a counter (instead of "000000000....000000") - better way ?
69422: 04/05/11: jtw: Re: VHDL Beginner: Reset a counter (instead of "000000000....000000") - better way ?
69429: 04/05/11: Martin Thompson: Re: VHDL Beginner: Reset a counter (instead of "000000000....000000") - better way ?
69438: 04/05/11: Rajeev: Re: VHDL Beginner: Reset a counter (instead of "000000000....000000") - better way ?
69445: 04/05/11: =?iso-8859-1?Q?Michael_Sch=F6berl?=: Re: VHDL Beginner: Reset a counter (instead of "000000000....000000") - better way ?
69473: 04/05/11: Ray Andraka: Re: VHDL Beginner: Reset a counter (instead of "000000000....000000") -
69378: 04/05/09: Dave: Floating Point With Xilinx EDK (PPC)?
69387: 04/05/10: Jon Beniston: Re: Floating Point With Xilinx EDK (PPC)?
69406: 04/05/10: Dave: Re: Floating Point With Xilinx EDK (PPC)?
69420: 04/05/10: Siddharth Rele: Re: Floating Point With Xilinx EDK (PPC)?
69441: 04/05/11: Jon Beniston: Re: Floating Point With Xilinx EDK (PPC)?
69483: 04/05/11: Dave: Re: Floating Point With Xilinx EDK (PPC)?
69497: 04/05/12: Sean Durkin: Re: Floating Point With Xilinx EDK (PPC)?
69522: 04/05/12: Dave: Re: Floating Point With Xilinx EDK (PPC)?
69542: 04/05/13: Sean Durkin: Re: Floating Point With Xilinx EDK (PPC)?
69379: 04/05/09: Matthieu Benoit: Altera EPM7032LC44 programming w/ ALL-03A Hilo
69382: 04/05/09: fhleung: bitgen program in ISE generate readback bitstream
69383: 04/05/10: Allan Herriman: Equivalent Register Removal in XST
69384: 04/05/10: Weddick: Serial Data Capture
69391: 04/05/10: Marc Randolph: Re: Serial Data Capture
69424: 04/05/11: Weddick: Re: Serial Data Capture
69388: 04/05/10: GreateWhite.DK: Bootloader question
69442: 04/05/11: Jon Beniston: Re: Bootloader question
69390: 04/05/10: ALuPin: How to perform a timing simulation in Modelsim with QuartusII output file ?
69413: 04/05/10: Andy Peters: Re: How to perform a timing simulation in Modelsim with QuartusII output file ?
69425: 04/05/10: ALuPin: Re: How to perform a timing simulation in Modelsim with QuartusII output file ?
69392: 04/05/10: Rajesh Murugesan: Can I use an internal reset signal in DLL?
69395: 04/05/10: Tom Hawkins: One issue about free hardware
69401: 04/05/10: Jim Lewis: RAM inference and Standards
69409: 04/05/10: Andy Peters: Re: One issue about free hardware
69426: 04/05/11: Adam Megacz: Re: One issue about free hardware
69431: 04/05/11: Jon Beniston: Re: One issue about free hardware
69439: 04/05/11: Jeff Cunningham: Re: One issue about free hardware
69477: 04/05/11: Jon Beniston: Re: One issue about free hardware
69488: 04/05/12: kal: Re: One issue about free hardware
69489: 04/05/12: Martin Thompson: Re: One issue about free hardware
69511: 04/05/12: Jon Beniston: Re: One issue about free hardware
69529: 04/05/13: Martin Thompson: Re: One issue about free hardware
69547: 04/05/13: Tom Hawkins: Re: One issue about free hardware
69568: 04/05/14: Martin Thompson: Re: One issue about free hardware
69569: 04/05/14: Jon Beniston: Re: One issue about free hardware
69600: 04/05/14: john jakson: Re: One issue about free hardware
69608: 04/05/15: Jon Beniston: Re: One issue about free hardware
69617: 04/05/15: Jim Lewis: Re: One issue about free hardware
69702: 04/05/18: rickman: Re: One issue about free hardware
69467: 04/05/11: Mike Treseler: Re: One issue about free hardware
69517: 04/05/13: Joe: Re: One issue about free hardware
69540: 04/05/13: David Brown: Re: One issue about free hardware
69587: 04/05/14: Roger Larsson: Re: One issue about free hardware
69590: 04/05/14: Jon Beniston: Re: One issue about free hardware
69594: 04/05/14: Mike Treseler: Re: One issue about free hardware
69599: 04/05/14: Jon Beniston: Re: One issue about free hardware
69612: 04/05/15: David Brown: Re: One issue about free hardware
69396: 04/05/10: Matthias =?iso-8859-1?Q?M=FCller?=: PCIX DMA Serverworks chipset
69400: 04/05/10: Mark Schellhorn: Re: PCIX DMA Serverworks chipset
69397: 04/05/10: Pszemol: 80186 processor core
69399: 04/05/10: arkaitz: Instantiating subblock signals with VHDL
69526: 04/05/13: Srinivasan Venkataramanan: Re: Instantiating subblock signals with VHDL
69578: 04/05/14: Mike Treseler: Re: Instantiating subblock signals with VHDL
69674: 04/05/18: Jeff Cunningham: Re: Instantiating subblock signals with VHDL
69403: 04/05/10: vax,3900: Monolithic state machine or structured state machine?
69408: 04/05/10: Jim Lewis: Re: Monolithic state machine or structured state machine?
69480: 04/05/11: Hal Murray: Re: Monolithic state machine or structured state machine?
69411: 04/05/10: James Morrison: Re: Monolithic state machine or structured state machine?
69412: 04/05/10: Jim Lewis: Re: Monolithic state machine or structured state machine?
69418: 04/05/10: Mike Treseler: Re: Monolithic state machine or structured state machine?
69450: 04/05/11: Brian Drummond: Re: Monolithic state machine or structured state machine?
69404: 04/05/10: vax,3900: How to simulator XILINX CPLD with off_chip wiring?
69414: 04/05/10: Amontec Team, Laurent Gauch: unused IO on SPARTAN-IIE
69417: 04/05/10: Austin Lesea: Re: unused IO on SPARTAN-IIE
69518: 04/05/12: Chris Cheung: Re: unused IO on SPARTAN-IIE
69552: 04/05/13: Amontec Team, Laurent Gauch: Re: unused IO on SPARTAN-IIE
69555: 04/05/13: E.S.: Re: unused IO on SPARTAN-IIE
69430: 04/05/11: gebirgeraider: instantiate an edf module with ise
69562: 04/05/14: Jim Wu: Re: instantiate an edf module with ise
69432: 04/05/11: José da Rocha: FPGA vs Microprocessor: newbie question
69434: 04/05/11: Marc Randolph: Re: FPGA vs Microprocessor: newbie question
69463: 04/05/11: Chris Cheung: Re: FPGA vs Microprocessor: newbie question
69469: 04/05/11: Rene Tschaggelar: Re: FPGA vs Microprocessor: newbie question
69433: 04/05/11: Stijn Goris: FPGA wanted
69436: 04/05/11: Ray Andraka: Re: FPGA wanted
69443: 04/05/11: Stijn Goris: Re: FPGA wanted
69472: 04/05/11: Ray Andraka: Re: FPGA wanted
69476: 04/05/12: Jim Granville: Re: FPGA wanted
69453: 04/05/11: Stijn Goris: Re: FPGA wanted
69462: 04/05/11: valentin tihomirov: Re: FPGA wanted
69479: 04/05/12: Kelvin @ SG: Re: FPGA wanted
69435: 04/05/11: stockton: VHDL Standard Supported by Xilinx ISE 6.1
69440: 04/05/11: Dave Marsh: Effects of moisture on CPLD
69444: 04/05/11: Austin Lesea: Re: Effects of moisture on CPLD
69447: 04/05/11: Dave Marsh: Re: Effects of moisture on CPLD
69457: 04/05/11: Austin Lesea: Re: Effects of moisture on CPLD
69448: 04/05/11: Leon Heller: Re: Effects of moisture on CPLD
69454: 04/05/11: Dave Marsh: Re: Effects of moisture on CPLD
69461: 04/05/11: Leon Heller: Re: Effects of moisture on CPLD
69666: 04/05/17: Jon Elson: Re: Effects of moisture on CPLD
69560: 04/05/13: Andy Peters: Re: Effects of moisture on CPLD
69575: 04/05/14: Dave Marsh: Re: Effects of moisture on CPLD
69615: 04/05/15: john jakson: Re: Effects of moisture on CPLD
69652: 04/05/17: Dave Marsh: Re: Effects of moisture on CPLD
69701: 04/05/18: rickman: Re: Effects of moisture on CPLD
70320: 04/06/12: res0uffu: Re: Effects of moisture on CPLD
69446: 04/05/11: Spyros Lyberis: Logiclock TCL flow -- near completion
70231: 04/06/09: Stephen Brown: Re: Logiclock TCL flow -- near completion
69451: 04/05/11: Francisco Rodriguez: Constraints interaction report
69458: 04/05/11: Symon: How do I find where P&R has placed my BRAM?
69492: 04/05/12: =?iso-8859-15?Q?Michael_Sch=F6berl?=: Re: How do I find where P&R has placed my BRAM?
69513: 04/05/12: Symon: Re: How do I find where P&R has placed my BRAM?
69468: 04/05/11: Mike Wirthlin: MOCA Design 2005
69475: 04/05/11: Fabio G.: Looking for Synario 3.0 (Lattice)
69509: 04/05/12: Dwayne Surdu-Miller: Re: Looking for Synario 3.0 (Lattice)
69512: 04/05/12: Fabio G.: Re: Looking for Synario 3.0 (Lattice)
69516: 04/05/13: Jim Granville: Re: Looking for Synario 3.0 (Lattice)
69528: 04/05/13: Fabio G.: Re: Looking for Synario 3.0 (Lattice)
69537: 04/05/13: Jim Granville: Re: Looking for Synario 3.0 (Lattice)
69556: 04/05/13: Fabio G.: Re: Looking for Synario 3.0 (Lattice)
69557: 04/05/14: Jim Granville: Re: Looking for Synario 3.0 (Lattice)
69567: 04/05/14: Fabio G.: Re: Looking for Synario 3.0 (Lattice)
69570: 04/05/14: Jim Granville: Re: Looking for Synario 3.0 (Lattice)
69605: 04/05/14: David Cooprider: Re: Looking for Synario 3.0 (Lattice)
69630: 04/05/16: Fabio G.: Re: Looking for Synario 3.0 (Lattice)
69478: 04/05/11: fhleung: reading bitstream in FPGA
69486: 04/05/12: Sean Durkin: Re: reading bitstream in FPGA
69481: 04/05/11: raj: VHDL-Verilog Co-Simulation
69490: 04/05/12: Allan Herriman: Re: VHDL-Verilog Co-Simulation
69482: 04/05/12: SneakerNet: FPGA + CF
69487: 04/05/12: Rene Tschaggelar: Re: FPGA + CF
69495: 04/05/12: Student: Re: FPGA + CF
69510: 04/05/12: Pablo Bleyer Kocik: Re: FPGA + CF
69485: 04/05/11: Bob Armstrong: Schematic/Service manual needed for EE Tools TopMax Programmer
69491: 04/05/12: Iwo Mergler: Compact Flash FPGA card
69523: 04/05/13: John Williams: Re: Compact Flash FPGA card
69525: 04/05/13: Student: Re: Compact Flash FPGA card
69536: 04/05/13: Iwo Mergler: Re: Compact Flash FPGA card
69535: 04/05/13: Iwo Mergler: Re: Compact Flash FPGA card
69496: 04/05/12: arkaitz: Mapping port for simulation only in VHDL
69499: 04/05/12: Stefan Frank: Re: Mapping port for simulation only in VHDL
69533: 04/05/13: arkaitz: Re: Mapping port for simulation only in VHDL
69504: 04/05/12: <news@rtrussell.co.uk>: Disabling bus-hold on XC9500XL
69505: 04/05/12: Brad Smallridge: Video Blob Analysis on FPGAs
69582: 04/05/14: Brad Smallridge: Re: Video Blob Analysis on FPGAs
69595: 04/05/14: Mike Treseler: Re: Video Blob Analysis on FPGAs
69618: 04/05/15: Brad Smallridge: Re: Video Blob Analysis on FPGAs
69620: 04/05/16: Chuck McManis: Re: Video Blob Analysis on FPGAs
69660: 04/05/17: Brad Smallridge: Re: Video Blob Analysis on FPGAs
69678: 04/05/18: Chuck McManis: Re: Video Blob Analysis on FPGAs
69740: 04/05/19: Jonathan Bromley: Re: Video Blob Analysis on FPGAs
69627: 04/05/16: Erik Widding: Re: Video Blob Analysis on FPGAs
69663: 04/05/17: Brad Smallridge: Re: Video Blob Analysis on FPGAs
69763: 04/05/19: Erik Widding: Re: Video Blob Analysis on FPGAs
69508: 04/05/12: nospam: virtex dev board?
69530: 04/05/13: Sean Durkin: Re: virtex dev board?
69532: 04/05/13: Sean Durkin: Re: virtex dev board?
69581: 04/05/14: myren, lord: Re: virtex dev board?
69585: 04/05/14: Austin Lesea: Re: virtex dev board?
69515: 04/05/12: Alt Torsten: APEX20KE PPA configuration error
69519: 04/05/12: azcycle: Decompiler for GAL JEDEC fusemap
69520: 04/05/13: Jim Granville: Re: Decompiler for GAL JEDEC fusemap
69521: 04/05/12: azcycle: Re: Decompiler for GAL JEDEC fusemap
69524: 04/05/13: rat: program flash memory through JTAG on FPGA
69554: 04/05/13: Jim Wu: Re: program flash memory through JTAG on FPGA
69559: 04/05/13: Andy Peters: Re: program flash memory through JTAG on FPGA
69564: 04/05/14: Petter Gustad: Re: program flash memory through JTAG on FPGA
69583: 04/05/14: Ryan Laity: Re: program flash memory through JTAG on FPGA
69596: 04/05/14: Eric Crabill: Re: program flash memory through JTAG on FPGA
69774: 04/05/19: E.S.: Re: program flash memory through JTAG on FPGA
69776: 04/05/19: Eric Crabill: Re: program flash memory through JTAG on FPGA
69803: 04/05/20: E.S.: Re: program flash memory through JTAG on FPGA
69806: 04/05/20: Symon: Re: program flash memory through JTAG on FPGA
69833: 04/05/21: Petter Gustad: Re: program flash memory through JTAG on FPGA
69840: 04/05/21: Symon: Re: program flash memory through JTAG on FPGA
69844: 04/05/21: Petter Gustad: Re: program flash memory through JTAG on FPGA
69814: 04/05/20: Andy Peters: Re: program flash memory through JTAG on FPGA
69818: 04/05/20: Jesse Kempa: Re: program flash memory through JTAG on FPGA
69527: 04/05/12: Ashant: synthesising VHDL for Xilinx FPGAs using ISE 6.1i
69531: 04/05/13: Mario Trams: Re: synthesising VHDL for Xilinx FPGAs using ISE 6.1i
69538: 04/05/13: =?iso-8859-1?Q?Michael_Sch=F6berl?=: Re: synthesising VHDL for Xilinx FPGAs using ISE 6.1i
69539: 04/05/13: Mario Trams: Re: synthesising VHDL for Xilinx FPGAs using ISE 6.1i
69622: 04/05/16: Ashant: Re: synthesising VHDL for Xilinx FPGAs using ISE 6.1i
69534: 04/05/13: Petter Gustad: ISE 6.2i Synopsys Design Compiler libraries?
69591: 04/05/14: Jon Beniston: Re: ISE 6.2i Synopsys Design Compiler libraries?
69687: 04/05/18: Petter Gustad: Re: ISE 6.2i Synopsys Design Compiler libraries?
69541: 04/05/13: GreateWhite.DK: Anyone who has worked with Altera Cyclone???
69543: 04/05/13: Kenneth Land: Re: Anyone who has worked with Altera Cyclone???
69566: 04/05/14: GreateWhite.DK: Re: Anyone who has worked with Altera Cyclone???
69545: 04/05/13: Jeroen: Re: Anyone who has worked with Altera Cyclone???
69544: 04/05/13: Jeroen: EPCS4 Configuration+firmware, Quartus problem
69546: 04/05/13: Kenneth Land: Re: EPCS4 Configuration+firmware, Quartus problem
69548: 04/05/13: Winston: Re: EPCS4 Configuration+firmware, Quartus problem
69549: 04/05/13: winston: Updating a XILINX Project
69563: 04/05/14: Sean Durkin: Re: Updating a XILINX Project
69551: 04/05/13: Anil Khanna: Using a FDDRCPE primitive. VIRTEX-II
69572: 04/05/14: Gabor Szakacs: Re: Using a FDDRCPE primitive. VIRTEX-II
69565: 04/05/14: Fred Ma: Simple way to generate random netlists of ALU cells
69573: 04/05/14: john jakson: Re: Simple way to generate random netlists of ALU cells
69588: 04/05/14: Fred Ma: Re: Simple way to generate random netlists of ALU cells
69593: 04/05/14: Ray Andraka: Re: Simple way to generate random netlists of ALU cells
69601: 04/05/15: Fred Ma: Re: Simple way to generate random netlists of ALU cells
69602: 04/05/15: Fred Ma: Re: Simple way to generate random netlists of ALU cells
69610: 04/05/15: john jakson: Re: Simple way to generate random netlists of ALU cells
69613: 04/05/15: Fred Ma: Re: Simple way to generate random netlists of ALU cells
69672: 04/05/17: Ray Andraka: Re: Simple way to generate random netlists of ALU cells
69681: 04/05/18: Fred Ma: Re: Simple way to generate random netlists of ALU cells
69571: 04/05/14: Florian Student: Quartus II Web Edition
69574: 04/05/14: Subroto Datta: Re: Quartus II Web Edition
69576: 04/05/14: Ray Andraka: Re: Quartus II Web Edition
69577: 04/05/14: Kenneth Land: Re: Quartus II Web Edition
69579: 04/05/14: Rene Tschaggelar: Re: Quartus II Web Edition
69580: 04/05/14: geoffrey wall: best fpga development board?
69584: 04/05/14: Symon: Re: best fpga development board?
69586: 04/05/14: geoffrey wall: Re: best fpga development board?
69621: 04/05/15: Rajeev: Re: best fpga development board?
69589: 04/05/14: Jon Beniston: Re: best fpga development board?
69603: 04/05/14: Tom Seim: Re: best fpga development board?
69604: 04/05/15: Alex Gibson: Re: best fpga development board?
69624: 04/05/16: Jesse Kempa: Re: best fpga development board?
69625: 04/05/16: Kenneth Land: Re: best fpga development board?
69592: 04/05/14: William H. Maddox III: Clueless newbie question -- what has changed to make moisture such
69606: 04/05/15: Gregory C. Read: Re: Clueless newbie question -- what has changed to make moisture such an issue?
69611: 04/05/15: john jakson: Re: Clueless newbie question -- what has changed to make moisture such an issue?
69597: 04/05/14: MM: 5V signals at Spartan-IIE inputs
69598: 04/05/14: Andras Tantos: Re: 5V signals at Spartan-IIE inputs
69607: 04/05/15: tushit: Quartus Internal Errors
69614: 04/05/15: Subroto Datta: Re: Quartus Internal Errors
69609: 04/05/15: Fred Ma: MCNC benchmarks (was: Simple way to generate random netlists of ALU
69616: 04/05/15: Alessandro Scaglione: EDK6.1 MBlaze : problems with INTC IPIF and external interrupts
69629: 04/05/16: Matthew Ouellette: Re: EDK6.1 MBlaze : problems with INTC IPIF and external interrupts
69646: 04/05/17: Alessandro Scaglione: Re: EDK6.1 MBlaze : problems with INTC IPIF and external interrupts
69667: 04/05/17: Matthew Ouellette: Re: EDK6.1 MBlaze : problems with INTC IPIF and external interrupts
69619: 04/05/15: Ed Anuff: FPGA Timing question
69628: 04/05/16: Symon: Re: FPGA Timing question
69661: 04/05/17: Gabor Szakacs: Re: FPGA Timing question
69623: 04/05/16: Martin Maurer: Internal Signals and other questions with ModelSim XE/II Starter 5.7g VHDL Testbench
69626: 04/05/16: Mike Treseler: Re: Internal Signals and other questions with ModelSim XE/II Starter
69821: 04/05/20: Charles Bailey: Re: Internal Signals and other questions with ModelSim XE/II Starter 5.7g VHDL Testbench
69631: 04/05/17: Florian Student: drive multiple outputs with the same value on EPM3064?
69632: 04/05/16: Chuck McManis: Phase relationship management
69634: 04/05/16: Hal Murray: Re: Phase relationship management
69639: 04/05/17: Jim Granville: Re: Phase relationship management
69642: 04/05/17: Philip Freidin: Re: Phase relationship management
69643: 04/05/17: Hal Murray: Re: Phase relationship management
69679: 04/05/18: Chuck McManis: Re: Phase relationship management
69688: 04/05/18: Philip Freidin: Re: Phase relationship management
69798: 04/05/20: Hal Murray: Re: Phase relationship management
69633: 04/05/16: jacobo: Please, I need help with a mpeg layer 1 decoder in vhdl
69636: 04/05/17: Bob Perlman: Re: Please, I need help with a mpeg layer 1 decoder in vhdl
69637: 04/05/17: Bob: Re: Please, I need help with a mpeg layer 1 decoder in vhdl
69644: 04/05/17: jacobo: Re: Please, I need help with a mpeg layer 1 decoder in vhdl
69638: 04/05/17: Chuck McManis: std_logic_vector vs unsigned
69647: 04/05/17: Martin Thompson: Re: std_logic_vector vs unsigned
69654: 04/05/17: Symon: Re: std_logic_vector vs unsigned
69675: 04/05/18: Jeff Cunningham: Re: std_logic_vector vs unsigned
69677: 04/05/18: Chuck McManis: Re: std_logic_vector vs unsigned
69685: 04/05/18: Martin Thompson: Re: std_logic_vector vs unsigned
69695: 04/05/18: Ralf Hildebrandt: Re: std_logic_vector vs unsigned
69641: 04/05/16: raj: load on a clock signal in FPGA
69653: 04/05/17: Marc Randolph: Re: load on a clock signal in FPGA
69665: 04/05/17: Jon Elson: Re: load on a clock signal in FPGA
69645: 04/05/17: ALuPin: Phase alignment
69648: 04/05/17: Dave: Low cost FPGA dev board with high speed i/f?
69670: 04/05/17: Will: Re: Low cost FPGA dev board with high speed i/f?
69693: 04/05/18: John Adair: Re: Low cost FPGA dev board with high speed i/f?
69649: 04/05/17: Basuki Endah Priyanto: Xilinx Foundation [*.SCH -> *.VHD]
69659: 04/05/17: Gabor Szakacs: Re: Xilinx Foundation [*.SCH -> *.VHD]
69650: 04/05/17: Basuki Endah Priyanto: Re: FPGA vs Microprocessor: newbie question
69655: 04/05/17: Anders: How to replace Triscend - Xilinx plans for the future
69657: 04/05/17: Amontec, Larry: Re: How to replace Triscend - Xilinx plans for the future
69669: 04/05/18: Jim Granville: Re: How to replace Triscend - Xilinx plans for the future
69719: 04/05/19: Jim Granville: Re: How to replace Triscend - Xilinx plans for the future
69764: 04/05/19: rickman: Re: How to replace Triscend - Xilinx plans for the future
69783: 04/05/20: Jim Granville: Re: How to replace Triscend - Xilinx plans for the future
69703: 04/05/18: rickman: Re: How to replace Triscend - Xilinx plans for the future
69767: 04/05/19: Ulf Samuelsson: Re: How to replace Triscend - Xilinx plans for the future
69656: 04/05/17: Daniel Gowans: Clock Generation from Asynchronous Data Stream
69662: 04/05/17: John_H: Re: Clock Generation from Asynchronous Data Stream
70019: 04/05/27: Daniel Gowans: Re: Clock Generation from Asynchronous Data Stream
69658: 04/05/17: Jakub: Xilinx training
69895: 04/05/23: Mike Treseler: Re: Xilinx training
69972: 04/05/25: Hendra Gunawan: Re: Xilinx training
69990: 04/05/26: Martin Thompson: Re: Xilinx training
69664: 04/05/17: viswanath: question about filter design vhdl
69676: 04/05/17: MM: Re: question about filter design vhdl
69668: 04/05/17: Tony Dean: IBUFG incapable of driving both CLKDLL and BUFG simultaneously?
69673: 04/05/18: Bob: Re: IBUFG incapable of driving both CLKDLL and BUFG simultaneously?
69700: 04/05/18: Tony Dean: Re: IBUFG incapable of driving both CLKDLL and BUFG simultaneously?
69727: 04/05/18: Ray Andraka: Re: IBUFG incapable of driving both CLKDLL and BUFG simultaneously?
69710: 04/05/18: Gabor Szakacs: Re: IBUFG incapable of driving both CLKDLL and BUFG simultaneously?
69723: 04/05/19: Marc Guardiani: Re: IBUFG incapable of driving both CLKDLL and BUFG simultaneously?
69736: 04/05/19: GSM User: Re: IBUFG incapable of driving both CLKDLL and BUFG simultaneously?
69759: 04/05/19: Tony Dean: Re: IBUFG incapable of driving both CLKDLL and BUFG simultaneously?
69671: 04/05/18: Jim Granville: Atmel Zigbee solutions
69690: 04/05/18: Jon Beniston: Re: Atmel Zigbee solutions
69697: 04/05/18: John_H: Re: Atmel Zigbee solutions
69705: 04/05/18: rickman: Re: Atmel Zigbee solutions
69718: 04/05/18: Jon Beniston: Re: Atmel Zigbee solutions
69766: 04/05/19: Ulf Samuelsson: Re: Atmel Zigbee solutions
69785: 04/05/19: Jon Beniston: Re: Atmel Zigbee solutions
69855: 04/05/22: Ulf Samuelsson: Re: Atmel Zigbee solutions
69680: 04/05/18: Rajesh Murugesan: DLL - Change in input frequency (CLKIN)
69712: 04/05/18: Tony Dean: Re: DLL - Change in input frequency (CLKIN)
69922: 04/05/24: Rajesh Murugesan: Re: DLL - Change in input frequency (CLKIN) ---help needed
70061: 04/06/01: Rajesh Murugesan: DLL- Change in input clock source --Suggestions plz
69713: 04/05/18: Symon: Re: DLL - Change in input frequency (CLKIN)
70064: 04/06/01: lee news: Re: DLL - Change in input frequency (CLKIN)
69682: 04/05/18: Student: How do I perform RTL simulation with a Core Generator RAM and multiplier?
69683: 04/05/18: Student: Re: How do I perform RTL simulation with a Core Generator RAM and multiplier?
69684: 04/05/18: <khiltrop@gesytec.de>: Xilinx WebPack 6 -> Error: 90:Portability <-- anyone can give me a hint?
69698: 04/05/18: Symon: Re: Xilinx WebPack 6 -> Error: 90:Portability <-- anyone can give me a hint?
69753: 04/05/19: <khiltrop@gesytec.de>: Antwort: Re: Xilinx WebPack 6 -> Error: 90:Portability <-- anyone can give
69757: 04/05/19: Symon: Re: Antwort: Re: Xilinx WebPack 6 -> Error: 90:Portability <-- anyone can give me a hint?
69686: 04/05/18: ALuPin: Quality of timing simulation
69689: 04/05/18: it: Micro : Bus
69691: 04/05/18: prav: Drive strength on I/O pads
69707: 04/05/18: Jamie Sanderson: Re: Drive strength on I/O pads
69794: 04/05/19: prav: Re: Drive strength on I/O pads
69692: 04/05/18: Aniket Naik: Malfunctioning dual port block ram.
69709: 04/05/18: Jon Beniston: Re: Malfunctioning dual port block ram.
69742: 04/05/19: Martin Thompson: Re: Malfunctioning dual port block ram.
69769: 04/05/19: Jon Beniston: Re: Malfunctioning dual port block ram.
69799: 04/05/20: Martin Thompson: Re: Malfunctioning dual port block ram.
69801: 04/05/20: General Schvantzkoph: Re: Malfunctioning dual port block ram.
70066: 04/06/01: spr: Re: Malfunctioning dual port block ram.
69694: 04/05/18: Patrik Eriksson: 64B/66B at sub 10Gbps in Xilinx MGT
69696: 04/05/18: Eng Gan: clock buffer in Leonardo Spectrum
69699: 04/05/18: Sander Odekerken: Meaning of output value?
69704: 04/05/18: Symon: Re: Meaning of output value?
69706: 04/05/18: John_H: Re: Meaning of output value?
69708: 04/05/18: Paul Marciano: How to select an FPGA size (beginner)
69711: 04/05/18: Ricardo: Re: How to select an FPGA size (beginner)
69714: 04/05/18: E.S.: Re: How to select an FPGA size (beginner)
69784: 04/05/19: Paul Marciano: Re: How to select an FPGA size (beginner)
69787: 04/05/19: Ray Andraka: Re: How to select an FPGA size (beginner)
69715: 04/05/18: Ray Andraka: Re: How to select an FPGA size (beginner)
69728: 04/05/19: Chuck McManis: Re: How to select an FPGA size (beginner)
69729: 04/05/19: glen herrmannsfeldt: Re: How to select an FPGA size (beginner)
69743: 04/05/19: Ray Andraka: Re: How to select an FPGA size (beginner)
69789: 04/05/20: Chuck McManis: Re: How to select an FPGA size (beginner)
69790: 04/05/20: Ray Andraka: Re: How to select an FPGA size (beginner)
69805: 04/05/20: Symon: Re: How to select an FPGA size (beginner)
69916: 04/05/24: thangkho: Re: How to select an FPGA size (beginner)
69716: 04/05/18: glen herrmannsfeldt: Webpack 6.1, ISEexamples, and CoreGen
69717: 04/05/18: John_H: Re: Webpack 6.1, ISEexamples, and CoreGen
69720: 04/05/18: glen herrmannsfeldt: Re: Webpack 6.1, ISEexamples, and CoreGen
69726: 04/05/18: Ray Andraka: Re: Webpack 6.1, ISEexamples, and CoreGen
69730: 04/05/19: glen herrmannsfeldt: Re: Webpack 6.1, ISEexamples, and CoreGen
69744: 04/05/19: Ray Andraka: Re: Webpack 6.1, ISEexamples, and CoreGen
69758: 04/05/19: Gabor Szakacs: Re: Webpack 6.1, ISEexamples, and CoreGen
69721: 04/05/18: vadim: NIOS Board Stratix Edition - FPGA won't configure
69724: 04/05/19: Subroto Datta: Re: NIOS Board Stratix Edition - FPGA won't configure
69761: 04/05/19: Jesse Kempa: Re: NIOS Board Stratix Edition - FPGA won't configure
69777: 04/05/19: Petter Gustad: Re: NIOS Board Stratix Edition - FPGA won't configure
69792: 04/05/20: Subroto Datta: Re: NIOS Board Stratix Edition - FPGA won't configure
69896: 04/05/23: vadim: Re: NIOS Board Stratix Edition - FPGA won't configure
69914: 04/05/24: Jesse Kempa: Re: NIOS Board Stratix Edition - FPGA won't configure
69722: 04/05/18: MS: opb_gpio with interrupt- v2pro
69725: 04/05/18: Kenneth Land: Nios II Going Live...
69734: 04/05/19: Goran Bilski: Re: Nios II Going Live...
69735: 04/05/19: Jim Granville: Re: Nios II Going Live...
69739: 04/05/19: Jeroen: Re: Nios II Going Live...
69748: 04/05/19: Kenneth Land: Re: Nios II Going Live...
69749: 04/05/19: Jon Beniston: Re: Nios II Going Live...
69751: 04/05/19: Nicholas C. Weaver: Re: Nios II Going Live...
69754: 04/05/19: Austin Lesea: Re: Nios II Going Live...
69756: 04/05/19: Nicholas C. Weaver: Re: Nios II Going Live...
69762: 04/05/19: Tim: Re: Nios II Going Live...
69782: 04/05/19: Austin Lesea: S3 cheap shot
69802: 04/05/20: E.S.: Re: S3 cheap shot
69804: 04/05/20: Austin Lesea: Never right, always room for improvement
69812: 04/05/20: Jesse Kempa: Re: Never right, always room for improvement
69817: 04/05/20: Austin Lesea: Re: Never right, always room for improvement
69841: 04/05/21: Jesse Kempa: Re: Never right, always room for improvement
69917: 04/05/24: Tim: Re: Never right, always room for improvement
69919: 04/05/24: Thomas Womack: Re: Never right, always room for improvement
69857: 04/05/22: Peter Sommerfeld: Re: Never right, always room for improvement
69904: 04/05/24: Austin Lesea: Re: Never right, always room for improvement
69815: 04/05/21: Tim: Re: Never right, always room for improvement
69824: 04/05/21: Jonathan Bromley: Re: Never right, always room for improvement
69834: 04/05/21: Nicholas C. Weaver: Re: Never right, always room for improvement
69849: 04/05/21: john jakson: Re: Never right, always room for improvement
69950: 04/05/25: Nial Stewart: Re: Never right, always room for improvement
69992: 04/05/26: john jakson: Re: Never right, always room for improvement
69848: 04/05/21: john jakson: Re: Never right, always room for improvement
69850: 04/05/22: Jim Granville: Re: Never right, always room for improvement
69861: 04/05/22: E.S.: Transputer on FPGA, was: Re: Never right, always room for improvement
69866: 04/05/22: rickman: Re: Transputer on FPGA
69868: 04/05/22: John Doty: Re: Transputer on FPGA
69873: 04/05/22: john jakson: Re: Transputer on FPGA
69875: 04/05/22: john jakson: Re: Transputer on FPGA
69876: 04/05/22: John Doty: Re: Transputer on FPGA
69880: 04/05/23: <andrew29@littlepinkcloud.invalid>: Re: Transputer on FPGA
69882: 04/05/23: john jakson: Re: Transputer on FPGA
69881: 04/05/23: Albert van der Horst: Re: Transputer on FPGA
69915: 04/05/24: john jakson: Re: Transputer on FPGA
69869: 04/05/22: john jakson: Re: Transputer on FPGA, was: Re: Never right, always room for improvement
69819: 04/05/20: rickman: Re: Never right, always room for improvement
69835: 04/05/21: Austin Lesea: Re: Never right, always room for improvement
69851: 04/05/22: Jan Gray: Re: Never right, always room for improvement
69779: 04/05/20: Jim Granville: Re: Nios II Going Live...
69760: 04/05/19: Jesse Kempa: Re: Nios II Going Live...
69768: 04/05/19: Peter Sommerfeld: Re: Nios II Going Live...
69770: 04/05/19: Goran Bilski: Re: Nios II Going Live...
69772: 04/05/19: Kenneth Land: Re: Nios II Going Live...
69775: 04/05/19: Eric Crabill: Re: Nios II Going Live...
69778: 04/05/19: Nicholas C. Weaver: Re: Nios II Going Live...
69780: 04/05/20: Jim Granville: Re: Nios II Going Live...
69788: 04/05/19: Ray Andraka: Re: Nios II Going Live...
69781: 04/05/20: Jim Granville: Re: Nios II Going Live...
69810: 04/05/20: Joel A. Seely: Re: Nios II Going Live...
69811: 04/05/21: Jim Granville: Re: Nios II Going Live...
69816: 04/05/20: Kenneth Land: Re: Nios II Going Live...
69832: 04/05/21: Kolja Sulimma: Re: Nios II Going Live...
69820: 04/05/21: Richard Pennington: Re: Nios II Going Live...
69843: 04/05/21: Geoffrey Brown: Re: Nios II Going Live...
69845: 04/05/21: Eric Smith: Re: Nios II Going Live...
69731: 04/05/19: ALuPin: Inversion of signals on synthesis
69733: 04/05/19: glen herrmannsfeldt: Re: Inversion of signals on synthesis
69741: 04/05/19: Jeroen: Re: Inversion of signals on synthesis
69732: 04/05/19: =?ISO-8859-1?Q?Daniel_K=F6the?=: Initialize Blockram from file
69750: 04/05/19: Jon Beniston: Re: Initialize Blockram from file
69771: 04/05/19: Gabor Szakacs: Re: Initialize Blockram from file
69773: 04/05/19: Shalin Sheth: Re: Initialize Blockram from file
69737: 04/05/19: Sean Durkin: Xilinx V2P: DCM and changing input clock
69752: 04/05/19: Austin Lesea: Re: Xilinx V2P: DCM and changing input clock
69755: 04/05/19: Sean Durkin: Re: Xilinx V2P: DCM and changing input clock
69791: 04/05/20: Allan Herriman: Re: Xilinx V2P: DCM and changing input clock
69809: 04/05/20: Austin Lesea: Re: Xilinx V2P: DCM and changing input clock
69878: 04/05/23: Allan Herriman: Re: Xilinx V2P: DCM and changing input clock
69905: 04/05/24: Austin Lesea: Re: Xilinx V2P: DCM and changing input clock
69907: 04/05/25: Allan Herriman: Re: Xilinx V2P: DCM and changing input clock
69910: 04/05/24: Austin Lesea: Re: Xilinx V2P: DCM and changing input clock
69738: 04/05/19: krebs: C-code to control FPGA with Leon
69746: 04/05/19: Jonathan Bromley: Re: C-code to control FPGA with Leon
69827: 04/05/21: krebs: Re: C-code to control FPGA with Leon
69745: 04/05/19: Matija: I2C Slave
69747: 04/05/19: rickman: Re: I2C Slave
69856: 04/05/22: S Ramirez: Re: I2C Slave
69858: 04/05/22: Matija: Re: I2C Slave
69888: 04/05/23: Andy Peters: Re: I2C Slave
69765: 04/05/19: Symon: Chipscope with clock enable.
69786: 04/05/19: Dave: Xilinx EDK (PPC): Problems Porting to Memec 2VP4LC Board
69795: 04/05/20: Sean Durkin: Re: Xilinx EDK (PPC): Problems Porting to Memec 2VP4LC Board
69793: 04/05/19: kumar: Debugging - Post-synthesis simulation
69796: 04/05/20: javid: Timing Questions?
69797: 04/05/20: Hal Murray: Re: Timing Questions?
69800: 04/05/20: Michael Dales: Trying to build simple demo using XPS and XC2VP20
70037: 04/05/28: Antti Lukats: Re: Trying to build simple demo using XPS and XC2VP20
69807: 04/05/20: Derek Simmons: Altera LP4 Need Help With Device Drivers and Setting Up
69991: 04/05/26: Derek Simmons: Re: Altera LP4 Need Help With Device Drivers and Setting Up
69995: 04/05/26: Subroto Datta: Re: Altera LP4 Need Help With Device Drivers and Setting Up
70002: 04/05/26: Derek Simmons: Re: Altera LP4 Need Help With Device Drivers and Setting Up
69808: 04/05/20: Seung: shift register by block RAM
69813: 04/05/20: Peter Alfke: Re: shift register by block RAM
69822: 04/05/20: ftls1@uaf.edu: FREQUENCY DOUBOULER BY MAX PLUS......
69897: 04/05/23: ftls1@uaf.edu: Re: FREQUENCY DOUBOULER BY MAX PLUS......
69823: 04/05/20: Aniket: Xilinx hypertransport lite reference design.
69825: 04/05/21: Sean Durkin: XIlinx V2P7: DCM won't lock
69831: 04/05/21: John Adair: Re: XIlinx V2P7: DCM won't lock
69836: 04/05/21: Austin Lesea: Re: XIlinx V2P7: DCM won't lock
69863: 04/05/22: Sean Durkin: Re: XIlinx V2P7: DCM won't lock
69900: 04/05/24: John Adair: Re: XIlinx V2P7: DCM won't lock
69908: 04/05/24: Sean Durkin: Re: XIlinx V2P7: DCM won't lock
69911: 04/05/24: Austin Lesea: Re: XIlinx V2P7: DCM won't lock
69838: 04/05/21: Phil Hays: Re: XIlinx V2P7: DCM won't lock
69862: 04/05/22: Sean Durkin: Re: XIlinx V2P7: DCM won't lock
69826: 04/05/21: Guenter Dannoritzer: How to handle different proccessing speeds?
69829: 04/05/21: john: Re: How to handle different proccessing speeds?
69852: 04/05/22: Guenter Dannoritzer: Re: How to handle different proccessing speeds?
69828: 04/05/21: john: DS-BD-V2M1000 datasheets?
69846: 04/05/21: Philip Freidin: Re: DS-BD-V2M1000 datasheets?
69847: 04/05/22: john: Re: DS-BD-V2M1000 datasheets?
69830: 04/05/21: Fred Ma: Seeking Chameleon Systems white paper
69837: 04/05/21: quantum: Old XCV50 FPGA and Ethernet
69839: 04/05/21: Dave Vanden Bout: Re: Old XCV50 FPGA and Ethernet
69842: 04/05/21: jimboluke: USB HUB?
69933: 04/05/25: Jeroen: Re: USB HUB?
69853: 04/05/22: Basuki Endah Priyanto: FPGA Board with Flash Memory
69854: 04/05/22: Martin Maurer: Re: FPGA Board with Flash Memory
69859: 04/05/22: Dave Vanden Bout: Re: FPGA Board with Flash Memory
69901: 04/05/24: John Adair: Re: FPGA Board with Flash Memory
69860: 04/05/22: Zspider: OT: Electronics learner kit?
69872: 04/05/22: Ray Andraka: Re: OT: Electronics learner kit?
69884: 04/05/23: electron man: Re: OT: Electronics learner kit?
69894: 04/05/23: Zspider: Re: OT: Electronics learner kit?
69864: 04/05/22: Chuck McManis: More fun with VHDL
69865: 04/05/22: Mike Treseler: Re: More fun with VHDL
69877: 04/05/22: George: Re: More fun with VHDL
69892: 04/05/23: Chuck McManis: Re: More fun with VHDL
69883: 04/05/23: Peter Wallace: Re: More fun with VHDL
69867: 04/05/22: sunil: Reg learning FPGA backend
69870: 04/05/23: Jim Wu: Re: Reg learning FPGA backend
69874: 04/05/22: john jakson: Re: Reg learning FPGA backend
69871: 04/05/23: Chuck McManis: Altium FPGA board
69879: 04/05/23: Leon Heller: Re: Altium FPGA board
69887: 04/05/23: Rene Tschaggelar: Re: Altium FPGA board
69893: 04/05/23: Chuck McManis: Re: Altium FPGA board
69935: 04/05/25: Rene Tschaggelar: Re: Altium FPGA board
69975: 04/05/26: Chuck McManis: Re: Altium FPGA board
70003: 04/05/26: Rene Tschaggelar: Re: Altium FPGA board
70031: 04/05/28: Chuck McManis: Re: Altium FPGA board
70010: 04/05/26: Eric Smith: Re: Altium FPGA board
69885: 04/05/23: electron man: is RAMbus going to resurect itself as another DDR2 format?
69886: 04/05/23: sameer: strange behaviour of the design
69889: 04/05/23: Marc Guardiani: Re: strange behaviour of the design
69890: 04/05/24: Jim Granville: Re: strange behaviour of the design
69891: 04/05/23: Andy Peters: Re: strange behaviour of the design
69898: 04/05/24: haim: spartan 2 demo example
69899: 04/05/24: GreateWhite.DK: HOWTO calculate the binary size of a .hexout/.flash/.germs file
69932: 04/05/25: Jeroen: Re: HOWTO calculate the binary size of a .hexout/.flash/.germs file
69941: 04/05/25: GreateWhite.DK: Re: HOWTO calculate the binary size of a .hexout/.flash/.germs file
69902: 04/05/24: Jimmy: VHDL simple question: is 2-D array synthesizable
69903: 04/05/24: Nicolas Matringe: Re: VHDL simple question: is 2-D array synthesizable
69906: 04/05/24: Jimmy: Re: VHDL simple question: is 2-D array synthesizable
69964: 04/05/25: Hendra Gunawan: Re: VHDL simple question: is 2-D array synthesizable
69968: 04/05/25: Austin Lesea: Re: VHDL simple question: is 2-D array synthesizable
69969: 04/05/25: Hendra Gunawan: Re: VHDL simple question: is 2-D array synthesizable
69989: 04/05/26: Martin Thompson: Re: VHDL simple question: is 2-D array synthesizable
69909: 04/05/24: Ste: How to convert a pattern to SVF
69918: 04/05/24: wei ming: I have problem with readback for virtex2
69921: 04/05/24: kumar: NGDBUILD warnings...please help
69923: 04/05/24: Stifler: Nios II = Microblaze
69925: 04/05/24: Ken Land: Re: Nios II = Microblaze
69934: 04/05/25: Uncle Noah: Re: Nios II = Microblaze
69937: 04/05/25: Goran Bilski: Re: Nios II = Microblaze
69945: 04/05/25: Jon Beniston: Re: Nios II = Microblaze
69954: 04/05/25: E.S.: Re: Nios II = Microblaze
69958: 04/05/25: Ken Land: Re: Nios II = Microblaze
69960: 04/05/25: E.S.: Re: Nios II = Microblaze
69970: 04/05/25: Kenneth Land: Re: Nios II = Microblaze
69997: 04/05/26: E.S.: Re: Nios II = Microblaze
70005: 04/05/26: Kenneth Land: Re: Nios II = Microblaze
69967: 04/05/25: Jon Beniston: Re: Nios II = Microblaze
69981: 04/05/26: David Brown: Re: Nios II = Microblaze
69930: 04/05/25: Jon Beniston: Re: Nios II = Microblaze
69931: 04/05/25: Goran Bilski: Re: Nios II = Microblaze
69944: 04/05/25: Jon Beniston: Re: Nios II = Microblaze
69946: 04/05/25: Goran Bilski: Re: Nios II = Microblaze
69965: 04/05/25: Jon Beniston: Re: Nios II = Microblaze
69971: 04/05/25: Kenneth Land: Re: Nios II = Microblaze
69978: 04/05/25: Stifler: Re: Nios II = Microblaze
69982: 04/05/26: David Brown: Re: Nios II = Microblaze
70004: 04/05/26: Goran Bilski: Re: Nios II = Microblaze
69996: 04/05/26: Nicholas C. Weaver: Re: Nios II = Microblaze
69993: 04/05/26: rickman: Re: Nios II = Microblaze
70011: 04/05/26: Kenneth Land: Re: Nios II = Microblaze
69998: 04/05/26: E.S.: Economics of CPU softcores, was : Re: Nios II = Microblaze
70012: 04/05/26: Kenneth Land: Re: Economics of CPU softcores, was : Re: Nios II = Microblaze
69924: 04/05/24: A_Smith: HSTL and Virtex 2
69926: 04/05/24: Tom Derham: Driving fpga pin out over long cable
69927: 04/05/25: Jim Granville: Re: Driving fpga pin out over long cable
69936: 04/05/25: Rene Tschaggelar: Re: Driving fpga pin out over long cable
69942: 04/05/25: Rajeev: Re: Driving fpga pin out over long cable
69949: 04/05/25: John_H: Re: Driving fpga pin out over long cable
69955: 04/05/25: Peter Alfke: Re: Driving fpga pin out over long cable
70022: 04/05/27: <sanpab@eis.uva.es>: Re: Driving fpga pin out over long cable
70024: 04/05/27: Rene Tschaggelar: Re: Driving fpga pin out over long cable
70025: 04/05/28: Jim Granville: Re: Driving fpga pin out over long cable
70023: 04/05/27: Gabor Szakacs: Re: Driving fpga pin out over long cable
70027: 04/05/27: Peter Alfke: Re: Driving fpga pin out over long cable
70028: 04/05/28: Jim Granville: Re: Driving fpga pin out over long cable
70038: 04/05/28: Tom Derham: Re: Driving fpga pin out over long cable
69928: 04/05/25: Student: What can I do if my chip can't meet timing?
69940: 04/05/25: ALuPin: Re: What can I do if my chip can't meet timing?
69974: 04/05/26: Student: Re: What can I do if my chip can't meet timing?
70001: 04/05/26: Peter Alfke: Re: What can I do if my chip can't meet timing?
70006: 04/05/27: Jim Granville: Re: What can I do if my chip can't meet timing?
70008: 04/05/27: Kelvin: Re: What can I do if my chip can't meet timing?
70026: 04/05/27: Jon Elson: Re: What can I do if my chip can't meet timing?
70029: 04/05/28: Kelvin: Re: What can I do if my chip can't meet timing?
70009: 04/05/26: Hal Murray: Re: What can I do if my chip can't meet timing?
70007: 04/05/26: Matthew E Rosenthal: Re: What can I do if my chip can't meet timing?
69947: 04/05/25: Jon Beniston: Re: What can I do if my chip can't meet timing?
69948: 04/05/25: Shalin Sheth: Re: What can I do if my chip can't meet timing?
69953: 04/05/25: Peter Alfke: Re: What can I do if my chip can't meet timing?
69973: 04/05/26: Student: Re: What can I do if my chip can't meet timing?
69952: 04/05/25: Symon: Re: What can I do if my chip can't meet timing?
69977: 04/05/26: RobertP: Re: What can I do if my chip can't meet timing?
69987: 04/05/26: General Schvantzkoph: Re: What can I do if my chip can't meet timing?
70014: 04/05/27: Petter Gustad: Re: What can I do if my chip can't meet timing?
69929: 04/05/25: Jack: VPR & Reconfigurable system ?
69938: 04/05/25: qudhs: Virtex2P co-simulation problems using Modelsim and smartmodel
69939: 04/05/25: Ivan: AWGN
69943: 04/05/25: mikegw: www.opencores.org ???
69963: 04/05/25: James: Re: www.opencores.org ???
69988: 04/05/26: Gabor Szakacs: Re: www.opencores.org ???
70036: 04/05/28: Rudolf Usselmann: Re: www.opencores.org ???
69951: 04/05/25: Oscar Garnica: Read/Write data from/to SRAM
69980: 04/05/25: ALuPin: Re: Read/Write data from/to SRAM
69999: 04/05/26: Tommy Thorn: Re: Read/Write data from/to SRAM
69956: 04/05/25: Joerg Ritter: ise 6.2 + linuxdrivers.tar.gz + kernel 2.6
70737: 04/06/25: Alexander Wirtz: Re: ise 6.2 + linuxdrivers.tar.gz + kernel 2.6
69957: 04/05/25: Matt Cohen: CPLD Board design newbie questions
69961: 04/05/25: Leon Heller: Re: CPLD Board design newbie questions
69959: 04/05/25: Paul Marciano: How to generate a 320x200 VGA signal?
70035: 04/05/28: Rudolf Usselmann: Re: How to generate a 320x200 VGA signal?
70042: 04/05/28: Jean Nicolle: Re: How to generate a 320x200 VGA signal?
70101: 04/06/02: Ed Anuff: Re: How to generate a 320x200 VGA signal?
69962: 04/05/25: wei ming: Readback on Vritex2, help me.
69966: 04/05/25: KrishK: Creating Orcad symbol for FPGA with large pin counts
69976: 04/05/26: Bob: Re: Creating Orcad symbol for FPGA with large pin counts
69979: 04/05/25: RANGA REDDY: SDRAM
70000: 04/05/26: Steven: Re: SDRAM
70292: 04/06/11: RANGA REDDY: Re: SDRAM
70294: 04/06/11: Tommy Thorn: Re: SDRAM
70297: 04/06/11: rickman: Re: SDRAM
70321: 04/06/11: Hal Murray: Re: SDRAM
70332: 04/06/12: john jakson: Re: SDRAM
70333: 04/06/12: Hal Murray: Re: SDRAM
70349: 04/06/14: Martin Thompson: Re: SDRAM
70355: 04/06/14: Ray Andraka: Re: SDRAM
70356: 04/06/14: krw: Re: SDRAM
69983: 04/05/26: Ruediger Scheidig: Xilinx mb-gcc, linker scripts and splitting Object-file sections
69984: 04/05/26: RANGA REDDY: SDRAM controller
69985: 04/05/26: Arie Zychlinski: Re: SDRAM controller
69994: 04/05/26: Tim: Re: SDRAM controller
69986: 04/05/26: Arie Zychlinski: SystemC book
70013: 04/05/27: Inquiring Guy: Good Devlopement Board for learning
70016: 04/05/27: Jan Panteltje: Re: Good Devlopement Board for learning
70015: 04/05/27: Matthias =?iso-8859-1?Q?M=FCller?=: ise 6.2 lvdci_33
70017: 04/05/27: LC Geldenhuys: Propogation delays and setup times
70018: 04/05/27: Mario Trams: Re: Propogation delays and setup times
70048: 04/05/29: Hendra Gunawan: Re: Propogation delays and setup times
70049: 04/05/30: Philip Freidin: Re: Propogation delays and setup times
70051: 04/05/31: LC Geldenhuys: Re: Propogation delays and setup times
70020: 04/05/27: Kevin Kelley: Job Opening - Product Planning Manager
70021: 04/05/27: Kevin Kelley: Sr. Design Engineering Opportunities
70030: 04/05/27: Thomas Stanka: Tool to help detecting race conditions with asych inputs?
70034: 04/05/28: Hal Murray: Re: Tool to help detecting race conditions with asych inputs?
70044: 04/05/28: Mike Treseler: Re: Tool to help detecting race conditions with asych inputs?
70083: 04/06/01: Thomas Stanka: Re: Tool to help detecting race conditions with asych inputs?
70045: 04/05/28: Hal Murray: Re: Tool to help detecting race conditions with asych inputs?
70047: 04/05/29: Mike Treseler: Re: Tool to help detecting race conditions with asych inputs?
70050: 04/05/31: Allan Herriman: Re: Tool to help detecting race conditions with asych inputs?
70084: 04/06/02: Hal Murray: Re: Tool to help detecting race conditions with asych inputs?
70085: 04/06/02: Allan Herriman: Re: Tool to help detecting race conditions with asych inputs?
70088: 04/06/02: Thomas Stanka: Re: Tool to help detecting race conditions with asych inputs?
70094: 04/06/02: Mike Treseler: Re: Tool to help detecting race conditions with asych inputs?
70032: 04/05/28: rat: how can I merge 66mhz pci clock to 33mhz clock?
70033: 04/05/28: Kelvin: Yawn...Cannot copy Acrobat Reader -write_timing_constraints YES directly into .xst file...
70039: 04/05/28: Timo Dammes: Xilinx System Generator
70291: 04/06/11: Jianyong Niu: Re: Xilinx System Generator
70040: 04/05/28: sarah: how to random generate packet for Ethernet MAC(802.3) with verilog in testbench ?
70046: 04/05/29: Mike Treseler: Re: how to random generate packet for Ethernet MAC(802.3) with verilog in testbench ?
70095: 04/06/02: <sanpab@eis.uva.es>: Re: how to random generate packet for Ethernet MAC(802.3) with verilog in testbench ?
70146: 04/06/04: MS: Re: how to random generate packet for Ethernet MAC(802.3) with verilog in testbench ?
70041: 04/05/28: Pratip Mukherjee: VHDL test bench in Quartus
70043: 04/05/28: Mike Treseler: Re: VHDL test bench in Quartus
70115: 04/06/03: salman sheikh: Re: VHDL test bench in Quartus
70122: 04/06/03: rickman: Re: VHDL test bench in Quartus
70143: 04/06/04: Rajeev: Re: VHDL test bench in Quartus
70144: 04/06/04: rickman: Re: VHDL test bench in Quartus
70149: 04/06/05: Pratip Mukherjee: Re: VHDL test bench in Quartus
70150: 04/06/05: rickman: Re: VHDL test bench in Quartus
70052: 04/05/31: Jimmy: VHDL warning " Feedback mux " from synplify pro ...thx
70054: 04/05/31: Allan Herriman: Re: VHDL warning " Feedback mux " from synplify pro ...thx
70055: 04/05/31: Allan Herriman: Re: VHDL warning " Feedback mux " from synplify pro ...thx
70072: 04/06/01: Ray Andraka: Re: VHDL warning " Feedback mux " from synplify pro ...thx
70053: 04/05/31: Pankaj Sharma: EDK 6.1
70056: 04/05/31: vadim: Serial I/O Standards
70057: 04/06/01: Allan Herriman: Re: Serial I/O Standards
70070: 04/06/01: Hal Murray: Re: Serial I/O Standards
70058: 04/05/31: Adam Megacz: solderless breadboard + fpga + smt-adaptable socket?
70060: 04/06/01: Jean Nicolle: Re: solderless breadboard + fpga + smt-adaptable socket?
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