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"Jim Granville" <no.spam@designtools.co.nz> skrev i meddelandet news:gcqvc.509$NA1.37943@news02.tsnz.net... > Srikanth Anumalla wrote: > > I am a novoice in FPGAs. My application needs an a/d converter on a FPGA. Is > > it possible to design an a/d converter on FPGA. I am using Altera Nios FPGA. > > Any info is appreciated. > > It all depends on the resolution/speed you need. > Tracking ADCs, which use a DAC and comparitor, are simple. > The DAC can be single pin PWM, or Rate Multiplier - for better > performance, external Vcc/Vref, and buffer all help. > Gnd and Vcc lines on FPGAs are NOT low noise analog nodes ! > > Sigma-Delta ADCs are also simple, but need an integrator/Vref/Slice > for best performance. > > If it is a closed-loop system, where you are more interested in > a balance-point than absolute precision/linearity, then the very > simple single slope RC ramp can be used. > -jg Any ADC on an FPGA is going to require something externally, so why not use a cheap external ADC or a small 8 pin micro with an ADC? -- Best Regards, Ulf Samuelsson ulf@a-t-m-e-l.com This is a personal view which may or may not be share by my Employer Atmel Nordic ABArticle: 70101
pm940@yahoo.com (Paul Marciano) wrote in message news:<d5bc3deb.0405251248.38717f73@posting.google.com>... > Hi. I'd like to build an 80s-style display controller, but I want to > output the image to a VGA monitor. Here are a couple of interesting options: http://elm-chan.org/works/crtc/report.html http://www.ohnaka.jp/wiki/wiki.cgi?page=%BB%F7%C8%F3VDP The second link is to a page in Japanese, so you'll need to hunt around for the links on it to the actual source files. The cool thing about it is that it appears to be a recreation of the TI TMS9918A video display controller that was used in a number of 80's computers and videogames. EdArticle: 70102
Registration Open
and
Program Announced
7th Mil/Aerospace Applications of Programmable
Logic Devices International Conference (MAPLD)
Ronald Reagan Building and International Trade Center
Washington, D.C.
September 8-10, 2004
Hosted by the NASA Office of Logic Design
Registration is now open for the 7th annual MAPLD International
Conference, September 8-10, 2004, Washington, D.C.
http://www.klabs.org/mapld04/reg/registration.html
The MAPLD program features approximately 130 technical presentations
in a variety of sessions, seminars, and workshops, as well as over 30
Industrial and Government Exhibits covering programmable logic devices
and technologies, digital engineering, and related fields for military
and aerospace applications. Devices, technologies, logic design,
flight applications, fault tolerance, usage, reliability, radiation
susceptibility, and encryption applications of programmable devices,
processors, and adaptive computing systems in military and aerospace
systems are among the subjects for the conference. Abstracts are
available on-line, via the conference home page.
The Invited Speaker program will include:
WELCOME AND OPENING REMARKS
Rear Adm. Craig E. Steidle, USN (Ret.)
NASA Associate Administrator for Exploration Systems
-and-
INVITED HISTORY TALK
Captain John W. Young
NASA Johnson Space Center
SEMINARS - Two full-day seminars will be presented:
• VHDL Synthesis for High-Reliability Systems
• Aerospace Mishaps and Lessons Learned
PANEL SESSION:
• "Why Is Space Exploration So Hard? The Roles of Man and Machine"
WORKSHOPS & "BIRDS OF A FEATHER" SPECIAL SESSIONS
• Mitigation Methods for Reprogrammable Logic in
The Space Radiation Environment
• Reconfigurable Computing - New Extended Format!
• PLD Failures, Analyses, and the Impact on Systems - NEW for 2004!!!
• Digital Engineering and Computer Design - A Retrospective and
Lessons Learned for Today's Engineers
* Includes a disassembly and discussion of a Block II
Apollo Guidance Computer by the engineers who designed it.
• "An Application Engineer's View" - Back for 2004!
• "NESC and Software" - a joint session of MAPLD and the NASA
Engineering and Safety Center
TECHNICAL SESSIONS:
• Applications: Military and Aerospace
• Systems and Design Tools
• Radiation and Mitigation Techniques
• Processors: General Purpose and Arithmetic
• Reconfigurable Computing, Evolvable Hardware, and Security
• Poster Session
INDUSTRIAL and GOVERNMENT EXHIBITS RESERVATIONS:
NASA Office of Logic Design Mentor Graphics Corporation
Xilinx Corporation Synthworks
Tensilica Actel Corporation
Annapolis Microsystems Space Micro, Inc.
SEAKR Engineering Aldec
IEEE Aerospace and Electronics Systems Society
Hier Design Global Velocity
Lattice Semiconductor Quicksilver Technology
Celoxica BAE Systems
The Andraka Consulting Group Aeroflex
Synopsys Peregrine Semiconductor
Starbridgesystems Condor Engineering
AccelChip NASA Engineering and Safety Center
Synplicity Defense Microelectronics Activity
Southwest Research Institute Altera
SRC Computers Mathstar
Sigrity
CONFERENCE HOME PAGE - http://klabs.org/mapld04 - contains
an abundance of information on both technical and programmatic
aspects of the conference. This conference is open to US and foreign
participation and is not classified. For related information, please
see the NASA Office of Logic Design Web Site (http://klabs.org).
For more information, please visit http://klabs.org/mapld04
or contact:
Richard Katz - Conference Chair NASA Goddard Space Flight Center
mapld2004@klabs.org Tel: (301) 286-9705
Late abstracts will be accepted for poster and worshop sessions only.
Please send submissions to mapld2004@klabs.org
Article: 70103
Field Programmable Pass Transistor Array.
Is there such a thing? I'm imagining even something that's NMOS-only
with dual rail encoding worked into the fabric.
I guess my point is that CMOS is cool, but it would be nice if people
could experiment with other logic styles without giving up the
coolness of programmable hardware. The most straightforward way I can
think of is to give people a pile of pass transistors connected by
programmable interconnect. I'm sure moving to a coarser granularity is
probably a good idea too.
- a
--
"The first time I read this book I felt what I could only explain as a
great disturbance in the Force: it was as if a billion washing
machinces all became unbalanced at once and were suddenly silenced."
-- anonymous book reviewer on Amazon.com
Article: 70104Adam Megacz wrote: > Field Programmable Pass Transistor Array. > > Is there such a thing? I'm imagining even something that's NMOS-only > with dual rail encoding worked into the fabric. > > I guess my point is that CMOS is cool, but it would be nice if people > could experiment with other logic styles without giving up the > coolness of programmable hardware. The most straightforward way I can > think of is to give people a pile of pass transistors connected by > programmable interconnect. I'm sure moving to a coarser granularity is > probably a good idea too. If you were an IC vendor, how many of these could you expect to sell ? The answer to that will tell you if there is such a thing. So what does exist : There are * Programmable Cross points, from Lattice * Programmable Analog parts, but usually with rather 'ordinary' analog specs, narrow Frequency ranges, and rather high prices. * Analog Switch technology is widely deployed, and comes in tiny packages, so you can always construct your own... * and there is always a sea of CD4007's :) -jgArticle: 70105
Take a look at Xilinx App Note 174 - Figure 11 (Board Level Deskew of Board Level Clock between Multiple FPGAs. The jist is that after your master FPGA generates its output clock at the PWB level, the signal is routed back into the FPGA BUFG input and is used to drive the FB input of the originating DLL/DCM. This is parallel for the Master FPGA as well as slaves. Traces should be matched at the board level. Also, make sure you think about the reset philosophy of the multiple FPGAs on the board. This usually requires a little thought, since resets and clock availability are tightly coupled in synchronous design. Usually, the master FPGA also distributes a "reset" signal to apply to slave DLLs. -- Regards, John Retta Owner and Designer Retta Technical Consulting Inc. Colorado based Xilinx Design consultant email : jretta@rtc-inc.com web : www.rtc-inc.com "chris" <ccoutand@hotmail.com> wrote in message news:33923a80.0406020327.20fde6f3@posting.google.com... > Hi, > > I have several FPGAs in my design and I want the first FPGA to feed > the other FPGAs with its master clock. The first FPGA use a DCM to > reshape an input clock and get its master clock. > I want the three FPGAs to have a phase-aligned clock. > I just don't know how to do it since the master clock of the first > FPGA which is the output clk0 of the DCM has to go through an output > buffer to access a pin to be distributed to the others FPGAs but then > the clock would have a delay compare to clk0. > Is someone can help me with that ? > > Thanks. Christophe.Article: 70106
Hello, Is there anybody, that know where I can find a free source code to generate a three-phase PWM to drive an AC motor with the SpartanII Fpga? Or I have to write myself :-) ? Thank you for your attention -- -- Ciao GiuseppeArticle: 70107
Luc Braeckman <luc.braeckman@pandora.be> wrote in message news:<5dfrb05arvko4ndjhikh2fat7b2c28mdis@4ax.com>... > Hi Chris, > > Basically you need a controllable skew on your clock domain > distributed over the PCB, right? > What is the master clock frequency and where is it derived from? > I might have a solution based on this info. > > Regards, Luc > On 2 Jun 2004 04:27:18 -0700, ccoutand@hotmail.com (chris) wrote: > > >Hi, > > > >I have several FPGAs in my design and I want the first FPGA to feed > >the other FPGAs with its master clock. The first FPGA use a DCM to > >reshape an input clock and get its master clock. > >I want the three FPGAs to have a phase-aligned clock. > >I just don't know how to do it since the master clock of the first > >FPGA which is the output clk0 of the DCM has to go through an output > >buffer to access a pin to be distributed to the others FPGAs but then > >the clock would have a delay compare to clk0. > >Is someone can help me with that ? > > > >Thanks. Christophe. Hi Luc, The master clock frequency is around 100MHz and is coming from an ADC. Christophe.Article: 70108
On Wed, 02 Jun 2004 20:40:28 -0700, Adam Megacz <adam@megacz.com> wrote: > >Field Programmable Pass Transistor Array. > >Is there such a thing? I'm imagining even something that's NMOS-only >with dual rail encoding worked into the fabric. > >I guess my point is that CMOS is cool, but it would be nice if people >could experiment with other logic styles without giving up the >coolness of programmable hardware. The most straightforward way I can >think of is to give people a pile of pass transistors connected by >programmable interconnect. I'm sure moving to a coarser granularity is >probably a good idea too. > > - a Two companies have made such parts in the past and offered them to end users: Icube: made some fairly large cross bar products. Had limitted success. Invented the quichswich products, which were seccond sourced by IDT, and these live on, but are trivial compared to the crossbar products. The remnants of the company were acquired by Fairchild. These parts appear to live on as: http://www.fairchildsemi.com/pf/OC%2FOCX256P.html http://www.fairchildsemi.com/ds/OC/OCX256P.pdf Aptix: This was more of a chip that looked like an FPGA, with all the logic blocks missing. So you got to route stuff similar to the way you might route I/O to I/O on an FPGA. Their target market was the configurable interconnect between a sea of FPGAs on a board, used for ASIC emulation. Innitially these cr*zy people did these chips as anti-fuse. Its lack of success was blamed on there not being a market for these types of parts. That one-time programmability might be an issue was apparently not thought to be a restriction. The company restructured and eventually did a "RAM" based product, but it also changed into a systems company, selling boards with their parts, as well as FPGAs from various vendors. A major part of their system is the SW that partitions large designs across multiple FPGAs, and figures out what goes into the external routing chips. http://www.aptix.com The company still seems to be using this technology, see http://www.aptix.com/products/overview.htm in the second paragraph: "Aptix’s proprietary Field Programmable Interconnect (FPIC™) technology" Currently, things are less that ideal for this company: http://www.governmententerprise.com/story/showArticle.jhtml?articleID=20900355 http://www.reed-electronics.com/electronicnews/article/CA414082?industryid=22111&industry=EDA PhilipArticle: 70109
Giuseppe=B3 wrote: > Hello, > Is there anybody, that know where I can find a free source code to gene= rate > a three-phase PWM to drive an AC motor with the SpartanII Fpga? >=20 > Or I have to write myself :-) ? Well, there is the PWM to modulate the voltages. Then the voltage has to be somewhat proportional to the frequency and=20 finally the current has to be fed back to control the frequency. What all of this do you wish to do in an FPGA ? Rene --=20 Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 70110
Hello! I have finished a Xilinx partial reconfiguration design which runs succesfully on my Virtex II Pro. Yet, there is one line of a reconfigurable module which crosses the module boundary. It is the constant clock enable signal for a reconfiguration module which not me but the tool added. This constant is generated in a LUT within the boundaries of another module, yet only connected to a LUT within the correct module (no further connections). I would be happy to know how to remove this boundary corssing signal. Did anybody encounter similar problems or may help me with some hints? Thanks a lot, FlorianArticle: 70111
Chris, Do you need other frequencies in your FPGAs derived from this clock? Is it single ended or differential? What skew do you need to anticipate? PLease let me know, Luc On 3 Jun 2004 00:56:08 -0700, ccoutand@hotmail.com (chris) wrote: >Luc Braeckman <luc.braeckman@pandora.be> wrote in message news:<5dfrb05arvko4ndjhikh2fat7b2c28mdis@4ax.com>... >> Hi Chris, >> >> Basically you need a controllable skew on your clock domain >> distributed over the PCB, right? >> What is the master clock frequency and where is it derived from? >> I might have a solution based on this info. >> >> Regards, Luc >> On 2 Jun 2004 04:27:18 -0700, ccoutand@hotmail.com (chris) wrote: >> >> >Hi, >> > >> >I have several FPGAs in my design and I want the first FPGA to feed >> >the other FPGAs with its master clock. The first FPGA use a DCM to >> >reshape an input clock and get its master clock. >> >I want the three FPGAs to have a phase-aligned clock. >> >I just don't know how to do it since the master clock of the first >> >FPGA which is the output clk0 of the DCM has to go through an output >> >buffer to access a pin to be distributed to the others FPGAs but then >> >the clock would have a delay compare to clk0. >> >Is someone can help me with that ? >> > >> >Thanks. Christophe. > >Hi Luc, > >The master clock frequency is around 100MHz and is coming from an ADC. > >Christophe.Article: 70112
>> Hello, >> Is there anybody, that know where I can find a free source code to >generate >> a three-phase PWM to drive an AC motor with the SpartanII Fpga? >> >> Or I have to write myself :-) ? >Well, there is the PWM to modulate the voltages. >Then the voltage has to be somewhat proportional to the frequency and >finally the current has to be fed back to control the frequency. > >What all of this do you wish to do in an FPGA ? <CUT> Thank you for your attention, I'm interesting only in the PWM to modulate the voltage. All the other is done with a uP. I know that is only al counter to do a triangular wave and a compare to set the output. But there are also the dead-time and the circuit to cut the impulse with duration < dead_time. And other little thinghs. My first target is something like the Hitachi ITU three-phase PWM generator function. The best would be something like the IC BMA828. Bye GiuseppeArticle: 70113
"Matt Cohen" <matthewlawrencecohen@yahoo.com> wrote in message news:81fdc5f7.0406021212.49a57321@posting.google.com... > I'm working on a design with a Xilinx XC95XL series CPLD. The inputs > would be coming from a system with a 5 V (possibly higher, I don't > have the exact number yet) output. I need 3.3 V outputs, so using the > separate I/O power supply is not a good solution. As a novice > engineer, I have a few ideas, but don't know which is best. Is there > a problem with using a simple resistor divider to create lower > voltages? Should I have to use a separate level shifter IC instead to > change the 5 V signals to 3.3 V? Thanks, > Matt Cohen I think you are in luck. The datasheet for the XC9500XL series specifically states that the inputs are 5V tolerant. In fact I am using one at the moment that is working just like that! JamesArticle: 70114
digari@dacafe.com (digari) wrote in message news:<e0855517.0406012125.492c4ccf@posting.google.com>... > hi, > i m still in planning phase of my design. i was just looking at xilinx > and altera devices. Xilinx provides tri-state buffers as well as > tri-state lines whereas altera doesn't and suggests to use muxs > insteed of tri-state buffers. > Now assume that i have a bus in my design where lots of drivers are > there n driving bus through tri-state buffers. I am just wondering > what will happen if i implement this design in altera. I'll have to > take all drivers at one place, put a mux and re-route them to all > sink. won't it affect timing considerably. > considering it xilinx becomes obvious choice because of tri-state > buffers n lines. Anyone has any other opinion or observation on the > topic?? On-chip tri-state is pretty near dead. As metal has gotten slower relative to transistors, making a long wire with multiple tri-state drivers on it has become very slow, since there's no easy way to re-buffer the signal (the signal could be flowing in one of two directions, since there are multiple drive points). For that reason, all Altera devices have relied on multiplexers to make on-chip buses, rather than on-chip tri-states. This approach is clearly winning out. Recently a company (I forget the name) filed a patent for SoC designs on ASICs where they use multiplexers rather than tri-state buses. So ASICs are following in FPGA footsteps here. Xilinx has also gradually abandoned on-chip tri-states (the 4K had real tri-states, Virtex-2 has a dedicated distributed mux, and Spartan-3 gets rid of that and relies on the regular logic). Altera has always used the regular logic approach. So don't worry about the lack of on-chip tri-states in Altera devices -- muxes are the way to go. Note that once you're using muxes to implement your buses, it also opens up the possibility of using more general switching fabrics (in the limit a crossbar) rather than one centralized bus. Vaughn AlteraArticle: 70115
My guess, is that Quartus only supports synthesizeable VHDL and wait is not synthesizeable. If I not mistake, you have only the waveform program to create testbenches, and so I use Modelsim for my simulations of Altera-targeted designs. Salman Pratip Mukherjee wrote: > Is it possible to write a test bench using VHDL in Quartus? When I tried I > got an error message telling me that wait <n> construct is not supported. > Is that true or am I making some mistake? Is there any way, may be using > tcl, I can simulate a VHDL like test bench? Testbench using waveforms just > does not work for me. > Thanks. > > Pratip Mukherjee > pratipm.remove_this@hotmail.comArticle: 70116
Vaughn, Yes, we do agree. Nice to let folks know that we agree on many things. Austin Vaughn Betz wrote: > digari@dacafe.com (digari) wrote in message news:<e0855517.0406012125.492c4ccf@posting.google.com>... > >>hi, >>i m still in planning phase of my design. i was just looking at xilinx >>and altera devices. Xilinx provides tri-state buffers as well as >>tri-state lines whereas altera doesn't and suggests to use muxs >>insteed of tri-state buffers. >>Now assume that i have a bus in my design where lots of drivers are >>there n driving bus through tri-state buffers. I am just wondering >>what will happen if i implement this design in altera. I'll have to >>take all drivers at one place, put a mux and re-route them to all >>sink. won't it affect timing considerably. >>considering it xilinx becomes obvious choice because of tri-state >>buffers n lines. Anyone has any other opinion or observation on the >>topic?? > > > On-chip tri-state is pretty near dead. As metal has gotten slower > relative to transistors, making a long wire with multiple tri-state > drivers on it has become very slow, since there's no easy way to > re-buffer the signal (the signal could be flowing in one of two > directions, since there are multiple drive points). > > For that reason, all Altera devices have relied on multiplexers to > make on-chip buses, rather than on-chip tri-states. > > This approach is clearly winning out. Recently a company (I forget > the name) filed a patent for SoC designs on ASICs where they use > multiplexers rather than tri-state buses. So ASICs are following in > FPGA footsteps here. Xilinx has also gradually abandoned on-chip > tri-states (the 4K had real tri-states, Virtex-2 has a dedicated > distributed mux, and Spartan-3 gets rid of that and relies on the > regular logic). Altera has always used the regular logic approach. > > So don't worry about the lack of on-chip tri-states in Altera devices > -- muxes are the way to go. Note that once you're using muxes to > implement your buses, it also opens up the possibility of using more > general switching fabrics (in the limit a crossbar) rather than one > centralized bus. > > Vaughn > AlteraArticle: 70117
"I think you are in luck. The datasheet for the XC9500XL series specifically states that the inputs are 5V tolerant. In fact I am using one at the moment that is working just like that!" Yes. Yes it does. Somehow I missed that. I just opened up the data sheet to check, and the very first thing I saw was "5V tolerant I/O pins accept 5V, 3.3V, and 2.5V signals". Thanks a lot everybody. MattArticle: 70118
Is Spartan 3 still faster and less expensive when there are 100+ 16/32-bit registers on a bus? -qlyus Austin Lesea <austin@xilinx.com> wrote in message news:<c9l1q5$m251@cliff.xsj.xilinx.com>... > Yup, > > Tristate is actually slower. > > The tristate buffers in Virtex and all subsequent families are in fact > separate bidirectional logic structures that simulate the behavior of a > tristate bus. > > http://www.xilinx.com/bvdocs/appnotes/xapp466.pdf > > see page 11: Spartan 3 is faster and less expensive without any > tristate elements at all! > > Austin > > rickman wrote: > > digari wrote: > > > >>hi, > >>i m still in planning phase of my design. i was just looking at xilinx > >>and altera devices. Xilinx provides tri-state buffers as well as > >>tri-state lines whereas altera doesn't and suggests to use muxs > >>insteed of tri-state buffers. > >>Now assume that i have a bus in my design where lots of drivers are > >>there n driving bus through tri-state buffers. I am just wondering > >>what will happen if i implement this design in altera. I'll have to > >>take all drivers at one place, put a mux and re-route them to all > >>sink. won't it affect timing considerably. > >>considering it xilinx becomes obvious choice because of tri-state > >>buffers n lines. Anyone has any other opinion or observation on the > >>topic?? > > > > > > The older Xilinx chips have lots of tristate buffers. But they have > > been phasing them out for the last two generations and have completed > > that task with the Spartan 3 chips. The internal tristate buffer is > > dead! > > > > BTW, if you think routing signals to a common mux is slow, you should > > check the timing numbers on the tbufs driving long lines which then run > > around the chip. If you do a really good job of placement, you can > > minimize the speed penalty. But tristate buffers will *always* be slow > > due to the nature of a passive pullup. > > > > Altera has a cascade backbone inside their LABs that will AND the > > outputs of the LUTs at a very high speed. This can implement a very > > wide AND-OR gate for wide muxes at high speed. > >Article: 70119
That's hardly a typical application. Also, I'm not sure if there ever were any FPGAs of any flavour that had longlines with 100+ tristate drivers on them. You should put those registers in a BlockRam mate! Cheers, Syms. "qlyus" <qlyus@yahoo.com> wrote in message news:da71446f.0406031036.137fd0db@posting.google.com... > Is Spartan 3 still faster and less expensive when there are 100+ > 16/32-bit registers on a bus? > > -qlyus > >Article: 70120
With that many registers, you might look at alternative architectures. If sequential access is
normally used, a shift register works well. If random access is needed, the troublesome part is
readback. You might consider readback through a dual port RAM such that the external world has
access to one port and the FPGA internals have access to the other port.
qlyus wrote:
> Is Spartan 3 still faster and less expensive when there are 100+
> 16/32-bit registers on a bus?
>
> -qlyus
>
> Austin Lesea <austin@xilinx.com> wrote in message news:<c9l1q5$m251@cliff.xsj.xilinx.com>...
> > Yup,
> >
> > Tristate is actually slower.
> >
> > The tristate buffers in Virtex and all subsequent families are in fact
> > separate bidirectional logic structures that simulate the behavior of a
> > tristate bus.
> >
> > http://www.xilinx.com/bvdocs/appnotes/xapp466.pdf
> >
> > see page 11: Spartan 3 is faster and less expensive without any
> > tristate elements at all!
> >
> > Austin
> >
> > rickman wrote:
> > > digari wrote:
> > >
> > >>hi,
> > >>i m still in planning phase of my design. i was just looking at xilinx
> > >>and altera devices. Xilinx provides tri-state buffers as well as
> > >>tri-state lines whereas altera doesn't and suggests to use muxs
> > >>insteed of tri-state buffers.
> > >>Now assume that i have a bus in my design where lots of drivers are
> > >>there n driving bus through tri-state buffers. I am just wondering
> > >>what will happen if i implement this design in altera. I'll have to
> > >>take all drivers at one place, put a mux and re-route them to all
> > >>sink. won't it affect timing considerably.
> > >>considering it xilinx becomes obvious choice because of tri-state
> > >>buffers n lines. Anyone has any other opinion or observation on the
> > >>topic??
> > >
> > >
> > > The older Xilinx chips have lots of tristate buffers. But they have
> > > been phasing them out for the last two generations and have completed
> > > that task with the Spartan 3 chips. The internal tristate buffer is
> > > dead!
> > >
> > > BTW, if you think routing signals to a common mux is slow, you should
> > > check the timing numbers on the tbufs driving long lines which then run
> > > around the chip. If you do a really good job of placement, you can
> > > minimize the speed penalty. But tristate buffers will *always* be slow
> > > due to the nature of a passive pullup.
> > >
> > > Altera has a cascade backbone inside their LABs that will AND the
> > > outputs of the LUTs at a very high speed. This can implement a very
> > > wide AND-OR gate for wide muxes at high speed.
> > >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 70121
So I thought, "how hard can it be to download to a V2P7 part using the slave
serial mode?"
Well, pretty hard.
I have a 'master' FPGA that loads a 'slave' FPGA using the slave serial
programming mode. The download process will work over and over, then
suddenly decide not to work. Then it doesn't work for a long
time. Very flakey.
The master FPGA drives PGM_N, CCLK, and DIN to the slave using
2.5V CMOS outputs. The signals all look clean, no over/undershoot,
no glitches in the transition region, etc. The data setup/hold is
over 100ns, the data is setup before the rising edge of CCLK and
is held until after the falling edge. By default, the clock is
held low and pulses high for about 70ns when new data is ready for
the slave.
The master FPGA has very simple logic that interfaces to a PC. The PC can
assert the PGM_N signal and can look at the status of INIT_N and DONE to
monitor programmng status. The PC can also write a 32 bit word into
the master which then serializes the data to the DIN and CCLK pins on
the slave.
Things to note:
1) The download is flakey, but since it can succeed multiple times
in a row, I'm pretty sure that the bit order of data being shifted
into the slave FPGA is correct.
2) I've added logic to grab the output data using the output CCLK clock
so the PC can verify that the data has not been corrupted. It always
reads back correctly.
3) I've turned the 'debug' flag on in bitgen so I can look at the
DOUT pin. When things work, I get lots of pulses out of DOUT,
when download fails, DOUT will either pulse low once or pulse
low multiple times, but stop pulsing before the download completes.
4) Occasionally, INIT_N is asserted by the FPGA before the download is done.
5) The data loads to the slave in bursts of 32 bits, ie, the PC sends
a 32 bit word, the master serializes it, then everything waits while
the PC realises it's done and loads the next word. It's about
150 usec between 'bursts'.
3 & 4 lead me to believe the slave FPGA is receiving corrupted data or
a bad clock occasionally, BUT... the signals look fine.
We have M[2:0] and HSWAP_EN pulled to 2.5V using 10K resistors. PWRDWN_N
is floating as is VBATT. The JTAG signal are also pulled to static levels.
It almost acts like there's a floating pin - if it's in one state everything
is fine, if it drifts or comes up in the 'wrong' state, the download fails.
Has anyone run into problems like this? My local FAE is stumped as am I.
Thanks for any insights!
John Providenza
Article: 70122There is something missing in this discussion. If you are talking about testbenches, then Quartus can't help you since testbenches are used in simulations and Quartus is not a VHDL simulator. I agree that using waveforms to simulate FPGA designs is not desirable. That is why I write my code to run on either Altera or Xilinx devices and use the Xilinx Modelsim simulator to test my design. I then fit the same design to the Altera devices. salman sheikh wrote: > > My guess, is that Quartus only supports synthesizeable VHDL and wait is > not synthesizeable. If I not mistake, you have only the waveform program > to create testbenches, and so I use Modelsim for my simulations of > Altera-targeted designs. > > Salman > > Pratip Mukherjee wrote: > > Is it possible to write a test bench using VHDL in Quartus? When I tried I > > got an error message telling me that wait <n> construct is not supported. > > Is that true or am I making some mistake? Is there any way, may be using > > tcl, I can simulate a VHDL like test bench? Testbench using waveforms just > > does not work for me. > > Thanks. > > > > Pratip Mukherjee > > pratipm.remove_this@hotmail.com -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 70123
I see where Atmel has announced a USB OTG full speed controller chip. It looks interesting. But I would prefer a high speed device. Anyone know of such a chip? Or I can use a core if it is not too large. So far I have not found anything that will implement OTG and high speed. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 70124
I always thought the internal tri-state bus in Xilinx was an advantage over Altera's devices. I started to use this feature in 4k series, in which the save of gates in this low density was more obvious when building a bus with 10+ registers. I have designed many projects with internal tri-state bus. The latest one is the 93-tap FIR filters. Each coefficient is a 16-bit register. With other registers and memory blocks, it is very easy to have the need of 100+ random access. The tartget device is a V-II Pro. The speed is not an issue as the clock for register access can be separate from the data stream clock. With Xilinx abandon of tri-state and Altera not doing it from the beginning, i am confused with who was smarter. If Xilinx gets rid of its unique features (such as SRL and tri-state) more and more, or Altera offers more features which used to be unique in Xilinx (Stratix-II started to offer 100+ multiplier), I have to ask why using Xilinx devices anymore? -qlyus Austin Lesea <austin@xilinx.com> wrote in message news:<c9nl06$jdk1@cliff.xsj.xilinx.com>... > Vaughn, > > Yes, we do agree. Nice to let folks know that we agree on many things. > > Austin > > Vaughn Betz wrote: > > digari@dacafe.com (digari) wrote in message news:<e0855517.0406012125.492c4ccf@posting.google.com>... > > > >>hi, > >>i m still in planning phase of my design. i was just looking at xilinx > >>and altera devices. Xilinx provides tri-state buffers as well as > >>tri-state lines whereas altera doesn't and suggests to use muxs > >>insteed of tri-state buffers. > >>Now assume that i have a bus in my design where lots of drivers are > >>there n driving bus through tri-state buffers. I am just wondering > >>what will happen if i implement this design in altera. I'll have to > >>take all drivers at one place, put a mux and re-route them to all > >>sink. won't it affect timing considerably. > >>considering it xilinx becomes obvious choice because of tri-state > >>buffers n lines. Anyone has any other opinion or observation on the > >>topic?? > > > > > > On-chip tri-state is pretty near dead. As metal has gotten slower > > relative to transistors, making a long wire with multiple tri-state > > drivers on it has become very slow, since there's no easy way to > > re-buffer the signal (the signal could be flowing in one of two > > directions, since there are multiple drive points). > > > > For that reason, all Altera devices have relied on multiplexers to > > make on-chip buses, rather than on-chip tri-states. > > > > This approach is clearly winning out. Recently a company (I forget > > the name) filed a patent for SoC designs on ASICs where they use > > multiplexers rather than tri-state buses. So ASICs are following in > > FPGA footsteps here. Xilinx has also gradually abandoned on-chip > > tri-states (the 4K had real tri-states, Virtex-2 has a dedicated > > distributed mux, and Spartan-3 gets rid of that and relies on the > > regular logic). Altera has always used the regular logic approach. > > > > So don't worry about the lack of on-chip tri-states in Altera devices > > -- muxes are the way to go. Note that once you're using muxes to > > implement your buses, it also opens up the possibility of using more > > general switching fabrics (in the limit a crossbar) rather than one > > centralized bus. > > > > Vaughn > > Altera
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