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c.chen@gmx.de (Chao) wrote in message news:<8228a344.0406101346.30f8ace2@posting.google.com>...
> I am dealing with the back-annotated SDF timing simulation. The
> timing_vhdl file is generated by the Xilinx ISE tool and I applied it
> to the Modelsim simulator. But how can I obtain my original
> input/output signal?
Maybe you are using a component instance,
and need a configuration.
Here's an example:
____________________________________________
-- vital entity by place+route
-- vho = /usr0/tres/vhdl/xszero/synth/work
configuration vital of test_xszero is
for sim
for dut:socket
use entity vho.xszero(\ep1k50fc256-1\);
end for;
end for;
end configuration vital;
______________________________________________
Or maybe you haven't written a vhdl testbench yet.
It is signals from the testbench architecture.
that drive your design instance.
-- Mike Treseler
Article: 70301Yttrium, The problem looks like the edn files for the FFT are not being correctly copied to the project directory. If you continue to have this problem, then I would recommend that you contact the the Xilinx Hotline, so that they can troubleshoot the problem and help you get it fixed. Regards, Chris Yttrium wrote: >Hey, > >i'm trying out some stuff in the Xilinx System Generator and i got some >errors during translation > >ERROR:NgdBuild:604 - logical block 'streamingfft_fft_fft64a_fft64a' with >type > 'vfft64v2' could not be resolved. A pin name misspelling can cause this, >a > missing edif or ngc file, or the misspelling of a type name. Symbol > 'vfft64v2' is not supported in target 'virtex2'. > >the strangest thing is that when i check in the synthesis report nothing >strange arises and no pin name misspelling has occured. i also tried some of >the aswers on the support site (like disabling read cores and giving a >specific macro search path) but they don't seem to work.... the only thing i >found is that of these components of the design there aren't any edn files? >might that be the problem and how could i make XSG or XST generate them? (i >have tried running XSG regenerating the same design and always the same >problem) > >thanx in advance, > >kind regards, > >Yttrium > > > >Article: 70302
I would be willing to bet NOT. I don't see any sign that the ASBL blocks relate to configuration blocks. Yeah, it would be a great think if they could do that, but I'm not holding my breath. Symon wrote: > > Rick, > I'm so excited that maybe my grammar got away from me. Try replacing > 'excited' with 'optimistic' to get what I meant. The 'new' thing that Xilinx > is pushing is this ASBL block structure. Surely(!?) they've designed these > blocks to be easily individually programmable? Especially as valued > customers like us have been pushing for it for years? > Cheers, Syms. > "rickman" <spamgoeshere4@yahoo.com> wrote in message > news:40C9D9F9.E6D04ADB@yahoo.com... > > Symon wrote: > > > > > > I'm excited that the block structure will finally make partial > > > reconfiguration a reality. > > > > I missed something. I don't see anything that talks about partial > > reconfiguration and what I do see indicates these parts are still > > designed around columns. > > -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 70303
ang_edward@hotmail.com (Edward) wrote in message news:<21076d77.0406110229.55163e02@posting.google.com>... > I am trying to interface the on-board SRAM which board? > (IDT71V416 256Kx16) to the > FPGA on the Stratix. It is not installed among the library components > in the SOPC builder so I cannot instantiate it automatically. > > I have the datasheet for the SRAM but I need to know where the > address, data pins etc. are connected to the FPGA. The pin-out table > doesn't seem to specify that in the Stratix handbook. I would expect to find it in the circuit board docs. > Can anybody tell me where to look for information or an alternative > methodology? That would be really helpful. http://groups.google.com/groups?&q=sram+controller+example -- Mike TreselerArticle: 70304
ang_edward@hotmail.com (Edward) wrote in message news:<21076d77.0406110229.55163e02@posting.google.com>...
> Hello All,
>
> I am trying to interface the on-board SRAM (IDT71V416 256Kx16) to the
> FPGA on the Stratix. It is not installed among the library components
> in the SOPC builder so I cannot instantiate it automatically.
>
> I have the datasheet for the SRAM but I need to know where the
> address, data pins etc. are connected to the FPGA. The pin-out table
> doesn't seem to specify that in the Stratix handbook.
>
> Can anybody tell me where to look for information or an alternative
> methodology? That would be really helpful.
>
> Thanks a mil!
> Ed
Hi Ed,
Hmm, sounds awfully like you have the Nios dev kit ('pro' edition).
The easy way to get your SRAM going is to locate your Nios kit
installation CD and make sure your install is up-to-date. That SRAM
chip *should* be included with SOPC Builder if you have Nios properly
installed. It will be listed under the components for the Nios 1S40
dev board.
For pin-outs, the various Nios/Nios II example designs (standard or
standard_32) will have this SRAM instantiated and will have all the
pins wired up and ready-to-go. This should save some time over
manually assigning the pins! (a human-error-prone process I have never
been fond of regardless of the tool).... so the ultra-easy way do use
this SRAM would be to simply copy one of these Nios exampled designs
off to a separate location, modify at-will to get the
peripherals/system choices you need, and keep the SRAM/pinouts/Avalon
connections the same.
Regards,
Jesse Kempa
Altera Corp.
jkempa at altera dot com
Article: 70305Let me correct this: 1. Resistance by itself does not matter. The product of resistance times capacitance matters. 2. When the process is scaled down, the metal thickness really is not (or hardly) reduced. It still is around a micron, as it has been for years. So, when all horizontal dimensions are cut in half, the metal traces become half as wide and half as long, which means resistance is constant. Yes, most metal traces are now much thicker than they are wide! And it would appear that the capacitance of a half-width trace that is half as long would be reduced 75%, and the RC product would thus be 4 times lower. Reality is less benign, since the capacitive fringe effects take over, and the sidewall capacitance and the trace-to-trace capacitance really increases. Interconnect delays matter, but we can send a signal over quite a distance in a single nanosecond. And on clock lines we can magically eliminate the delay completely, using a DCM. Peter Alfke Phil Hays wrote: > > (Hal Murray) wrote: > > <Snip> > >Suppose I design a FPGA with old fashioned tbufs and long lines, but > >don't cover the width of the whole chip, but just X LUT/FF units. > >Would that track other speed improvements as silicon gets faster? > > No, interconnect does not scale. Interconnect gets slower as the > device geometry gets smaller. > > Transistors scale. As they get smaller, the operating voltage > decreases and the switching speed increases. Nice, eh? > > Interconnect has a bulk resistivity set by the material. The end-to > end resistance is (resistivity*length)/(width*thickness). If the > ratios between length : width : thickness are constant, the resistance > doubles if the size halves. This is why interconnect was almost > ignorable at 3 micron geometry and is a major source of delay at .90 > micron, even after changing to copper with a lower bulk resistivity. > > -- > Phil Hays > Phil_hays at posting domain should work for emailArticle: 70306
Does anybody know if the Xilinx Paralel cable IV cable can be made to work under Linux w/ ISE 6.1i.03? And to make it even more interesting, my Linux is AMD64, will the driver work at all on this system? .... and while we're on the subject, the Linux driver source is itself is pretty basic. Is there programming informatino for the cable that one can use to write custom software to drive the device. -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep."Article: 70307
Hi, > i try to latch external data (AD7...AD0) into an internal > FPGA register on the rising edge of an external signal > (address latch enable = ALE). Isn't ALE supposed to be used with an actual latch, like a 74LS373, where you'd tie ALE to the G (enable) input? There are latch primitives in some FPGAs if you need to use them. In any event, you said you are using rising edge triggered flip flops with ALE as the clock. Are you sure the "data" is valid at the rising edge of ALE? If I were NOT using latches, and instead elected to use flip flops, I'd clock the "data" on the negative edge of ALE. EricArticle: 70308
Hi, Go to http://www.engr.sjsu.edu/crabill and download Lab #1. Eric Yang-Tzu wrote: > > Hello everybody, > > I am trying to use Xilinx's tool, ISE4.1i, to generate the > bitstream file from my VHDL designs. > > If I have three designs named A, B, C. Designs B and C are the > components of A. When I using Xst to synthesize C, it could be done. > But if I synthesize A, B, and C, errors occured. Therefore, I could > have no choice but stop. > > Could anyone tell me how to using the xilinx command line from > synthesize VHDL files to generate bitstream file (or SVF file)? Any > Documents about this? I am reading the documents of "Development > System Reference Guide" of xilinx, but no good answers. > Could anyone tell me the correct design flow or give me an example > using command line to synthesize, PAR and generate configuration > files? > The chip I am using is xc2s100-5pq208. > Thanks for any answers. > > Yang-TzuArticle: 70309
The following solution record should help: http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=18612 There is information that allows for customized cable use. Stephen Williams wrote: > > Does anybody know if the Xilinx Paralel cable IV cable can > be made to work under Linux w/ ISE 6.1i.03? And to make it > even more interesting, my Linux is AMD64, will the driver work > at all on this system? > > > .... and while we're on the subject, the Linux driver source is > itself is pretty basic. Is there programming informatino for the > cable that one can use to write custom software to drive the > device.Article: 70310
Neil Glenn Jacobson wrote: > The following solution record should help: > > http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=18612 > > > There is information that allows for customized cable use. Not really. There is driver source, but all that does is allow one to write programs to send bytes to the device. That does not say what the interesting byte streams are. For example, is it a bit-banged JTAG interface, or are there high-level commands that the device understands. I've downloaded and looked at the driver source in the tar file. It is a very thin layer. This basically tells me there are ways to send bytes, but nothing about what those bytes should be. And these app notes say that Linux support starts with ISE 6.2i. That is not what I was hoping to hear. -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep."Article: 70311
Rajeev wrote: > glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote in message news:<Oxmxc.15640$HG.9409@attbi_s53>... >>(snip) >>To me, a global asynchronous reset driven from an external >>pin, or by the FPGA itself, is fine. The user of the system >>is then responsible for any required timing. (I believe most > I was puzzled by your saying this. It seems clear that neither the system > nor user (ie external to the chip) has any control over the reset skew > internal to the device, and that they cannot fix a startup problem caused > by this. Perhaps the answer is application-dependent: > I can see global external async reset being fine for the class of > designs which reset into an idle state, ie they don't do anything until > they receive an external trigger. Yes, that is the type of device I was considering. The external trigger might be a clock edge, though, so one should be sure not to enable that clock too soon. -- glenArticle: 70312
Sorry - typo - there is NO information that allows customized for cable use. The solution record describes how to make the driver work for iMPACT on other Linux platforms. Stephen Williams wrote: > Neil Glenn Jacobson wrote: > >> The following solution record should help: >> >> http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=18612 >> >> >> There is information that allows for customized cable use. > > > Not really. There is driver source, but all that does is allow > one to write programs to send bytes to the device. That does not > say what the interesting byte streams are. For example, is it a > bit-banged JTAG interface, or are there high-level commands that > the device understands. > > I've downloaded and looked at the driver source in the tar file. > It is a very thin layer. This basically tells me there are ways > to send bytes, but nothing about what those bytes should be. > > And these app notes say that Linux support starts with ISE 6.2i. > That is not what I was hoping to hear. >Article: 70313
Sorry - typo - There is NO information that allows for customized cable use. The cable is for use only with Xilinx-supplied applications Stephen Williams wrote: > Neil Glenn Jacobson wrote: > >> The following solution record should help: >> >> http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=18612 >> >> >> There is information that allows for customized cable use. > > > Not really. There is driver source, but all that does is allow > one to write programs to send bytes to the device. That does not > say what the interesting byte streams are. For example, is it a > bit-banged JTAG interface, or are there high-level commands that > the device understands. > > I've downloaded and looked at the driver source in the tar file. > It is a very thin layer. This basically tells me there are ways > to send bytes, but nothing about what those bytes should be. > > And these app notes say that Linux support starts with ISE 6.2i. > That is not what I was hoping to hear. >Article: 70314
If you are invloved in designing low power or heat sensitive applications visit http://www.quicklogic.com/lowpower and register for the Techonline seminar on Low PowerArticle: 70315
Neil Glenn Jacobson wrote: > Sorry - typo - > > There is NO information that allows for customized cable use. > > The cable is for use only with Xilinx-supplied applications And the Xilinx applications with ISE 6.1i cannot use it under Linux. Correct? -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep."Article: 70316
Hi Can anyone please give me an rough overview about prices of IPs for the Xilinx Virtex II Pro? i.e. 10/100 Ethernet CAN-Controller LIN - Local Interconnect Network Bus Controller (iLIN) Do I have to pay for each sold piece or one time or one time per project? FrankArticle: 70317
Frank, I'm not being rude, but that's kinda like asking "Can you give me a brief overview of the price of cars fuelled by petrol? i.e. SUV Compact Luxury Do I have to lease, finance or purchase?" To answer your question, you gotta go to your local IP mall! Have a nice weekend, Syms "Frank Benoit" <nospam@xyz.com> wrote in message news:pan.2004.06.12.00.33.17.424256@xyz.com... > Hi > > Can anyone please give me an rough overview about prices of IPs for the > Xilinx Virtex II Pro? i.e. > 10/100 Ethernet > CAN-Controller > LIN - Local Interconnect Network Bus Controller (iLIN) > Do I have to pay for each sold piece or one time or one time per project? > > Frank > >Article: 70318
Yes, it is this kind of asking. In your example i think i can give an answer. But with IPs? Do I have to think about 100$ or 100.000$ for an ethernet mac? If every IP like the listed examples is about 10.000$ or more I don't have to think about it any longer. If someone has examples, it would be nice. FrankArticle: 70319
On Fri, 11 Jun 2004 11:31:18 -0700, Stephen Williams wrote: > > Does anybody know if the Xilinx Paralel cable IV cable can > be made to work under Linux w/ ISE 6.1i.03? And to make it > even more interesting, my Linux is AMD64, will the driver work > at all on this system? > > > .... and while we're on the subject, the Linux driver source is > itself is pretty basic. Is there programming informatino for the > cable that one can use to write custom software to drive the > device. The driver is tied to the kernel in Redhat 8.0 (I think it's 2.4.17). They don't have a patch for a modern kernel.Article: 70320
I have real life experience with moisture effects with BGA parts, Bake them at the recommended temp for the time specified on the bag, or yoiu will get disconnected wires to the pins. I found that my assembler used parts stored in an 'office environment' for several days, and *ALL* parts turned out to have bad connections when the boards were done. The humidity issue is very real, follow the directions on the bag, really. A burned designer "Dave Marsh" <me@privacy.net> wrote in message news:40a0dd9d$0$15249$fa0fcedb@lovejoy.zen.co.uk... > I have twenty Xilinx XC9572XL VQFP64. Their sealed package has been open two > months, and stored in an office with no temperature/humidity control. Now I > want to get these devices soldered in for a pre-production run. > > If I put these in without carrying out a baking cycle am I asking for > trouble? What are the likely effects due to moisture, and what are people's > real-life experiences? > > Many thanks, > > Dave > > >Article: 70321
[DRAM refresh not needed if you read/write often enough] >I've never seen anybody take advantage of that though. We built a delay line using DRAM. The idea was to simulate a 10,000 km 155 megabit link in order to test software. No refresh needed. Just assign the RAS/CAS bits such that you use each row often enough. On the other hand, you can save power if you don't touch rows more often than necessary. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 70322
The real question is not if the support partial reconfiguration ... but you and how many others want it... there was a partially configurable Xilinx ...once .. many years ago... but it came and went.. this is capitalism not fantasy money talks the rest walk. So unless someone is willing to spend $$$ partial reconfiguration is an electric dream. and if you really need it.. put down 2 devices :-) Simon "Symon" <symon_brewer@hotmail.com> wrote in message news:2iu5tqFqvetqU1@uni-berlin.de... > Rick, > I'm so excited that maybe my grammar got away from me. Try replacing > 'excited' with 'optimistic' to get what I meant. The 'new' thing that Xilinx > is pushing is this ASBL block structure. Surely(!?) they've designed these > blocks to be easily individually programmable? Especially as valued > customers like us have been pushing for it for years? > Cheers, Syms. > "rickman" <spamgoeshere4@yahoo.com> wrote in message > news:40C9D9F9.E6D04ADB@yahoo.com... > > Symon wrote: > > > > > > I'm excited that the block structure will finally make partial > > > reconfiguration a reality. > > > > I missed something. I don't see anything that talks about partial > > reconfiguration and what I do see indicates these parts are still > > designed around columns. > > > >Article: 70323
Arturo, > I'm a new user of fpga, actually i'm learning about it and i need > help. > I want to know how import cpu's cores (8051 or z80) into a xilinx fpga > device ( Spartan IIe ). If someone can send me a tutorial where i can > learn about that i thanks a lot. You may also want to have a look at Nexar (http://www.altium.com/nexar) They have a pre-synthesised 8051, z80 and PIC16C cores for Altera and Xilinx complete with build (C and asm) and debugging tools. They also have a schematic entry front end with their cores where you can place a 8051, z80 etc on a sheet and connect it up making it child’s play and ideal for designers new to fpga. There is a couple of good tutorials which come with the package.Article: 70324
Frank Benoit <nospam@xyz.com> wrote in message news:<pan.2004.06.12.02.06.43.85995@xyz.com>... > Yes, it is this kind of asking. In your example i think i can give an > answer. But with IPs? Do I have to think about 100$ or 100.000$ for an > ethernet mac? If every IP like the listed examples is about 10.000$ or > more I don't have to think about it any longer. If someone has examples, > it would be nice. > > Frank http://www.opencores.com have some for free. Cheers, JonB
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