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Martin Maurer wrote: > Hello, > > i have the following problem: i try to latch external data (AD7...AD0) into > an internal FPGA register on the rising edge of an external signal (address > latch enable = ALE). Generally this seems to work, but i often have > situations where a very short peak is on the signal ALE. Peak is around 20 > ns (can measure them with a scope), whereas my normal signal is around 12 us > (600 times longer). > > What is a common way of handling this ? Best solution is to remove the glitch :) That may not always be possible - if not, are you confident you know what it causing it, and thus its MAX width when illegal ? <snip> > > 2) I found a lot of articles about doing an RC at the input side. How do i > calculate the values of R and C e.g. when i want to ignore all pulses below > 50 ns ? The RC product, or timeconstant of 3-5x Glitch get you in the ball-park of some-attenutaion. You need to confirm comfortably dropping it below the threshold, but also avoid going below the FPGAs min input slew rate, as well as not distorting the good edge outside valid data times.... An external RC plus a 1G14 or 1G17 SCHMITT tiny logic gate is probably the best solution, as you can probe the filtered, squared output to verify data windows. > 3) Is there any method to do it FPGA internal ? Don't want to add external > hardware... read of bad ways with delay lines.... This is possible, but risky, so should only be a path of last resort... > i think i read somewhere > of reserved words like "SKEW", "SLOW", "FAST". Do they help me ? Should i go > in this direction ? No, these are PIN features, not noise filters. > 4) Or must i add an external clock only for this ? E.g. with a counter, only > when certain count value is reached, the line is valid ? Depends on if ALE is async with this. 12us is relatively slow, so if you have a MHz region clock already in the FPGA, you can always make a digital filter from a simple saturating counter. You need to ensure the sampling instant is comfortably clear of both DATA invalid edges. -jgArticle: 70276
Hey, Why so much negativity on this board regarding V4 already? It's the most kick-ass and awesome FPGA ever made. How bout some kudos and a big thanks to Xilinx for stepping up to the plate and hitting one out of the park? If you think the parts are not planned right or no thinking was put into it you are on a different planet. The people with the most desire for the right features determined the results. I really don't think Xilinx told their customers what they need. So I would humbly submit to you that if you don't understand the thinking, then you don't understand the market. Anyway, let's get a bit excited on this board about the most significant advancement in FPGA technology in several years. It will completely blow Stratix II and anything else out of the water in every regard. Great thinking and innovation seem to be poured into V4. 500 MHz all over the place. 3 versions, Everything, logic, DSP PPC 405 600 to 11 Gbps I/O 1 Gbps I/O on every pin Sounds pretty spectacular to me. So get a bit excited and have some positive thinking out there. V4 SX, LX, and FX are going to be the standard in 90 nm FPGA technology. Yeah! "Brannon King" <bking@starbridgesystems.com> wrote in message news:<ca9v66$m5@dispatch.concentric.net>... > So after looking at the Virtex4 line of devices and their associated > features > (http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=v4_asmbl), I'm a > little miffed at their chip resource allocation. > > First of all, suppose I'm planning on filling an FPGA full of logic. I'm > probably going to run the majority of that logic in the same clock domain so > I don't need a whole lot of DCMs. However, I do need some way to get my data > to/from the chip. What's up with zero transceivers on the "logic platform"? > The same can be asked of the "signal processing platform". I was so looking > forward to getting away from the old parallel I/O issues, and if I'm going > to have to deal with that, maybe we better leave those DCMs on there. It > wouldn't take very many transceivers to alleviate the issue. > > Second, what about those of us who build and prototype digital bus > controllers, routers, and similar applications. In that situation I'm > looking for an FPGA with lots of memory, lots of transceivers, lots of DCMs, > a fair amount of logic, and not much else. DSP and Processors don't really > help me in that type of application, yet to get what I need I will end up > spending the extra money for the FX chip.Article: 70277
what is frame buffer? "Tommy Thorn" <TommyAtNumba-Tu.Com--not@yahoo.com> ??? news:bZRxc.16121$Fo4.211255@typhoon.sonic.net ???... > San San wrote: > > I wonder who is using lancelot daughter board for altera bios dev board? > > Can we exchange email for discussion?I have many problem about this. I am > > green to FPGA system design. > > Most certainly. H. Peter Anvin started a mailing list for the Lancelot > + Altera Nios Dev boards (see below) that you should join. Framebuffer > graphics is pretty easy (mine is about a page). Sounds is interesting, > but HPAs Sigma-delta converter is on the Lancelot page. PS/2 kbd and > mouse is mostly a software issue, but HPAs ABC80 supports keyboard. > > Tommy > > Here the call from participation: > > Hi all, > > I have no idea how big this community is, but I've been trying to set > up a mailing list for people who hack the Altera NIOS kits > (APEX/Cyclone/Stratix) and especially using the Lancelot boards from > www.fpga.nl. > > This may sound rather restrictive, but the hope is that there will be > enough of a group that we can trade designs around. > > The subscription/archives page is at: > > http://www.zytor.com/mailman/listinfo/lancelot > > I hope we can get some people together, at least. > > -hpa >Article: 70278
There is no difference in Stratix and Stratix II anyway. So what does it matter? If there is a difference, other than Altera finally doing a full copy of the Virtex II structure, I'd be happy to hear about it. There is no new innovation in Stratix II. It's just a shrink of Stratix. A bit faster and denser. That's it. Stratix II is same as Stratix. Hey, what happened to the vaunted Terminator technology? It got stripped out of Stratix. I see it is supposed to work in Stratix II again. Serial resistor only. I guess we will find out if it does or not after several customers find out if it meets the spec. Just like in Stratix. davidg@altera.com (Dave Greenfield) wrote in message news:<5c156a0b.0406101600.61f08aa9@posting.google.com>... > We have highlighted that Stratix II devices will ship to customers in > July. Stratix II checkout and characterization is proceeding ahead of > schedule. Stratix II Development Kits are on track to ship later in > Q3. > Dave Greenfield > Altera Product Marketing > > > > > Any news on when a Stratix-II Dev kit will be available? > > > > TommyArticle: 70279
"Stifler" <seannstifler69@hotmail.com> wrote in message news:bf780a06.0406102246.528d26e4@posting.google.com... > There is no difference in Stratix and Stratix II anyway. So what does > it matter? If there is a difference, other than Altera finally doing a > full copy of the Virtex II structure, I'd be happy to hear about it. > > There is no new innovation in Stratix II. It's just a shrink of > Stratix. A bit faster and denser. That's it. Stratix II is same as > Stratix. > You haven't looked at any information on the Stratix II, have you? They use a completely different type of basic logic element (6 input LUTs with 2 outputs, rather than the standard 4 input, 1 output LUT). Ultimately, the result is faster and denser, but it is hardly "just" a shrink of the Stratix. And of course, there is the usual progress you'd expect for a new generation of chips - more memory, faster I/O, etc., which is useful but not as "innovative" as the new logic structure. > Hey, what happened to the vaunted Terminator technology? It got > stripped out of Stratix. I see it is supposed to work in Stratix II > again. Serial resistor only. I guess we will find out if it does or > not after several customers find out if it meets the spec. Just like > in Stratix. > > > davidg@altera.com (Dave Greenfield) wrote in message news:<5c156a0b.0406101600.61f08aa9@posting.google.com>... > > We have highlighted that Stratix II devices will ship to customers in > > July. Stratix II checkout and characterization is proceeding ahead of > > schedule. Stratix II Development Kits are on track to ship later in > > Q3. > > Dave Greenfield > > Altera Product Marketing > > > > > > > > Any news on when a Stratix-II Dev kit will be available? > > > > > > TommyArticle: 70280
On Thu, 10 Jun 2004 10:13:39 +0100, Andrew Greensted <ajg112@ohm.york.ac.uk> wrote: >But seriously, has anyone had any experience (good or bad) programming >xilinx devices over JTAG with third party devices in the chain. I don't know why your setup fails, but I'm having good luck with a three-device chain: Xilinx CPLD - Xilinx Virtex II - Analog Devices ADSP-2196. I'm using ISE 6.2, iMPACT, and a Xilinx Parallel Cable IV. I inserted '>' characters to reduce newsreader line-wrap problems. Here's my iMPACT script: > setMode -bscan > setCable -port lpt1 > addDevice -p 1 -file mycpld.jed > addDevice -p 2 -file xc2v250.bsd > addDevice -p 3 -file adsp2196m.bsd > program -e -p 1 > quit Here's my adsp2196m.bsd: > entity generated_adsp2196m is > generic (PHYSICAL_PIN_MAP : string := "X_PACKAGE"); > port (TCK: in bit; TDI: in bit; TDO: out bit; TMS: in bit); > use STD_1149_1_2001.all; > attribute Component_Conformance of adsp2196m : entity is "STD_1149_1_2001"; > attribute PIN_MAP of adsp2196m : entity is PHYSICAL_PIN_MAP; > constant X_PACKAGE:PIN_MAP_STRING := "TCK : 1," & "TDI : 2," & "TDO : 3," & "TMS : 4"; > attribute Tap_Scan_In of TDI: signal is true; > attribute Tap_Scan_Mode of TMS: signal is true; > attribute Tap_Scan_Out of TDO: signal is true; > attribute Tap_Scan_Clock of TCK: signal is (1.0e06, BOTH); > attribute Instruction_Length of adsp2196m: entity is 5; > attribute Instruction_Opcode of adsp2196m: entity is "BYPASS (11111)"; > attribute Instruction_Capture of adsp2196m: entity is "XXX01"; > attribute Boundary_Length of adsp2196m: entity is 1; > attribute Boundary_Register of adsp2196m: entity is "0 (BC_1, *, control, 0)"; > end adsp2196m;Article: 70281
Can you point me to some technical data on the enhanced partial
reconfig capabilities? I'm very interested in this area and I can't
seem to find anything on Xilinx's site that wasn't written by somebody
from the marketing department.
- a
"Symon" <symon_brewer@hotmail.com> writes:
> I bet the answer you get from Xilinx will be along the lines of "we analysed
> X number of designs from our customer base and found these three to be the
> best fit (to maximise our profits)". They won't actually say the bit in
> parentheses, but that's what they're in business for. Fair enough.
> I guess the 'new' architecture makes it somewhat easier to add further
> variants. After all, they've only used three letters (LSF) so far, that
> leaves space for 23 more mixes! ;-)
> I'm excited that the block structure will finally make partial
> reconfiguration a reality.
> cheers, Syms.
>
>
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great disturbance in the Force: it was as if a billion washing
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Article: 70282Hello As I'm a beginner with the Simulink tool, I'm very interrested in example designs for System Generator. Can anyone post a link or something ? I want to design filters which should run on a fpga (Xilinx Spartan 2 Xc2s200). But there are questions that the manual doesn't answer... (like : how do I access data from the fpga board sram to put it to the filter) Regards, Timo Dammes Circuits and System Lab University of Dortmund, GermanyArticle: 70283
hi, im having trouble infering a dual port ROM with xilinx ISE 5.2i. I can infer dual port RAM, but i need it to be ROM in order to have it initialised. does anybody know how to do it? i've been searching the web and xilinx website, but i havent seen how to infer a dual port ROM, only regular ROM, but i need to do two read access (and given that the ROMs will be implemented in BlockRAM, it'd be a waste if i had to use two cycles to read from dual port capable BlockRAMs) i'd like the approach to be VHDL, cause it seems that you can do it with Coregen?? but i want it to be VHDL cause the ROM generation has to automatic (thru a C program that generates VHDL code) comments are welcome, TIAArticle: 70284
Hi all! I'm using ISE 6.1 and a Spartan3 fpga. Last day I tried to instantiate a synchronous FIFO using Logicore. When I use this instance in my design the beavioural simulation works perfectly while the post-translate (and the others too) simulation don't. Looking at the RTL schematic I saw that the vector output of the instantiated fifo weren't connected with the output and with the other elements in the design. I tried to instantiate other memories...asynchronous fifo and so on but the problem is always the same. What can I do? The instantiated fifo working in a standalone manner (providing all signal throug a testbench) work fine even in the post-translate. Can you help me? Thanks a lot Guido Inviato da www.mynewsgate.netArticle: 70285
It does not have to be ROM to be initialised. I usually use constraints editor or go directly to the ucf file to set the RAM/ROM initial values. The blockram can be considered as writeable ROM that simply isn't written. Usually I tie off the write enable to the inactive state if it really matters but more often being able to split the blockram into a combination of RAM and pseudo ROM is more useful to me. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk This message is the personal opinion of the sender and not that necessarily that of Enterpoint Ltd.. Readers should make their own evaluation of the facts. No responsibility for error or inaccuracy is accepted. "sebastian" <malaka@email.it> wrote in message news:6aefd6be.0406110137.58a0268f@posting.google.com... > hi, > > im having trouble infering a dual port ROM with xilinx ISE 5.2i. I can > infer dual port RAM, but i need it to be ROM in order to have it > initialised. does anybody know how to do it? i've been searching the > web and xilinx website, but i havent seen how to infer a dual port > ROM, only regular ROM, but i need to do two read access (and given > that the ROMs will be implemented in BlockRAM, it'd be a waste if i > had to use two cycles to read from dual port capable BlockRAMs) > i'd like the approach to be VHDL, cause it seems that you can do it > with Coregen?? but i want it to be VHDL cause the ROM generation has > to automatic (thru a C program that generates VHDL code) > comments are welcome, TIAArticle: 70286
Hello All, I am trying to interface the on-board SRAM (IDT71V416 256Kx16) to the FPGA on the Stratix. It is not installed among the library components in the SOPC builder so I cannot instantiate it automatically. I have the datasheet for the SRAM but I need to know where the address, data pins etc. are connected to the FPGA. The pin-out table doesn't seem to specify that in the Stratix handbook. Can anybody tell me where to look for information or an alternative methodology? That would be really helpful. Thanks a mil! EdArticle: 70287
Inference doesn't work for this case on any tool that i am aware of. You
can instantiate dual port RAMs, initialize them with the init=attributes
and generics (latest synplify generates the attributes from the generic).
For ROM, just tie the write enables to '0'.
sebastian wrote:
> hi,
>
> im having trouble infering a dual port ROM with xilinx ISE 5.2i. I can
> infer dual port RAM, but i need it to be ROM in order to have it
> initialised. does anybody know how to do it? i've been searching the
> web and xilinx website, but i havent seen how to infer a dual port
> ROM, only regular ROM, but i need to do two read access (and given
> that the ROMs will be implemented in BlockRAM, it'd be a waste if i
> had to use two cycles to read from dual port capable BlockRAMs)
> i'd like the approach to be VHDL, cause it seems that you can do it
> with Coregen?? but i want it to be VHDL cause the ROM generation has
> to automatic (thru a C program that generates VHDL code)
> comments are welcome, TIA
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 70288
Hello everybody,
I am trying to use Xilinx's tool, ISE4.1i, to generate the
bitstream file from my VHDL designs.
If I have three designs named A, B, C. Designs B and C are the
components of A. When I using Xst to synthesize C, it could be done.
But if I synthesize A, B, and C, errors occured. Therefore, I could
have no choice but stop.
Could anyone tell me how to using the xilinx command line from
synthesize VHDL files to generate bitstream file (or SVF file)? Any
Documents about this? I am reading the documents of "Development
System Reference Guide" of xilinx, but no good answers.
Could anyone tell me the correct design flow or give me an example
using command line to synthesize, PAR and generate configuration
files?
The chip I am using is xc2s100-5pq208.
Thanks for any answers.
Yang-Tzu
Article: 70289Hi all. I have to write a code for the MicroBlaze soft processor (Xilinx Platform Studio 6.1.03i) and I am facing the following problem: both my assembly code and my c code have to access some shared (global!) variables but I do not know how to do it. I downloaded all the MicroBlaze documentation from the Xilinx web site (or at least I am convinced I did) but I did not find any clue. Does someone of you out there know how to do it? Regards, Andrea SabatiniArticle: 70290
Hey, i'm trying out some stuff in the Xilinx System Generator and i got some errors during translation ERROR:NgdBuild:604 - logical block 'streamingfft_fft_fft64a_fft64a' with type 'vfft64v2' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, or the misspelling of a type name. Symbol 'vfft64v2' is not supported in target 'virtex2'. the strangest thing is that when i check in the synthesis report nothing strange arises and no pin name misspelling has occured. i also tried some of the aswers on the support site (like disabling read cores and giving a specific macro search path) but they don't seem to work.... the only thing i found is that of these components of the design there aren't any edn files? might that be the problem and how could i make XSG or XST generate them? (i have tried running XSG regenerating the same design and always the same problem) thanx in advance, kind regards, YttriumArticle: 70291
Hi, Timo, A single port ram works in your case, but make sure you dont overwrite the original data before they are processed. I put a bit algorithm here for your ref. in a typical loop,, 1>generate an address 2>set read signal 3>process the data shown at the output port of the ram block using the sysgen block 4>set ram write signal (write the result to the same address of the original data in the ram) then start another loop.. jy "Timo Dammes" <timo.dammes@gmx.de> wrote in message news:c97fbf$d6j$1@nx6.HRZ.Uni-Dortmund.DE... > Hello > > I'd like to use Xilinx System Generator (Matlab Simulink tool) to configure > a Xilinx fpga : (Spartan 2, Xc2s200) for a practical course at university. > > If anyone has experiences with System Generator : > Is it possible to access the memory of the fpga with a block ? I wrote a c++ > program that transfers data (i.e. a picture) to the fpga's memory. Then I'd > like the System Generator schematic to read that data, work with it and > write it back to the memory. Is that possible with the "single port ram" > block ? > > Does anyone already have an example program ? > > Regards, > Timo Dammes > >Article: 70292
Hi is it true that Micron SDRAM does not require any refresh cycles if we are reading the SDRAM rows once in 20 ms atleast? if i dont give any refresh cycles what will be the condition of the SDRAM? please reply me answer.. regards, S.RANGA REDDY dxslyz@lycos.de (Steven) wrote in message news:<bcbfc047.0405260919.70a46cbb@posting.google.com>... > I think, you just send auto refresh command to sdram, and set a count, > let it count down from the cycles it needs. When count equals 0, then > auto refresh is finished. SDRAM does the job automatically. > > > Steven > > > > sudharr@myw.ltindia.com (RANGA REDDY) wrote in message news:<37ba429a.0405252227.77dfb1f2@posting.google.com>... > > Hi all, > > > > can anybody tell how autorefresh in SDRAM exactly works? suppose in > > SDRAM specifications it is mentioned that 64 ms, 4096 cycle > > refresh(15.6 us/row) what exactly it means and how we need to generate > > the autorefresh cycles. > > > > actually i am trying to upgrade the 512k*4*32 SDRAM(Fujitsu Make) to > > Micron Make 1M*4*32 SDRAM. > > > > FUJITSU specifies that 4K refresh cycles every 16ms, auto refresh (3.9 > > us) and micron specifies that 64 ms, 4096 cycle refresh(15.6 us/row). > > > > Did any body tried to do this kind of upgradation. we have the code > > for Fujitsu SDRAM specifications. > > > > Anybody can help in this regard please reply to > > sudharr@myw.ltindia.com .i can send u the data sheets of both the > > SDRAMs,if you want. > > > > thanks and regards, > > > > S.RANGA REDDYArticle: 70293
"Stifler" <seannstifler69@hotmail.com> wrote in message news:bf780a06.0406102214.3bc26509@posting.google.com... > Hey, > > Why so much negativity on this board regarding V4 already? It's the > most kick-ass and awesome FPGA ever made. How bout some kudos and a > big thanks to Xilinx for stepping up to the plate and hitting one out > of the park? Has it been made yet? I was real happy to see the announcement but a bit disappointed that it didn't come with some data sheets for a good architectural description with all the minutia about resources available in the planned parts. I'm okay with not having working silicon for a short while but I think some of the backlash on this board was because of the insensitive tease. Bait the engineers with something that looks very good but don't give them any real meat. I'm looking forward to further news. > If you think the parts are not planned right or no thinking was put > into it you are on a different planet. The people with the most desire > for the right features determined the results. I really don't think > Xilinx told their customers what they need. So I would humbly submit > to you that if you don't understand the thinking, then you don't > understand the market. > > Anyway, let's get a bit excited on this board about the most > significant advancement in FPGA technology in several years. It will > completely blow Stratix II and anything else out of the water in every > regard. Great thinking and innovation seem to be poured into V4. You may be overstating a bit to suggest this is "the most significant advancement" since the features are almost everything we've already seen. The PPC, the MGT, the CLB structure (I believe) are all pretty much the same. The evolutionary features that are attractive include the enhanced DSP elements including hardware divide and the no-overhead FIFO mode for the BlockRAMs. Neat stuff, but it doesn't come across as a revolutionary product. Evolutionary is fine. Didn't Stratix-II come out with a "revolutionary" change to the LUT structures to allow interesting input configurations such as independent 3-bit and 5-bit input functions without chewing up other resources? A little flexibility is a good thing. Don't get me wrong - I like the LUTs we get from Xilinx thanks to the memory and SRL capabilities; I've used them virtually unchanged for years and years. > 500 MHz all over the place. > 3 versions, Everything, logic, DSP > PPC 405 > 600 to 11 Gbps I/O > 1 Gbps I/O on every pin A nice feature set, indeed. > Sounds pretty spectacular to me. So get a bit excited and have some > positive thinking out there. V4 SX, LX, and FX are going to be the > standard in 90 nm FPGA technology. > > Yeah! I'm hoping Xilinx continues to deliver the price/performance advantages we've come to enjoy. Looking forward to it!Article: 70294
RANGA REDDY wrote: > is it true that Micron SDRAM does not require any refresh cycles if we > are reading the SDRAM rows once in 20 ms atleast? if i dont give any > refresh cycles what will be the condition of the SDRAM? AFAIK, *no* SDRAM requires refresh cycles if all the rows you care about are touched (read or written) sufficiently often. I think once every 64ms is enough. I've never seen anybody take advantage of that though. TommyArticle: 70295
Symon wrote: > > I'm excited that the block structure will finally make partial > reconfiguration a reality. I missed something. I don't see anything that talks about partial reconfiguration and what I do see indicates these parts are still designed around columns. I am still waiting for modular configuration support for Spartan 3. I was told over six months ago that they had just a couple of issues that needed to be addressed before they could provide this and that Xilinx was commited to providing this feature. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 70296
Adam, I don't know any technical details, but it struck me that the block structure is ideally suited to partial reconfiguration on a block by block basis. It's like lots of mini FPGAs on one die, much more than it was before. I don't believe that Xilinx will pass up this opportunity to tune the software to allow block by block P&R etc. I envisage an application, a bit like Ultracontroller, that demonstrates 'partial configuration for dummies' of a ASBL block with a standardised interface to adjacent blocks. I'd recommend pestering your FAE, if enough people are interested or, more importantly, enough people will use this feature, I'm sure the marketing machine will respond! From my point of view, with an FPGA with as many gates as these parts will have, I think partial reconfiguration will become the norm as more and more little ASICs are converted to IP and hoovered up into the FPGA. cheers, Syms. "Adam Megacz" <adam@megacz.com> wrote in message news:m13c521ot7.fsf@nowhere.com... > > Can you point me to some technical data on the enhanced partial > reconfig capabilities? I'm very interested in this area and I can't > seem to find anything on Xilinx's site that wasn't written by somebody > from the marketing department. > > - aArticle: 70297
Tommy Thorn wrote: > > RANGA REDDY wrote: > > is it true that Micron SDRAM does not require any refresh cycles if we > > are reading the SDRAM rows once in 20 ms atleast? if i dont give any > > refresh cycles what will be the condition of the SDRAM? > > AFAIK, *no* SDRAM requires refresh cycles if all the rows you care about > are touched (read or written) sufficiently often. I think once every > 64ms is enough. > > I've never seen anybody take advantage of that though. There are some apps where the refresh is done automatically by the repetitive accesses, like video for example. The refresh period varies with different row/column sizes and layout, so check the data sheet! I recall that the older parts were in the low ms range, but the period increased as the number of rows increased. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 70298
Hello Timo When you install Sysgen there are many demos that are included in the install directory: %my_matlab_install%\toolbox\sysgen62\xilinx\sysgen\examples %my_matlab_install%\toolbox\sysgen62\xilinx\sysgen\examples\demos There are a number of different filters included in the examples. If you are trying to read data from external sram (?) then you could use a memory controller to read data into the FPGA. If you are building a parallel filter then the data is usually applied directly to the filter after a couple pipeline stages for performance. If you are using a MAC structure then often you will want to use memory buffers to align your data with your coefficients. Xilins offers a classes that cover these topics in detail: http://www.xilinx.com/support/training/cur_paths/atp-dsp.htm The classes are available in Germany and other places in Europe. Cheers, Elliot Timo Dammes wrote: > Hello > > As I'm a beginner with the Simulink tool, I'm very interrested in example > designs for System Generator. Can anyone post a link or something ? > > I want to design filters which should run on a fpga (Xilinx Spartan 2 > Xc2s200). But there are questions that the manual doesn't answer... (like : > how do I access data from the fpga board sram to put it to the filter) > > Regards, > Timo Dammes > Circuits and System Lab > University of Dortmund, GermanyArticle: 70299
Rick, I'm so excited that maybe my grammar got away from me. Try replacing 'excited' with 'optimistic' to get what I meant. The 'new' thing that Xilinx is pushing is this ASBL block structure. Surely(!?) they've designed these blocks to be easily individually programmable? Especially as valued customers like us have been pushing for it for years? Cheers, Syms. "rickman" <spamgoeshere4@yahoo.com> wrote in message news:40C9D9F9.E6D04ADB@yahoo.com... > Symon wrote: > > > > I'm excited that the block structure will finally make partial > > reconfiguration a reality. > > I missed something. I don't see anything that talks about partial > reconfiguration and what I do see indicates these parts are still > designed around columns. >
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