Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
"Rene Tschaggelar" <none@none.net> wrote in message news:40b323b8$0$700$5402220f@news.sunrise.ch... > Chuck McManis wrote: > > Bringing it back on topic... > > > > Have you played with the FPSLIC stuff? AVR core plus FPGA? I've got the > > development board as I was looking at some sort of custome baseboard > > controller (SMBus, i2c, etc) and it looks great but Atmel doesn't seem > > particularly committed to it ... > > As said, I had no gain in putting any core into an FPGA yet. While using > a standalone cpu let you select between a bunch of compilers, they > somehow vanish when you put a core into an FPGA. > BTW, what does an I2C or SMB, that cannot be done with some port pins ? You mis-read what I typed. The FPSLIC system embeds a "real" ATMEL AVR core inside an FPGA fabric. All the ATMEL compilers work as you'd expect, all the peripherals are on the expected pins, except that the pins go into the FPGA fabric where you can either route them to an "off chip" I/O (using them then like you would normally) or to some device you've cons'd up inside the FPGA. Imagine a multichip module where the FPGA and the microprocessor are on the same subtrate. --ChuckArticle: 69976
"KrishK" <krishk@signalogic.com> wrote in message news:1c0a2959.0405251506.3a6886e6@posting.google.com... > I am using Orcad version 9.2 to create orcad symbols. I am trying to > follow a method described earlier in the same newsgroup. I am > describing pointwise the steps am following: > > 1) I downloaded the pinout table from Xilnx website > 2) I sort the pinout in excel based on bank number > 3) I create a new part in a library in Orcad and place the number of > pins I need using "place pin array" command > 4) I select the pins whose name and pin number have to be changed and > press "CTRL + E" and I get the browse spreadsheet editor in Orcad. > > After that I am not able to do anything other than copy the contents > of the Browse spreadsheet editor. To insert the pin names I select the > coloumn "Name" and I press ctrl + insert, but nothing happens > For instance after I select the "Name" coloumn to be replaced by the > contents I am trying to paste, the commands like "paste" , "copy" > among others just goes unusable(the letters on those commands goes > grey from black). Actually the paste is not active at all irrespective > of whether I select any coloumn or not. > > Is this a version problem? I see Rotem Gazit had posted this message > in 2001. > Please let me know if you have experienced this difficulty before. > > thanks > Krishna Kumar > DSP Systems Engineer > Signalogic Inc > 9617 dallas > TX-75243 Krishna, You have to organize the Xilinx spreadsheet such that the pin-name and pin-number are in the same colunm order as what's in the Orcad spreadsheet (what you see when you select the placed pins and do "properties". Once you've done that, go to the Xilinx spreadsheet and select BOTH columns of cells (name and number). I select the data and don't select the whole columns (I'm not sure if this really matters). Once selected, do a CTRL C. Now, go the Orcad spreadsheet. Select the cells of both columns (name and number) and do a SHIFT INSERT. Close the Orcad spreadsheet and you'll see the name and number's inserted into your symbol. Good luck, BobArticle: 69977
You can try multi-pass place and route as well. -- RobertP.Article: 69978
Landman, First off, your analogy was terrible. You are assuming my getting the brand new car which is faster and better has no cost. If I knew I could have had the better car for the same price 2 years earlier, I would feel like an idiot for not buying it 2 years ago. From my experience, cpu engineers are never too excited about having a processor architecture canceled. It's not a free conversion. The cost of this conversion can be debated. Maybe it's not too costly. A 38 page app note tells me it's not invisible to the engineering team. Engineering effort is required to switch Nios 1 to Nios II. That's not free. Also, custom instuctions are probably as stupid as a window register file. Why do you need a custom instuction so bad? I believe it's simply hardware acceleration. There's several ways to accomplish hardware acceleration. Altera's custom instuction can bog down your processor Fmax. It goes right into the middle of the pipe. Why not simply have your processor launch off a separate process while it continues to grind away at top speed? I can think of several ways to stomp a custom instruction depending on what it is. How about using a dual port ram and write a bunch of data to it. Have my user logic attached to the other side and process it. Tell me when it's done. Or, use a DMA to transfer a burst of data to a user peripheral. Altera hypes this custom instruction crap. It's the same hype as the windowed register file. It's the same joke. It's probably as stupid of an idea as having a windowed register file. Which they just chucked. Along with the 16 bit instructions. As someone already mentioned, MicroBlaze has an FSL interface for hardware acceleration. It probably blows away Altera's custom instruction. "Kenneth Land" <kland1@neuralog1.com1> wrote in message news:<10b7qg7fqd1cod1@news.supernews.com>... > "Jon Beniston" <jon@beniston.com> wrote in message > news:e87b9ce8.0405251505.5b6713a8@posting.google.com... > <snip> > > > > You say it like it doesn't matter. Maybe it doesn't with FPGA CPUs as > > you're obviously not concerned about price anyway ;) > > > > Cheers, > > JonB > > Hard to imagine an embedded project without an fpga. Might as well have > only one chip (fpga + softcore cpu) and save the board space since you're > most likely going to require an fpga anyway. (board space == $$$, parts > count == $$$) > > The reason you would want to use a softcore over hard is because it can be > *exactly* customized to any application. Need 27 serial ports and timers? > no problem. Need none? don't waste the pins or money. Need more > processing power? add custom instructions/external parrallel logic or > another softcore cpu (or 8!). > > I've seen hard core projects fail, but a soft core project can only fail > from early abandonment. More/harder work can always find a solution, > because the hardware can become anything you're willing to realize. > > KenArticle: 69979
Hi all, can anybody tell how autorefresh in SDRAM exactly works? suppose in SDRAM specifications it is mentioned that 64 ms, 4096 cycle refresh(15.6 us/row) what exactly it means and how we need to generate the autorefresh cycles. actually i am trying to upgrade the 512k*4*32 SDRAM(Fujitsu Make) to Micron Make 1M*4*32 SDRAM. FUJITSU specifies that 4K refresh cycles every 16ms, auto refresh (3.9 us) and micron specifies that 64 ms, 4096 cycle refresh(15.6 us/row). Did any body tried to do this kind of upgradation. we have the code for Fujitsu SDRAM specifications. Anybody can help in this regard please reply to sudharr@myw.ltindia.com .i can send u the data sheets of both the SDRAMs,if you want. thanks and regards, S.RANGA REDDYArticle: 69980
"Oscar Garnica" <ogarnica@dacya.ucm.es> wrote in message news:<c8vtvf$6$1@thule.sim.ucm.es>... > Hi, > > We have tried to read/write data from/to SRAM (AS7C4096) using a tri-state > buffer to drive data bus but we are not being able to manage this task. > Whenever we try to read data from the memory we obtain the value 0x0000 > although the memory word has been loaded with a different pattern. > Similarly, when we write data the final value in the memory word is 0x0000 > regardless of the value we drive into the data bus. > > Has anybody any idea about this? What are we doing wrong? > > Thanks a lot > > O. Garnica > UCM Have a closer look at the control signals OE_N, WE_N, CS_N. Is the sram address stable before these signals are asserted for write cycle? RgdsArticle: 69981
"E.S." <emu@ecubics.com> wrote in message news:4KLsc.19641$zs2.4918@fe39.usenetserver.com... > Uncle Noah wrote: > > > In Microblaze there is no way to add your own custom instructions. It > > is not an extensible processor but just provides the means to add > > peripherals to a small SoC. Correct me if i am wrong. I just hope that > > the tools (assembler, simulator, debugger) can be retargeted for the > > new ISA. Or be able to use inline assembly with the new instructions. > > The corresponding hardware should be built by some RTL description i > > would give. > > Sorry, but I think that "custom instructions" are the worst idea. > Than you have to update (with new versions/revisions) not only your > design, but also the whole toolchain ? (assembler/linker/cc ?) > The custom instructions are already available in the toolchain, with pre-defined macros for the assembly instructions. When you want to actually use them for something, you can define new names that make more sense in your application. Gcc does a pretty good job of optomising such assembly macros, so you don't lose anything. I don't know about Nios II (I haven't looked in detail yet), but on the Nios I you can also tell gcc to use custom instructions automatically for certain operations. For example, if you know your code requires a lot of divisions, you can make a custom hardware divider and tell gcc to use it for all divisions. > And there is still tha chance, that the whole CPU slows down, because > of your new instruction, so you even loose, not gaining anything :( > That would be the case if your custom instructions execute too slowly, so that your cpu's max frequency were reduced. The obvious answer then would be to use multi-cycle custom instructions. > Much simpler to access a "accelarator" memory mapped, or as a > peripheral, or whatever interface you have for it. > Sometimes that is the case - it depends on what you are doing. Memory mapped peripherals require memory-style access, however, including loads, stores and address calculations, whereas custom instructions get their data immediately. For fast peripherals, custom instructions will save a lot of overhead.Article: 69982
"Stifler" <seannstifler69@hotmail.com> wrote in message news:bf780a06.0405252226.60e2d1f0@posting.google.com... > Landman, > > Also, custom instuctions are probably as stupid as a window register > file. Why do you need a custom instuction so bad? I believe it's > simply hardware acceleration. There's several ways to accomplish > hardware acceleration. Altera's custom instuction can bog down your > processor Fmax. It goes right into the middle of the pipe. Why not > simply have your processor launch off a separate process while it > continues to grind away at top speed? > > I can think of several ways to stomp a custom instruction depending on > what it is. How about using a dual port ram and write a bunch of data > to it. Have my user logic attached to the other side and process it. > Tell me when it's done. Or, use a DMA to transfer a burst of data to a > user peripheral. > What's next, "My dad could beat up your dad" ? You are arguing about something you aparently neither know about nor care about, so why bother? I've got no idea about what an FSL interface is, having not looked closely at the MicroBlaze, so I don't know how it compares to other solutions - certainly not enough to declare it "stupid". But there are many ways to do hardware acceleration of a soft cpu on an fpga, and there are many sorts of tasks that could be accelerated - what is the big problem with Altera offering one more? I'm sure it is possible to cause yourself problems by using it badly, such as trying to do a slow process in a single clock cycle and thus reducing your fMax, or stalling the processor for hundreds of cycles - that's bad design on the user's part, not the fault of the custom instruction concept. If your application calls for fast, simple custom operations, however, then the custom instruction mechanism cuts down the overhead quite significantly. You choose the hardware acceleration method that matches the requirements. > Altera hypes this custom instruction crap. It's the same hype as the > windowed register file. It's the same joke. It's probably as stupid of > an idea as having a windowed register file. Which they just chucked. > Along with the 16 bit instructions. > Windowed register files have some advantages over traditional register banks, and some disadvantages - and how they affect you depends on the application. Sun's SPARC processors are good for some uses, and poor on others. There are lots of choices when designing processors - register setup and instruction formats are two of them. What makes the "best" design will depend on many factors, such as application, speed, fpga size, fpga design, code density - and it will also change over time, as the developers come up with better designs, and as development tools improve. But just because the Nios II is in many ways better than the Nios I, doesn't make the Nios I suddenly "crap" or "a joke". When your favourite crisp manufacturer comes out with a "new, even tastier" variety - does that mean that the old type is suddenly terrible, and that the company should be condemed for ever advertising it? > As someone already mentioned, MicroBlaze has an FSL interface for > hardware acceleration. It probably blows away Altera's custom > instruction. > Can you explain how it "blows away" custom instructions? I don't know what the FSL interface is, so I can't compare them myself. > > "Kenneth Land" <kland1@neuralog1.com1> wrote in message news:<10b7qg7fqd1cod1@news.supernews.com>... > > "Jon Beniston" <jon@beniston.com> wrote in message > > news:e87b9ce8.0405251505.5b6713a8@posting.google.com... > > <snip> > > > > > > You say it like it doesn't matter. Maybe it doesn't with FPGA CPUs as > > > you're obviously not concerned about price anyway ;) > > > > > > Cheers, > > > JonB > > > > Hard to imagine an embedded project without an fpga. Might as well have > > only one chip (fpga + softcore cpu) and save the board space since you're > > most likely going to require an fpga anyway. (board space == $$$, parts > > count == $$$) > > > > The reason you would want to use a softcore over hard is because it can be > > *exactly* customized to any application. Need 27 serial ports and timers? > > no problem. Need none? don't waste the pins or money. Need more > > processing power? add custom instructions/external parrallel logic or > > another softcore cpu (or 8!). > > > > I've seen hard core projects fail, but a soft core project can only fail > > from early abandonment. More/harder work can always find a solution, > > because the hardware can become anything you're willing to realize. > > > > KenArticle: 69983
Hi, actually I try to link the various object-file sections of my code in separate memory regions (using mb-gcc and a linker script, output: *.elf). Now, every memory region has 8 kB of adress space, so it is a non-contigueous memory. If i try to link, the .text section does not fit to 8kB. Is there any chance to tell the linker: hey, put the first 8kB of .text section in memory region A (the first 8kB) and the rest of it in memory region B? Regards, RuedigerArticle: 69984
Hi all, can anybody tell how autorefresh in SDRAM exactly works? suppose in SDRAM specifications it is mentioned that 64 ms, 4096 cycle refresh(15.6 us/row) what exactly it means and how we need to generate the autorefresh cycles. actually i am trying to upgrade the 512k*4*32 SDRAM(Fujitsu Make) to Micron Make 1M*4*32 SDRAM. FUJITSU specifies that 4K refresh cycles every 16ms, auto refresh (3.9 us) and micron specifies that 64 ms, 4096 cycle refresh(15.6 us/row). Did any body tried to do this kind of upgradation. we have the CPLD which controls the Fujitsu SDRAM and other interfaces.now we want to upgrade the SDRAM as i mentioned above. Anybody can help in this regard please reply to sudharr@myw.ltindia.com .i can send u the data sheets of both the SDRAMs,if you want. thanks and regards, S.RANGA REDDYArticle: 69985
in general the 64mS says that you need to complete all the 4096 cycles in 64
mS period. how you do it it is your choice (based on the application) = you
can do 4096 refresh cycles in a clock by clock (NOT real-life option) and
after these 4096 clocks go to sleep or do your algorithm until the next 64mS
starts or (another scenario) you can do some N refresh cycles together and
repeat this so 4096/N such events will take less than 64mS, etc.
as the SDRAM takes care inside for the refresh it actauly means that you
will "visit" every SDRAM line in 64 mS and this will prevent the data from
disappearing.
as for the upgrade -->
the X mS period is the MIN. as you see Fujitsu asks for 16 mS while Micron
wants 64 mS = actualy you need to do NOTHINg as what will happen with the
Micron is that it will "over-" refreshed (x4) but this odes NOT make any
damage at all ! doing the oposite (Micron --> Fujitsu) will NOT work as than
if the design is for 64 mS and the device expects 16 mS the data might
disappear (might as if you still keep accessing the SDRAM it will take
longer time for this effect).
hope this helps.
--
yours -
Arie Z.
============================================
Arie Zychlinski
R&D Consulting & Development
P.O.Box 536
Kfar-Saba 44104
ISRAEL
Mobile: 972-52-8320230
Phone: W: 972-9-7673074 H: 972-9-7658268
E-Mail: arie_zy@bezeqint.net
===========================================
"RANGA REDDY" <sudharr@myw.ltindia.com> wrote in message
news:37ba429a.0405260302.2728abcc@posting.google.com...
> Hi all,
>
> can anybody tell how autorefresh in SDRAM exactly works? suppose in
> SDRAM specifications it is mentioned that 64 ms, 4096 cycle
> refresh(15.6 us/row) what exactly it means and how we need to generate
> the autorefresh cycles.
>
> actually i am trying to upgrade the 512k*4*32 SDRAM(Fujitsu Make) to
> Micron Make 1M*4*32 SDRAM.
>
> FUJITSU specifies that 4K refresh cycles every 16ms, auto refresh (3.9
> us) and micron specifies that 64 ms, 4096 cycle refresh(15.6 us/row).
>
> Did any body tried to do this kind of upgradation. we have the CPLD
> which controls the Fujitsu SDRAM and other interfaces.now we want to
> upgrade the SDRAM as i mentioned above.
>
> Anybody can help in this regard please reply to
> sudharr@myw.ltindia.com .i can send u the data sheets of both the
> SDRAMs,if you want.
>
> thanks and regards,
>
> S.RANGA REDDY
Article: 69986
anyone can recommend / comment on the book "a SystemC Primer" by Bhasker ?
does has any other information that may be dowloaded from the SystemC .org
site ?
--
yours -
Arie Z.
============================================
Arie Zychlinski
R&D Consulting & Development
P.O.Box 536
Kfar-Saba 44104
ISRAEL
Mobile: 972-52-8320230
Phone: W: 972-9-7673074 H: 972-9-7658268
E-Mail: arie_zy@bezeqint.net
===========================================
Article: 69987On Tue, 25 May 2004 15:12:45 +0800, Student wrote: > Hi, there: > > My clock is 40MHz, but I have complicated FFT operations and other DSP > stuff. > The longest path is 25.8ns, though after I set the constraints at > 23ns...Previously it > was 27.5ns at constraints of 25ns... > > What may I do now? How far can over constraining go? The source codes are > from > other people so I can't change a lot of it. > > Besides -opt_mode Speed in XST, what else controls can I use in ISE6.1? > > Does Synplify optimize for speed? How does it compare with XST? > > Kelvin Synplify usually does a 10% better job then any other synthesis tool so it might fix your problem. You could also try ISE6.2sp2. XST is an immature tool so three are significant improvements with each release at this stage. The final thing to try is floorplanning.Article: 69988
James <james@zavoo.com> wrote in message news:<rTPsc.3570$L8.1433@fe2.columbus.rr.com>... > mikegw wrote: > > Anyone know what happed to this site? It has been off the air for a few > > days now. > > > > Mike > > > > > Try a mirror: > http://opencores.nnytech.net/projects.cgi/web/opencores/mirrors The mirror works, but site still has some links to www.opencores.org which don't :(Article: 69989
Austin Lesea <austin@xilinx.com> writes: > Hendra, > > Max II has no RAM in the logic plane, so it only seems natural that a > 2D array (which looks like RAM) would not be easily recognized. > I think the OP is referring to the Max Plus II (which I tend to abbreviate to MP2) tool, not the MaxII devices. IIRC the MP2 VHDL compiler can't do 2d arrays (and indeed many other things). Quartus probably can. > One should be able to use each LE as a FF in the array, but that is > pretty inefficient, and would chew up all resources pretty fast. > Indeed that would happen if the tools recognised the array - if you instantiate an LPM_RAM this is what will happen in devices without RAM blocks (like the old Flex 6K) <snip> -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 69990
"Hendra Gunawan" <u1000393@email.sjsu.edu> writes: > > Jakub wrote: > > > > > I am a junior FGPA designer and am planning on attending some training > > > to improve my design skills and FPGA knowledge. Can someone tell me > > > if the courses offered by Xilinx are good courses? I am looking into > > > the FPGA design flow (not VHDL classes) with courses like fundamental > > > of FPGA design, designing for performance etc etc.. > > I attended both Fundamentals of FPGA Design and Designing for Performance. > In my opinion, they are not that usefull. The classes are mostly focused on > how to use the software, clicking here and there and see how it changes. > There is no in depth tutorial on Xilinx FPGA architecture. I think they > posted some of their course material on Xilinx ftp site. Look for > "Fundamentals of FPGA Design", "Designing for Performance", and "Advanced > FPGA Implementation" keywords. Just look over it and make decision on your > own whether or not you really need to take the course. > Note that I am not trying to discredit Xilinx or anything. I think Xilinx is > a wonderfull company, their software is much better than Altera, the help > menu is very good, and their website is very well organized. I am just > dissapointed that I don't get the thing that I expected out of the class. I > expected to learn Xilinx Hardware FPGA Architecture, but instead I have just > been taught on how to use the software tool. > I can't comment on those courses, but I know we all got a lot out of the "DSP implementation techniques" course both about logic-architecture (not much about routing resources) and about doing DSP in FPGAs. Not a PC in sight - lots of paper exercises to amek you think! Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 69991
I'm still looking for help setting up my system. If anyone out there can help me I would greatly appreciated it. I've already checked Altera's website. In the readme file it says the board is still supported but I have found out how. > I have an Altera LP4 ISA interface board I'm trying to setup to use > with MAX+plus II 9.23. What device drivers do I need to install to use > this board? Will the LP6 Drivers work? > > There are also some DIP switches on it. Does anybody know what the set > or control? > > I have the pod and I'm going to try to program Altera EPM7256EGC192. > Does anybody know if there is any reason this combination of software > and hardware won't work? > > Thanks, > Derek SimmonsArticle: 69992
"Nial Stewart" <nial@nialstewartdevelopments.co.uk> wrote in message news:<40b36e96$0$4587$db0fefd9@news.zen.co.uk>... > "john jakson" <johnjakson@yahoo.com> wrote in message > news:adb3971c.0405211754.52bb304c@posting.google.com... > > > > 3) Its creators are British. > > > > > > > Perhaps I am doomed to fail on all 3 counts. > > > > Anyway I may be a US citizen before this thing gets polished and can > > deny the last rule as everything important has to seem to be invented > > or reinvented in the US- (sadly). > > > > Since my math isn't so great maybe I can deny the 2nd rule too:). > ^^^^ > > John, looks like you're most of the way there ;-) > > I still don't understand why Americans shorten mathematics > to 'math'. > > > Nial. I don't know either, but I think its because I don't ever hear the term arithmetic used in kindergarden level like we did in UK so math got pushed down to cover that and never got explained as being more serious term when they grow out of it. And where did all the u's go too:) regards johnjakson_usa_comArticle: 69993
Kenneth Land wrote: > > "Jon Beniston" <jon@beniston.com> wrote in message > news:e87b9ce8.0405251505.5b6713a8@posting.google.com... > <snip> > > > > You say it like it doesn't matter. Maybe it doesn't with FPGA CPUs as > > you're obviously not concerned about price anyway ;) > > > > Cheers, > > JonB > > Hard to imagine an embedded project without an fpga. Might as well have > only one chip (fpga + softcore cpu) and save the board space since you're > most likely going to require an fpga anyway. (board space == $$$, parts > count == $$$) > > The reason you would want to use a softcore over hard is because it can be > *exactly* customized to any application. Need 27 serial ports and timers? > no problem. Need none? don't waste the pins or money. Need more > processing power? add custom instructions/external parrallel logic or > another softcore cpu (or 8!). > > I've seen hard core projects fail, but a soft core project can only fail > from early abandonment. More/harder work can always find a solution, > because the hardware can become anything you're willing to realize. Ok, how about an 8 bit CPU with an 8 input, 10 bit ADC and a brown out detector? I think this costs less than $3 and comes in a 28 pin TSSOP or a 5 x 5 mm QFN. MCUs often have advantages since they are typically mixed signal chips, not just digital. It can be pretty hard to beat an MCU with an FPGA when you need even just a little bit of analog. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 69994
Arie Zychlinski wrote: > means that > you will "visit" every SDRAM line in 64 mS and this will prevent the > data from disappearing. And one of the many advantages of an FPGA is that if you know enough about the application to know that every row will be visited anyway you don't need to refresh at all.Article: 69995
Hi Derek, One of my colleagues said that this should work and the LP6 documentation should be helpful. - Subroto Datta Altera Corp. "Derek Simmons" <Derek_SImmons@msn.com> wrote in message news:14030831.0405260539.493a5865@posting.google.com... > I'm still looking for help setting up my system. If anyone out there > can help me I would greatly appreciated it. I've already checked > Altera's website. In the readme file it says the board is still > supported but I have found out how. > > > > I have an Altera LP4 ISA interface board I'm trying to setup to use > > with MAX+plus II 9.23. What device drivers do I need to install to use > > this board? Will the LP6 Drivers work? > > > > There are also some DIP switches on it. Does anybody know what the set > > or control? > > > > I have the pod and I'm going to try to program Altera EPM7256EGC192. > > Does anybody know if there is any reason this combination of software > > and hardware won't work? > > > > Thanks, > > Derek SimmonsArticle: 69996
In article <bf780a06.0405252226.60e2d1f0@posting.google.com>, Stifler <seannstifler69@hotmail.com> wrote: >Also, custom instuctions are probably as stupid as a window register >file. Why do you need a custom instuction so bad? I believe it's >simply hardware acceleration. There's several ways to accomplish >hardware acceleration. Altera's custom instuction can bog down your >processor Fmax. It goes right into the middle of the pipe. Why not >simply have your processor launch off a separate process while it >continues to grind away at top speed? Likewise, this is the whole BLEEPING point of having a coprocessor interface: it gives you a separate pipeline for your instructions, etc etc etc, so you can have the advantages of a "custom" extention to your instruction set, without having it in the pipeline or even necessarily in the critical path... Chimaera (a hard processor design with an in-the-pipeline reconfigurable unit for custom instructions) was, IMO, a failure compared to GARP (a hard processor design with a reconfigurable unit as a MIPS coprocessor, with its own specialized memory interfaces). Yet Chimaera was a useful failure, an incredibly valuable negative result: showing just how little one could achive with in-the-pipeline custom instructions. Especially since, for custom instructions, you are often dealing with large working sets (otherwise you don't really benefit in the first place), so having a coprocessor with its own optimized (eg, streaming, strided-streaming) memory access ports is a huge win over "in-the-pipeline" custom instructions. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 69997
Kenneth Land wrote: > "E.S." <emu@ecubics.com> wrote in message > news:GsOsc.20467$zs2.931@fe39.usenetserver.com... >>>Ever heard the term "Sour Grapes" ? >> >>Heard before, but why in this context ? > > Uh.. Because you're saying you don't want something you can't have, even > though it's of great value. (Custom Instructions with Nios (the grapes) vs. > Microblaze (no grapes) - so you say "They are probably sour anyway") OK, I got it. Thanks ;-) But I wasn't even thinking about the NIOS <--> MicroBlaze competition (?) More along the lines, how I like to expand my processors. And my software guys are trying to kill me each time we invent a new instruction ;-) CheersArticle: 69998
Kenneth Land wrote: > "Jon Beniston" <jon@beniston.com> wrote in message > news:e87b9ce8.0405251505.5b6713a8@posting.google.com... > <snip> > >>You say it like it doesn't matter. Maybe it doesn't with FPGA CPUs as >>you're obviously not concerned about price anyway ;) I don't think it is so easy to calculate. Having a chance to change "hardware" at a very late stage of a project, can save you a lot of money. BTW, how many poeple in this group are really selling millions of boards, so it make sense to cut a dollar on the chip, but spend it in software instead ? > Hard to imagine an embedded project without an fpga. Might as well have > only one chip (fpga + softcore cpu) and save the board space since you're > most likely going to require an fpga anyway. (board space == $$$, parts > count == $$$) Sitting long nights to get the tools working ? priceless ;-) > The reason you would want to use a softcore over hard is because it can be > *exactly* customized to any application. Need 27 serial ports and timers? > no problem. Need none? don't waste the pins or money. Need more > processing power? add custom instructions/external parrallel logic or > another softcore cpu (or 8!). But probably you didn't spent enough time to get the requirements/specification straight in the first place ? > I've seen hard core projects fail, but a soft core project can only fail > from early abandonment. Or delays ... > More/harder work can always find a solution, > because the hardware can become anything you're willing to realize. But you need a boss with a good sense of humour ;-) cheersArticle: 69999
ALuPin wrote: > "Oscar Garnica" <ogarnica@dacya.ucm.es> wrote in message news:<c8vtvf$6$1@thule.sim.ucm.es>... >> >>We have tried to read/write data from/to SRAM (AS7C4096) using a tri-state >>buffer to drive data bus but we are not being able to manage this task. >>Whenever we try to read data from the memory we obtain the value 0x0000 >>although the memory word has been loaded with a different pattern. >>Similarly, when we write data the final value in the memory word is 0x0000 >>regardless of the value we drive into the data bus. >> >>Has anybody any idea about this? What are we doing wrong? > > > Have a closer look at the control signals OE_N, WE_N, CS_N. > Is the sram address stable before these signals are asserted for write cycle? Oscar, with that level of detail (= lack thereof) we can't help much. In my SRAM controller (Cyclone hooked up to two IDT71V416) I take four (10ns) cycles for write: - one to turn of the output enable (OE_N = 0), - one to load the address and data, and open the output drivers, - one to write the data (WE_N = 1) - one to turn it back off (WE_N = 0) For writes after write in a row, the first cycle can be shaved off, but I haven't been able to bring the write process down under three cycles in spite of the datasheet's claimed 0 tWR. I don't know if that's normal (this is with the Nios development board, Cyclone edition). I'm more concerned about the maximum read performance. Reading the data sheet, the positive (4 ns) tOH made me think that I could sustain a read every cycle (the tRC is 10ns as is my cycle time), but my testing has given inconsistent results. Question to the experts: Is this (simplified example) safe? assign fse_a = read_addr; always @(posedge clk) begin read_data <= fse_d; // SRAM data read_addr <= read_addr + 4; end (Obviously the read_data would correspond to the previous cycle read_addr). Thanks, Tommy
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z