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I meant to say that Virtex-IIProX has 10+gigabit/sec dedicated transceivers. There is and will be no SpartanProX. Sorry for the typo :-( Peter Alfke > From: Peter Alfke <peter@xilinx.com> > Organization: Xilinx,Inc > Newsgroups: comp.arch.fpga > Date: Thu, 22 Apr 2004 16:50:11 -0700 > Subject: Re: Time domain/Delay line UARTs - high speeds > > Let me describe today's and tomorrow's capabilities. > Inside the FPGS, the general-purpose routing structure makes it difficult to > clock GP logic much faster than 500 MHz, but dedicated functions can be > pushed faster, perhaps to 800 MHz. On-chip clock delay can be completely > eliminated, and global clock skew can (hopefully) be kept below 150 ps. > Clock phase shifting can have <30 ps resolution. > When saving pc-board area and interconnect pins is important, dedicated > transceivers can run (today in SpartanProX) at slightly over 10 > gigabits/second (100 picosecond per bit). > These are all fairly realistic parameters for aggressive designs. > > Just my personal observations, not an official Xilinx position. > Peter Alfke > >> From: Jim Granville <no.spam@designtools.co.nz> >> Organization: TelstraClear >> Newsgroups: comp.arch.fpga >> Date: Fri, 23 Apr 2004 10:48:59 +1200 >> Subject: Time domain/Delay line UARTs - high speeds >> >> Jim Granville wrote: [Old topic Issues on Shift Register in a >> Clockless UART ] >>> That design can be done with a delay line ( which needs >> baud-precision - not really a common building block...), >> plus it's not clear how it would manage sync in packed streaming data... >>> >> >> ( I've changed the topic, as that thread was looking like someone's >> homework.) >> >> I think there is scope to study more what can, and can't be done with >> delay lines. >> FPGAs cannot clock above 1GHz, but they CAN resolve time to >> ~140ps regions, in some cases ( see Peter A's posts ). >> >> Taking the example above, delay line bit sampling is easy enough, but >> the byte sync is rather harder. I think the only solution is >> a longer delay line, and wider stop bits - so the data is framed >> as 8(+) Stop bits, 1 start Bit, 8 data bits... >> (8 bits is illustrative only) >> >> A capture is triggered only when the delay line taps show >> 8 stop bits, and one start - otherwise the data 'leaving' the delay >> line can trigger false captures. >> >> Txmit would be via a register chain/MUX tree, that loads/holds >> until flipped from 'wait' to 'delaylinego', then data would stream >> out. Pacing would be done from a slower clock, but the time >> domain precision of this would be delay element sized (~140ps) >> This assumes, of course, that access to this detail is possible >> in the FPGA hardware :) >> >> All up, data rates in the GigaBaud region would appear do-able. >> >> There are benefits to thinking more in time-domain, rather >> than simple MHz - once the ideas are there, the tools and fabric >> can follow. >> >> -jg >> >Article: 68976
Please visit my website http://209.11.152.57/galois/index.jsp if you need a galois field multiplier hardware. The work is based on equation for galois field multiplication that I developed as an independent researcher. The website restricts you upto GF(2^16) only, but the underlying engine does not have any such restriction. Email me for any questions.Article: 68977
On Fri, 23 Apr 2004 15:33:07 +0100, Nial Stewart wrote: > > "AndyAtHome" <fpgadev@yahoo.com> wrote in message > news:29ab33c4.0404220812.3fe7b63@posting.google.com... >> Dear All, >> >> I'm just about to purchase Xilinx ISE BaseX plus MXE for 1,295 USD. >> Having downloaded the free edition I have to say I'm less than >> impressed with the general user friendliness - no keyboard shortcuts, >> no code completion, etc. > > As Jon says, don't rely on the P+R tools for design entry, there > are much better text editors about (I too use Textpad). Both Emacs and Xemacs are available on every platform. There is an excellent Verilog mode as well as VHDL mode that will do everything that you ever dreamed you needed. Don't waste your time using primitive editors.Article: 68978
Emacs + Icarus Verilog + Quartus II does the trick for me quite nicely and all is for free. The _only_ thing I miss from the paid-for Quartus is the FPGA Editor and more device support. I spend 95% of the time in Emacs and Icarus Verilog, so I don't care much about the remaining 5% as long as it works (and Quartus II is very stable). When I used Xilinx WebPACK I even had scripted the P&R and programming tools so I would never leave Emacs. I have yet to take the time to figure out how to do that with Quartus. I'm curious, what are you really expecting better for your $2k? A better editor? Tommy AndyAtHome wrote: > Dear All, > > I'm just about to purchase Xilinx ISE BaseX plus MXE for 1,295 USD. > Having downloaded the free edition I have to say I'm less than > impressed with the general user friendliness - no keyboard shortcuts, > no code completion, etc. > > Is it the case that in terms of commercial tools chains ISE plus > Modelsim is the only thing in the market under $2,000? > > It would be great to hear from any other Xilinx developer's that have > found an alternative under 2,000 USD. > > Thanks, > > Andy.Article: 68979
user@domain.invalid wrote: > > Steven wrote: > > Hi, newgrouper, > > > > does anyone know what dqm does ? The specification of micron is > > vague. What mask function does it mean ? > > > > Thanks > > > > Steven. > > Hi > > My interpretation is that the mask means that you can choose to not overwrite parts of existing data when you do a write to a certain address. > > A little example: > If you have a data width of 64 bits and have 8 bits of dqm:s, and have a data architecture that use byte-variables. > Then you can store 8 variables on one address and change one without destroy the others by using dqm as byte-enable. > > If I'm wrong I'm sure someone will correct me. That is part of it. In essence the DQM is a byte enable. On write it will allow or prevent the write on a byte by byte basis. On read, IIRC, it will enable the data output or tristate the output on byte by byte basis. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 68980
On Fri, 23 Apr 2004 13:26:57 -0400, "B. Joshua Rosen" <bjrosen@polybus.com> wrote: >Both Emacs and Xemacs are available on every platform. There is an >excellent Verilog mode as well as VHDL mode that will do everything that >you ever dreamed you needed. Don't waste your time using primitive editors. And there's another option: some of the features of Verilog mode for emacs--automatic argument lists, automatic module instantiation--can be run in batch mode. I invoke emacs in batch mode from inside UltraEdit (world's best text editor, IMHO) and never have to look at an emacs screen or struggle with the funky emacs command sequences. Very nice. Bob Perlman Cambrian Design WorksArticle: 68981
Hi, I used to do some thing similar, but then I figured out yet another easier way (atleast I find so). I refernce to a file named say "image_data.txt" inside my TB. Using a script around my simulator, I use UNIX links to simulate multiple images, infact you could do some thing like: ln -s image_0.txt image_data.txt run # End of 1 sim with image_0 reset rm -f image_data.txt ln -s image_1.txt image_data.txt run # Second simulation with image 1!! I did this using NCSIM - FYI. HTH, Ajeetha, http://www.noveldv.com Co-Author: Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition. "jtw" <wrightjt @hotmail.invalid> wrote in message news:<h21ic.54437$or3.2341@newssvr25.news.prodigy.com>... > If you need to open an arbitrary file (like I often want to do), define it > as a generic, with a default value. When you call the simulator (I've > worked with Modelsim doing this), provide the generic as part of the call. > E.g., vsim tb_config -ggeneric1=generic1value ... (other options.) > > Then you can set up a script (or batch file) with whatever value you need > for the generic-- or just manually type in every time you run it. > > Jason >Article: 68982
I'm running into a problem trying to use the output registers
in a Xilinx IOB and am hoping someone has seen/solved this
before.
An original verion of my code worked just fine and XST pushed
the registers into the IOB:
//synthesis attribute IOB of sram0_a is "TRUE"
always @(posedge clk_mem)
begin
sram0_a[19:1] <= `Tdo do_wr ? wr_addr[19:1] : rd_addr[19:1];
sram0_a[0] <= `Tdo 1'b0;
end
We then added a second bank of sram and duplicated the sram
address pins:
//synthesis attribute IOB of sram0_a is "TRUE"
//synthesis attribute IOB of sram1_a is "TRUE"
wire [19:1] sram_a;
assign sram_a = do_wr ? wr_addr[19:1] : rd_addr[19:1];
always @(posedge clk_mem)
begin
sram0_a[19:1] <= `Tdo sram_a;
sram1_a[19:1] <= `Tdo sram_a;
sram0_a[0] <= `Tdo 1'b0;
sram1_a[0] <= `Tdo 1'b0;
end
Now XST says:
Register <sram0_a<1>> equivalent to <sram1_a<1>> has been removed
and the IOB output regs are no longer used.
I've played around with the "keep" and "Save Net Flag" constraints
with no success.
Any suggestions?
Thanks!
John Providenza
Article: 68983Hi, I am running the EDK 3.2 and using a Virtex II XC2V2000 FPGA. The C program I am compiling on the Microblaze seems to need more space on the ILMB and DLMB collectively. Both will fit independently into the current 0x00000000 to 0x0000FFFF configuration for the LMB_BRAM_if_cntlr but not together. Any ideas on how I can increase either the ILMB without decreasing the DLMB? I have looked into making one BRAM be the ILMB and one BRAM be the DLMB. But it doesn't seem to like this configuration. Thanks, JosephArticle: 68984
John Providenza wrote:
> I'm running into a problem trying to use the output registers
> in a Xilinx IOB and am hoping someone has seen/solved this
> before.
>
> An original verion of my code worked just fine and XST pushed
> the registers into the IOB:
> //synthesis attribute IOB of sram0_a is "TRUE"
> always @(posedge clk_mem)
> begin
> sram0_a[19:1] <= `Tdo do_wr ? wr_addr[19:1] : rd_addr[19:1];
> sram0_a[0] <= `Tdo 1'b0;
> end
>
> We then added a second bank of sram and duplicated the sram
> address pins:
> //synthesis attribute IOB of sram0_a is "TRUE"
> //synthesis attribute IOB of sram1_a is "TRUE"
> wire [19:1] sram_a;
> assign sram_a = do_wr ? wr_addr[19:1] : rd_addr[19:1];
>
> always @(posedge clk_mem)
> begin
> sram0_a[19:1] <= `Tdo sram_a;
> sram1_a[19:1] <= `Tdo sram_a;
> sram0_a[0] <= `Tdo 1'b0;
> sram1_a[0] <= `Tdo 1'b0;
> end
>
> Now XST says:
> Register <sram0_a<1>> equivalent to <sram1_a<1>> has been removed
> and the IOB output regs are no longer used.
>
> I've played around with the "keep" and "Save Net Flag" constraints
> with no success.
>
> Any suggestions?
Howdy John,
I can't help you with what might be causing the behavior, but until you
figure that part out, perhaps you can work around it by putting a reset
or enable signal on flops for one of the address buses but not the
other. Of course, the reset or enable has to be tied to something that
the tool thinks could dynamically change (even _you_ know it doesn't
change) so that it doesn't optimize out!
Have fun,
Marc
Article: 68985I will slip in an 'oops' and a 'thanks' here. The input jitter generality is clearly wrong and contentious. This issue brings up an application issue that has come up a number of times for me. I've set up a number of clock dividers using various techniques like clock-puncturing and numerator-accumulation/denominator-thresholding, but of course the output clock jitter varies directly with the input clock width. What kind of thing could accept an extremely jittery clock output like that described above, and produce a nice clean clock with the same average frequency and substantially reduced jitter? Best regards, Dwayne Surdu-MillerArticle: 68986
Rene Tschaggelar wrote: > Nial Stewart wrote: > >> This is off topic for the news group, but I know there >> is a vast array of experience here, hopefully someone >> can help. >> >> I've an application where I need a 20MHz clock which can >> be adjusted by +/- 2% (rough requirements, the client doesn't >> actually know what's required). The timebase of frequency >> adjustments isn't critical. I haven't been given any >> jitter specs. >> >> This has to be incorporated in a working prototype in >> 3 weeks so the solution must be simple and fairly >> stable. >> >> The VCXOs that I've found are adjustable by at most >> 200ppm, so this isn't an option. >> >> I'm thinking of using a 74LS624 with a single pin DAC >> driving the frequency control input. The data sheet >> specifies 20MHz as the maximum output frequency, but >> the performance graphs show outputs at up to 30MHz. >> >> >> The prototype board I'm using has an Altera Cyclone >> (EP1C6). >> >> Ideal requirements... >> 20MHz +/- 2%, easily adjustable. >> Simple (single device ?) >> Operates from 3.3V supply >> Can be sourced from distributor in a couple of days. >> > > LTC6900, LTC6903 from linear technology Also, Maxim have VCO & clock chips, and Cypress have a range of programmable clock generators. Even a Cygnal uC will come close : They have an internal current injection OSC, with a 8 bit DAC, that is nominally 24MHz, but trims 16-24 MHz IIRC. You can also build one using a LC osc and a varicap :) -jgArticle: 68987
> From: Dwayne Surdu-Miller <miller@SEDsystems.nospam.ca> > Organization: Posted via Supernews, http://www.supernews.com > Newsgroups: comp.arch.fpga > Date: Fri, 23 Apr 2004 14:29:01 -0600 > Subject: Re: PLL and DLL > > I will slip in an 'oops' and a 'thanks' here. The input jitter > generality is clearly wrong and contentious. > > This issue brings up an application issue that has come up a number of > times for me. I've set up a number of clock dividers using various > techniques like clock-puncturing and > numerator-accumulation/denominator-thresholding, but of course the > output clock jitter varies directly with the input clock width. > > What kind of thing could accept an extremely jittery clock output like > that described above, and produce a nice clean clock with the same > average frequency and substantially reduced jitter? > > Best regards, > Dwayne Surdu-Miller This can be done with a PLL (or a DLL that behaves like a PLL) Between phase detector and the variable oscillator you need a low-pass filter. This filter must suppress all the results of incoming jitter, but must still make the output track the average input frequency change. It must pass dc, but must suppress anything above a given frequency. Peter AlfkeArticle: 68988
Perhaps u could declare two independent always blocks. I believe
the optimization is occuring because it is defined in the
same always block.
always @(posedge clk_mem)
begin
sram0_a[19:1] <= `Tdo sram_a;
sram0_a[0] <= `Tdo 1'b0;
end
always @(posedge clk_mem)
begin
sram1_a[19:1] <= `Tdo sram_a;
sram1_a[0] <= `Tdo 1'b0;
end
John Providenza wrote:
> I'm running into a problem trying to use the output registers
> in a Xilinx IOB and am hoping someone has seen/solved this
> before.
>
> An original verion of my code worked just fine and XST pushed
> the registers into the IOB:
> //synthesis attribute IOB of sram0_a is "TRUE"
> always @(posedge clk_mem)
> begin
> sram0_a[19:1] <= `Tdo do_wr ? wr_addr[19:1] : rd_addr[19:1];
> sram0_a[0] <= `Tdo 1'b0;
> end
>
> We then added a second bank of sram and duplicated the sram
> address pins:
> //synthesis attribute IOB of sram0_a is "TRUE"
> //synthesis attribute IOB of sram1_a is "TRUE"
> wire [19:1] sram_a;
> assign sram_a = do_wr ? wr_addr[19:1] : rd_addr[19:1];
>
> always @(posedge clk_mem)
> begin
> sram0_a[19:1] <= `Tdo sram_a;
> sram1_a[19:1] <= `Tdo sram_a;
> sram0_a[0] <= `Tdo 1'b0;
> sram1_a[0] <= `Tdo 1'b0;
> end
>
> Now XST says:
> Register <sram0_a<1>> equivalent to <sram1_a<1>> has been removed
> and the IOB output regs are no longer used.
>
> I've played around with the "keep" and "Save Net Flag" constraints
> with no success.
>
> Any suggestions?
>
> Thanks!
>
> John Providenza
--
/ 7\'7 Paulo Dutra (paulo.dutra@xilinx.com)
\ \ ` Xilinx hotline@xilinx.com
/ / 2100 Logic Drive http://www.xilinx.com
\_\/.\ San Jose, California 95124-3450 USA
Article: 68989The question isone of adjustable range (2%) vs. inherent stability. A VXCO gives you very good stability, but limited range (as a result of the high Q value that is responsible for its stability) Resistor-based oscillators, like the ones from Linear Technology, offer a wide range, but are much more affected by Vcc,temperature etc. If you want both stability and wide range, you are in for complex circuitry, like DDS phase accumulators etc, Max acceptable jitter then becomes the issue... Peter AlfkeArticle: 68990
Right on. Thanks for the information Sean. You got it to work with EDK 3.2. I got it to work for EDK6.2 with help from paulo@xilinx.com Here was my final comment to Xilinx on the subject: --------------------------- OK. I did the following: 1. changed the microblaze instance name to "xlxi_1" in top.sch 2. removed system.bmm from the sub-module group(XPS placed it there) 3. added system_stub.bmm associate with Top.sch 4. added "xlxi_1" to the BRAM heirarchy path in each BRAM entry of system_stub.bmm 5. selected Top.sch as top design and ran implementation. 6. finally got a system_stub_bd.bmm with placements in the XPS implementation folder! Well, that was a lot of extra work and I wished the process was documented better. The issue with XPS not exporting the right bmm file with the correct top level file is still there, but I know what do do now. Thank you for your time. I believe the issue can be "closed" now. Morris. -------------------------- Summary: In exporting to Project Navigator, XPS does not know what you will call your Microblaze sub-module instantiated in the top design. Hence it can't put the hierarchy path in the BMM file. Then XPS does two things wrong: it associates the wrong (system.bmm) file with the sub-module instead of the specified top level design. Once you have the instance name (you can assign this) of the sub-module in the top design, then you have to find system_stub.bmm and put the name of the sub-module instance on every text line in the BMM file where there is a BRAM specified. Then you have REMOVE the BMM file associated with the sub-module (XPS did this automatically) and ADD the system_stub.bmm (with your manually-added hierarchy paths) to the top design. Interesting notes: I believe I received two replies from Germany. Xilinx claims to have sold 10,000 copies of EDK. I did not see this issue addressed in the Xilinx answer database. I ran into this problem within 5 days of my evaluation of EDK. A Memec FAE told me to just work in the XPS environment. Morris "Sean Durkin" <smd@despammed.com> wrote in message news:c685g2$912lu$1@uni-berlin.de... > Morris Ho wrote: > > > Tools used: EDK and ISE 6.2 on Win2000. I compiled the Memec HelloWorld > > project and successfully ran it on their Spartan IIELC reference design > > board. > > [...snip...] > > I found by extensive poking around that the Project Navigator does NOT > > automatically update the BMM file with the newly placed locations of BRAM > > that holds the Microblaze program. > > I'm still using EDK3.2, but have had similar problems and maybe that > will help you: > > When you set the hierarchy to "sub-module" in XPS, you have to give it > the name of the top instance. This name is used in the original BMM > created by XPS to tell bitgen the complete path to the BRAMs. XPS also > creates an example top-level-VHDL-file that is supposed to show you how > to declare and instantiate the module with the MicroBlaze in it > (something like "system_stub.vhd"). When you export to "Project > Navigator", a new project is created with system_stub.vhd as the > top-level-design file, but neither the UCF nor the BMM are added to the > project sources, you have to do that manually (theoretically, ngdbuild > should find the BMM automatically, but that never works for me). If you > don't add the BMM, it is not updated (you normally get a new BMM like > system_bd.bmm WITH the information on the placement, not an updated > BMM), and then you get exactly the problems you mentioned. > > But if you do add the BMM as a source to the project, it still doesn't > work quite right: In EDK3.2 the top instance name you enter in the > project settings is *NOT* transferred to the VHD-file. I.e. if you do > copy&paste from system_stub.vhd, the instance name in your top-level > does not match the instance name in the BMM file, hence "ngdbuild" just > gives you an error about not being able to find the BRAMs and aborts. > Same should apply if you do it with schematics. > > So, this might help you: > > a) add the BMM as a source to your project in Project Navigator > b) make sure the instance name for the module with the MicroBlaze > matches the name you specified in EDK before exporting. I've never > worked with schematics, but I'm sure you can specify the instance name > when you add a component. > > What you should get in the end is not an updated BMM, but instead a > completely new one with "_bd" appended to the name, and that is the one > you have to import in XPS. > > cu, > SeanArticle: 68991
I found the answer after more dinking around. You need to use the option: //synthesis attribute equivalent_register_removal of sram0_a is no; //synthesis attribute equivalent_register_removal of sram1_a is no; John P johnp3+nospam@probo.com (John Providenza) wrote in message news:<349ef8f4.0404231052.21feda24@posting.google.com>... > I'm running into a problem trying to use the output registers > in a Xilinx IOB and am hoping someone has seen/solved this > before. > > An original verion of my code worked just fine and XST pushed > the registers into the IOB: > //synthesis attribute IOB of sram0_a is "TRUE" > always @(posedge clk_mem) > begin > sram0_a[19:1] <= `Tdo do_wr ? wr_addr[19:1] : rd_addr[19:1]; > sram0_a[0] <= `Tdo 1'b0; > end > > We then added a second bank of sram and duplicated the sram > address pins: > //synthesis attribute IOB of sram0_a is "TRUE" > //synthesis attribute IOB of sram1_a is "TRUE" > wire [19:1] sram_a; > assign sram_a = do_wr ? wr_addr[19:1] : rd_addr[19:1]; > > always @(posedge clk_mem) > begin > sram0_a[19:1] <= `Tdo sram_a; > sram1_a[19:1] <= `Tdo sram_a; > sram0_a[0] <= `Tdo 1'b0; > sram1_a[0] <= `Tdo 1'b0; > end > > Now XST says: > Register <sram0_a<1>> equivalent to <sram1_a<1>> has been removed > and the IOB output regs are no longer used. > > I've played around with the "keep" and "Save Net Flag" constraints > with no success. > > Any suggestions? > > Thanks! > > John ProvidenzaArticle: 68992
> If I remember this right, originally there were Gate Arrays, > which were actually closer to transistor arrays. Everything needed > to make logic circuits except the metal layer. (Maybe only one > or two at the time.) NRE costs are lower than standard cell > or custom logic, though usable density was a little lower, too. > > Then along came FPGA's, so the original ones have been renamed? > > -- glen I have run across the term "structured asic" these days but never really found a definition of it. Is structured asic simply what we used to call a gate array (fixed cell size cusomization of metal only)? -JeffArticle: 68993
Nial, Got a Xilinx with a DCM spare? Try this crap idea. Frequency in = Fin From N= 20 to 32, use a DCM to give you Fout = (N/(N-1))*Fin Gives you a range of multipliers from 1.052 to 1.032 in 12 steps Scale the frequencies accordingly to fit the DCM specs, i.e. use CLKFX at (say) double your 20MHz. Of course, this gets a lot harder to do on the fly, but might work for compile time. Do I win £5? Cheers mate, Syms. "Nial Stewart" <nial@nialstewartdevelopments.co.uk> wrote in message news:40892522$0$31708$fa0fcedb@lovejoy.zen.co.uk... > I've an application where I need a 20MHz clock which can > be adjusted by +/- 2% (rough requirements, the client doesn't > actually know what's required). The timebase of frequency > adjustments isn't critical. I haven't been given any > jitter specs. > > Thanks for any ideas, > > > Nial Stewart > > >Article: 68994
Peter Alfke wrote: > The question isone of adjustable range (2%) vs. inherent stability. > A VXCO gives you very good stability, but limited range (as a result of the > high Q value that is responsible for its stability) > > Resistor-based oscillators, like the ones from Linear Technology, offer a > wide range, but are much more affected by Vcc,temperature etc. > > If you want both stability and wide range, you are in for complex circuitry, > like DDS phase accumulators etc, Max acceptable jitter then becomes the > issue... Or something with a 'Medium Q' - the pull-ability/Stability trade off of an OSC is determined by the Q, and there are other resonance solutions with intermediate Q's. Inductors can come in a range of Q's, I thing the highest are silver plated helical resonators, and SAW resonators can be made with moderate Q's... -jgArticle: 68995
Hi,
Does it mean in MPGA the program process can be done only once,
and it can only done on the foundry side?
sincerely
-------------
Kuan Zhou
ECSE department
On Thu, 22 Apr 2004, Peter Alfke wrote:
> A mask-programmable gate array uses one (or more) metal mask in the IC
> manufacturing process, to achieve the intended functionality.
>
> In an FPGA, the user programs a standard off-the shelf chip, either by
> loading a bitstream into latches, or into Flash cells, or by programming
> antifuses.
> The manufacturer just provides software support.
> Peter Alfke
>
> > From: Kuan Zhou <zhouk@rpi.edu>
> > Organization: Rensselaer Polytechnic Institute, Troy NY, USA
> > Newsgroups: comp.arch.fpga
> > Date: Thu, 22 Apr 2004 17:39:53 -0400
> > Subject: What is MPGA?
> >
> > Hi,
> > I am wondering what's the difference between MPGA and FPGA?
> > MPGA is Mask Programmed Gate Array. What does Mask mean here?
> >
> >
> >
> > sincerely
> > -------------
> > Kuan Zhou
> > ECSE department
> >
> >
>
>
>
Article: 68996> Hi, > Does it mean in MPGA the program process can be done only once, > and it can only done on the foundry side? Yes, and that's why FPGAs have become so popular. The user can make the change, and (except for antifuse FPGAs) the chip can be reprogrammed an unlimited number of times. Peter Alfke > >Article: 68997
Jeff Cunningham wrote: > >> If I remember this right, originally there were Gate Arrays, >> which were actually closer to transistor arrays. Everything needed >> to make logic circuits except the metal layer. (Maybe only one >> or two at the time.) NRE costs are lower than standard cell >> or custom logic, though usable density was a little lower, too. >> >> Then along came FPGA's, so the original ones have been renamed? > >> -- glen > > > > I have run across the term "structured asic" these days but never really > found a definition of it. Is structured asic simply what we used to call > a gate array (fixed cell size cusomization of metal only)? A structured ASIC requires only a subset of masks to customize. You might have two metal layers and 1 or two via layers for customization. This lowers NRE charges and improves turn around time. Equally important, structured ASICs take care of power distribution, clock distribution, test, and signal integrity issues via a combination of architecture and tools. There is also a lot of focus on accuracy of pre-handoff timing prediction based on placement so that the handoff is in one direction only. From a design tasks point of view it it similar to an FPGA. You obviously lose reprogramability, so if you like debugging live hardware, you will want to use one or more FPGAs to prototype. > > -Jeff >Article: 68998
Austin is right.. you need to contact them.. and any existing design in is probably of little consequence as parts evolve so quickly that its like the space shuttle.. all 1970's design and 30 years out of date :-) There are so many issues involved (I had a look for my company once) that a lot of it is suck it and see... start with the specs. Find out which of the international specs (e.g. EN60950, ETSI, UL etc) you are designing to. Develop the concepts ... psu ... grounding etc. Work out what you want to do and how big an FPGA is required... do you want / need redundancy? Redundancy should have two different designers working in isolation to be truly redundant... do you need in circuit programming? Resets , Special IO etc... then contact suppliers.... they can be very helpful if you have lots of ideas... (and if you don't too) but you have to know what questions to ask first. Just the voltage tolerance on the PSU itself can be a design challenge. Simon "Austin Lesea" <austin@xilinx.com> wrote in message news:c6bbb4$5691@cliff.xsj.xilinx.com... > Jacek, > > Yes we have FPGAs that have been used in railway equipment. > > The problem is the sometimes close to ten year qualification process* > for railway equipment, which means by the time it is qualified for use, > the parts are well into their obsolesence. > > If you have such an application, you should contact a Xilinx FAE, and > discuss the best choice of product with them (one that we expect will be > around for another > 20 years like the 2K has been, and the 3K will have > been). > > As always, if any of our products are used in an application where human > life despends on the perfect functioning, see the very serious legal > stuff at: > > http://www.xilinx.com/legal.htm > > For example, we heard that a manufacturer wants to use an FPGA in a > nuclear reactor control system. That certainly gets our attention, as > we insisted that the design be done in such a way that is consistent > with the application (ie fully TMR, dual redundant, hot standby, etc etc > etc). > > *(based on what I've heard about a certain railway equipment supplier) > > Austin > > Jacek Mocki wrote: > > Does anyone know some examples of using CPLD or FPGA devices in railways > > equipment? > > > > Regards > > > > JacekArticle: 68999
ENTITY EX_TOP IS
generic (
outfilep_string : string :="results/CDAC_OUT.txt";
inpfilen_string : string :="data/CDAC_IN.txt"
);
PORT(
AVDD : IN real;
AVDD_REF : IN real;
AVSS : IN real;
AVSS_REF : IN real;
--input port list
CDAC_OUTN : OUT real:= 0.0;
CDAC_OUTP : OUT real:= 0.0
);
end;
The idea is to make the file as generic(here i have a default value
for the files). Then during instantiation you can change the name of
the file as per your requirement. By this the idea is to have multiple
testcases which actually feed different input data and dump out
different output files.
I hope this helps
Best Regards,
Sajan.
"paris" <273986malaka@email.it> wrote in message news:<c64kuc$ut8$1@avanie.enst.fr>...
> hi guys,
>
> im having some trouble with reading from a file, actually the thing is the
> opening part.
> the problem is that i "dont" know the name of the file to read before
> compiling, that is because i've a "configuration" file where i give
> commands, one of them being the name of the "input" file.
>
> i know i could use a function, but that only works when i've a small amount
> of data to read, cause otherwise, storing a HUGE array slows down the
> simulation, without saying that modelsim tells me that i has not enough
> memory and will start paging to disk and after a while it says that i got
> completely out of memory.
>
> Simulation works perfect if i read one line (of the input file) at the time,
> but that means that the filename has to be written on the code (at least
> that's how i've been doing, by using ' file fp : TEXT is in "input.dat"; ')
>
> now i need to open an arbitrary file, so i tried "file_open(fp,
> filenameString, READ_MODE);" the problem is that somehow it doesnt work, as
> it seems that if i open the file in one process (i have to open the file
> just once and read it till the end of the file at every rising_edge(clk), so
> that's two processes). It doesnt work cause it seems that the file is
> "closed" outside the process it was opened (i think i even read about that
> issue).
>
> Also i cant find "file_open" declaration.
>
> i also tried with a process like this: (im at home now, so i dont have the
> real sources, but i cant sleep so im writing to ask for help :) please)
>
> process
> begin
>
> if (filenameString /= nothing) then
> file_open(fp, filenameString, READ_MODE);
>
> while (not endfile(fp)) loop
> wait until rising_edge(clk);
> read(fp, data);
> etc, etc
> end loop;
> file_close(fp);
> end if;
> end process;
>
> that didnt work either, im not sure if it was because of the file_open part
> (i also did a check on the opening, it was succesful) or because the process
> get in an infinite loop, modelsim just stop responding (i think that endfile
> might return false if the file is not open, giving rise to the infinite
> loop, but the loop would at least be "waiting" for "clk" and it would
> actually read the data, but that doesnt happen). The file might get closed
> once "out" the process (like when another process gets executed) or
> something, i have no clue...
>
> do any of you knows or have faced already this kind of situation? namely,
> reading a file whose name's specified after compilation (by another file)
> line by line (that is, not using a function to read a whole chunk of data
> and storing it in an array)
>
> any comments will be appreciated, thanks
>
>
>
> Paris
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