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A good description of what static timing analysis covers, and its implementation and use in the Quartus II tools for Timing verification is provided in the Timing Analysis section os the Quartus II handbook. This is available at: http://www.altera.com/literature/hb/qts/qts_qii53004.pdf A lot of the analysis topics are generic and should apply to other tools. - Subroto Datta Altera Corp. "K PRASAD" <prasadkdnvs@rediffmail.com> wrote in message news:22f10f27.0404090246.30bb0130@posting.google.com... > hi > > Can any body explain me abt the static timing analysis > clearly what is the inndustry standard tools for that > what is the input to STA tool and what is the output. > > thank u > > regards > prasadArticle: 68626
Open Source synthesizable Arm vhdl model: For those that are interested: We have allocated a Opencores Project at: http://www.opencores.org/projects.cgi/web/core_arm/overview The source can be checked out via CVS or snapshots. Meanwhile on sourceforge you can browse them too. Vhdl files are annotated and nice to read. http://skdec.sourceforge.net/build_html/vhdl/index.htm Slowly but shurely we aproach a working verion. Indeed very slowly.Article: 68627
Hi Would anybody be willing to compile old ispDS (.ldf/.lif) files for a Lattice 1016 CPLD to a 1016E device (ending up with a PLD)? I do not have software that can do this, nor can I afford it (being a student). The input files can be found at http://no-way.org/~batronix/pcla_pld.zip. Thank you very much & nice evening Flavio Curti -- http://no-way.org/~fcu/ Mach mit bei der Community-Bibliothek - In Zuerich/CH http://zurich.communitybooks.org/ - Worldwide http://dlpdev.theps.net/ListOfExistingDlpNodesArticle: 68628
On Fri, 9 Apr 2004 21:59:49 -0400 (EDT), Matthew E Rosenthal <mer2@andrew.cmu.edu> wrote:
>I am using a memec 2Vp20 board and I want to know which LOC constraint i
>should use to be able to use rocket IO ports #6 and 7 or MGT # 19 and 21.
>I have looked around and been unable to find any documents correlating
>these port numbers or MGT numbers to actual LOC style constraint
>any help would be appreciated
>
>thanks
>
>Matt
The way I answer these type of questions is to run the FPGA editor,
on an empty design in the appropriate chip. This can also tell you
which CLBs are closest to which IOBs, the real order of IOBs (which
may not be obvious in BGA packages). And clock buffer placement,
which can be pretty important due to the arcane restrictions.
On the bottom edge of the die (looking at the die, which is the only
view that the editor gives), going left to right, the GT locations are
GT_X0Y0, between CLB slice column 15 and 16 (A BRAM column)
RXP=AP27, RNX=AP26, TXP=AP28, TXN=AP29
GT_X1Y0, between CLB slice column 39 and 40 (A BRAM column)
RXP=AP19, RNX=AP18, TXP=AP20, TXN=AP21
GT_X2Y0, between CLB slice column 51 and 52 (A BRAM column)
RXP=AP15, RNX=AP14, TXP=AP16, TXN=AP17
GT_X3Y0, between CLB slice column 75 and 76 (A BRAM column)
RXP=AP7, RNX=AP6, TXP=AP8, TXN=AP9
Along the top, from left to right
GT_X0Y1, between CLB slice column 15 and 16 (A BRAM column)
RXP=A27, RNX=A26, TXP=A28, TXN=A29
GT_X1Y1, between CLB slice column 39 and 40 (A BRAM column)
RXP=A19, RNX=A18, TXP=A20, TXN=A21
GT_X2Y1, between CLB slice column 51 and 52 (A BRAM column)
RXP=A15, RNX=A14, TXP=A16, TXN=A17
GT_X3Y1, between CLB slice column 75 and 76 (A BRAM column)
RXP=A7, RNX=A6, TXP=A8, TXN=A9
Pin numbers are for the FF1152 ball package
I assume that the Port/MGT numbers are something unique to the memec
board, so you will need to look at the schematics to finish resolving
this.
Philip Freidin
Philip Freidin
Fliptronics
Article: 68629
Hi All FPGA Gurus,
Can someone point me to verilog source to build
8bit x 16K Single Port Block Internal Ram to be used in integration
and testing of Openrisc soc on Spartan 3 LC board.
I am using Xilinx Webpack 6.2, so Core generator is
not an option.
Thanks in advance,
Regards,
AJ
Article: 68630Hi Magnus, strange application but anyhow: I guess, when I look at ieee802.3ae appendix 44a figure 44a-1 the "sync header bits" were prepended every 64 scrambled bits, by the way a great way to synchronize via barrel shifter. I think if you don´t want that behavior search for a switch in the xilinx manual to switch of sync header generation, or scramble by yourself. (Do you only rely on the balancing character of the scrambler polynom?) kind regards, thomas "Magnus Danielson" <magda@netinsight.net> schrieb im Newsbeitrag news:404dd391$1@fnewsb.telia.net... > Steve Casselman wrote: > > "Magnus Danielson" <magda@netinsight.net> wrote in message > > news:404c4a28$1@fnewsa.telia.net... > > > > The 8B/10B (or any other xB/yB) encoding is there so that you transmit an > > equal number of ones and zeros. This keeps the transceivers from saturating > > one way or the other. > > Almost true. For the 8B/10B encoding it is certainly true, with its > running disparity you ensure the DC balance i.e. equal balance between > 0s and 1s. In SDH/SONET you use scrambling with a PRBS to acheive DC > balance (an approximation) and in the 64B/66B (10GE) you also use > scrambling, but only for 64 bits while the other two bits (sync) is set > in a separate encoder/decoder block. It is this block which I want to > bypass since it creates an obstacle for my application. I can't use the > sync bits arbitrarilly, they must DC balance on their own (in 10GE they > are either 01 or 10). > > So, I still need to know where these bits show up on my Rocket I/O. > > Cheers, > Magnus - who defeated the SDH/SONET scrambler with a customized ping!Article: 68631
Ajey Patil <patilajeyb@netscape.net> wrote in message news:<1081664351.515136@sj-nntpcache-5>... > Hi All FPGA Gurus, > > Can someone point me to verilog source to build > 8bit x 16K Single Port Block Internal Ram to be used in integration > and testing of Openrisc soc on Spartan 3 LC board. > > I am using Xilinx Webpack 6.2, so Core generator is > not an option. > > Thanks in advance, > Regards, > AJ Look in the templates menu, it gives Verilog/VHDL example code for most useful structures that will be inferred from similar looking code. For some reason it does not supply a template for a dual ported Blockram writeable on 2 ports, only 1 so in that case I instance by name and connect up ports, guess XST doesn't have that recognizer done yet. OTOH something like this in your code might help reg [7:0] MyRam[16*1024-1:0]; .... always @(ck) if (we) MyRam[i] <= data; ... assign foo = MyRam[j]; regards johnjakson_usa_comArticle: 68632
hi! i saw the "annotated" version and i loved it!, specially the "crosslinks" or "hyperlinks" explaining what's the use or the definition of signals, etc. How did you produce it?, is there a program or IDE for VHDL that helps you write code that way? cause it's great! "Konrad Eisele" <eiselekd@web.de> escribió en el mensaje news:ddbcd13.0404101053.490c82c6@posting.google.com... > Open Source synthesizable Arm vhdl model: > > For those that are interested: > We have allocated a Opencores Project at: > http://www.opencores.org/projects.cgi/web/core_arm/overview > The source can be checked out via CVS or snapshots. > Meanwhile on sourceforge you can browse them too. Vhdl > files are annotated and nice to read. > http://skdec.sourceforge.net/build_html/vhdl/index.htm > Slowly but shurely we aproach a working verion. Indeed > very slowly.Article: 68633
John,
Thanks for your response, I am newbie to FPGA, so please
excuse my ignorance. If I use reg [7:0] MyRam[16*1024-1:0],
will that ensure that this ram will be allocated from Block Ram
in Spartan3 ?
I found a module in Xilinx library for 8 x 2k Block Ram
but I not sure how to extend it to build 8 x 16k, (I have a
general idea on generating EN for each block
from ADDR[14:11] , but not sure how to interface DO
and DI from all blocks )
RAMB16_S9 RAMB16_S9_inst (
.DO(DO), // 8-bit Data Output
.DOP(DOP), // 1-bit parity Output
.ADDR(ADDR), // 11-bit Address Input
.CLK(CLK), // Clock
.DI(DI), // 8-bit Data Input
.DIP(DIP), // 1-bit parity Input
.EN(EN), // RAM Enable Input
.SSR(SSR), // Synchronous Set/Reset Input
.WE(WE) // Write Enable Input
);
Any help in this regard would be highly appreciated.
Thanks,
Ajey
>OTOH something like this in your code might help
>
> reg [7:0] MyRam[16*1024-1:0];
>
> ....
> always @(ck) if (we) MyRam[i] <= data;
>
> ...
> assign foo = MyRam[j];
>
>
>regards
>
>johnjakson_usa_com
>
>
Article: 68634Hi folks, My laptop does not have a parallel port. So, I bought this PCMCIA to parallel port converter. http://www.quatech.com/catalog/parallel_pcmcia.php It claims to work exactly like a native parallel port. But I have problem using it with my FPGA. 10% of the time, it works perfectly. But 90% of the time, I get an error while downloading the bit stream to the FPGA. Impact gives me the following error messages: Device #1 selected //*** BATCH CMD : Program - p 1 PROGRESS_START - Starting Operation Validating chain... Boundary-Scan chain validated successfully. '1':Programming device... done. INFO:iMPACT:579 - '1':Completed downloading bit file to device. INFO:iMPACT:580 - '1':CHecking done pin ... done. '1': Programming terminated, Done did not go high. PROGRESS_END - End Operation. Elapsed time = 10 sec. All the download attempts, the successfull and un-successfull one, use the same bitstream file. My FPGA is D2E from digilent.cc. I have Webpack 6.2i with latest service pack installed, Windows XP Professional, PIII 700MHz and 256 MB RAM. Does anyone have any suggestion on how to fix the problem? Is there any other PCMCIA to parallel port converter, other than spp-100 from Quatech, that is available in the market? Please help, I really need to use this FPGA for doing my work! Thanks a lot in advance! HendraArticle: 68635
Can anyone list out a few algorithms for delay testing of fpga interconnects....Article: 68636
On Sat, 10 Apr 2004 23:21:01 -0700, Ajey Patil wrote: > Hi All FPGA Gurus, > > Can someone point me to verilog source to build > 8bit x 16K Single Port Block Internal Ram to be used in integration > and testing of Openrisc soc on Spartan 3 LC board. > > I am using Xilinx Webpack 6.2, so Core generator is > not an option. > > Thanks in advance, > Regards, > AJ The block RAMs are available as unisim models. Look in $XILINX/verilog/src/unisims/ The block RAMs models are, RAMB16_S18_S18.v RAMB16_S1_S4.v RAMB16_S2_S9.v RAMB16_S4_S9.v RAMB16_S18_S36.v RAMB16_S1_S9.v RAMB16_S2.v RAMB16_S4.v RAMB16_S18.v RAMB16_S1.v RAMB16_S36_S36.v RAMB16_S9_S18.v RAMB16_S1_S18.v RAMB16_S2_S18.v RAMB16_S36.v RAMB16_S9_S36.v RAMB16_S1_S1.v RAMB16_S2_S2.v RAMB16_S4_S18.v RAMB16_S9_S9.v RAMB16_S1_S2.v RAMB16_S2_S36.v RAMB16_S4_S36.v RAMB16_S9.v RAMB16_S1_S36.v RAMB16_S2_S4.v RAMB16_S4_S4.v The single port model that you want is RAMB16_S9.vArticle: 68637
Dave, As a third party observer, I felt that Austin's preemptive strike was justified given that the link was posted in the newsgroup. Likewise, I would have no problem with you directly answering the questions he raised. I may get myself in trouble here by violating the technical sanctity of this newsgroup, but I think some marketing (with technical or factual points) can be useful as long as it does not interfere with the specific technical questions posted. I had three points relating to the seminar in question that I hope you can address: 1) Was I/O timing taken into account at all for the benchmarks? Did the designs have I/O constraints? I would have liked to see both the Tsu and Tco on the critical path, instead of just the Fmax, since these can be traded off in many situations. In fact, a higher core Fmax at the expense of system Fmax may be useless in many applications. 2) How long has Altera had these 75 designs? Part of the discrepancy in performance between the two vendors may be that the tools, and possibly even the architectures, have been tuned to their in-house designs. 3) For your "best effort" comparision, did you use any manual placement/routing for either of the tools? Did you analyze the critical path of either vendor for possible improvement through manual intervention? SD davidg@altera.com (Dave Greenfield) wrote in message news:<5c156a0b.0404091635.6091f8fe@posting.google.com>... > Austin, > > To your comment: "Just wanted to be sure to balance the scales." > What exactly were you looking to balance? > The only related post was John Hu's posting that was a completely > technical reply (i.e. no marketing data or performance comparison > whatsoever) to a request for information comparing Virtex II with > Stratix. John also provided a pointer to where the user could get > information if he was interested. > Your post seemed like a bit of a preemptive strike against content in > a net seminar ? not information on this site. > > And "just can't stand it when others post "PM" so I feel obligated > to balance it out". > While I don't know what "PM" means, there was no applicable follow-up > post here whatsoever. Don't confuse a net seminar (where some degree > of marketing is generally acceptable) with a post here. > > Altera will respond to technical issues on this newsgroup (ideally > Altera's increased activity over the past 18 months has positively > contributed to this group). We will generally refrain from providing > marketing information here ? though we may point requesters to a > location where they can get marketing data. However, we will > selectively respond with marketing information where it is warranted > (i.e. when responding to direct competitive questions, incorrect > information, or competitor's claims). > > And this certainly applies to postings from any individual who > consistently uses a cloak of being just a technical person while > regularly dishing marketing data. > > Dave Greenfield > Altera Product Marketing > > > Thanks, I just can't stand it when others post "PM" so I feel > obligated > to balance it out. > > I do try to place some really useful and practical bits in the post, > however. > > AustinArticle: 68638
Hi A SoC done with EDK 6.1 using OPB_DDR core works OK in XPS but when the SoC is used in ISE flow the Xilinx OPB_DDR doesnt pass translate stage with error that asyn_fifo edif can not be loaded due to pin name mismatch! how to make it work? there should be some fix, but can not find in Xilinx answer database at least! thanks! Antti http://xilinx.openchip.orgArticle: 68639
Antti Lukats wrote: > "Dave" <postmaster@localhost> wrote in message > news:40767be7_1@news.chariot.net.au... > >>In January there was a discussion about the Spartan-3 LC kit from Memec. >>(http://www.memec.com/Memec/iplanet/link1/Spartan3LC_3.pdf) >>I'm wondering if anyone has purchased the kit and has any comments? >> >>In particular I’m interested in the USB 2.0 Interface. We are > > > S3LC uses Silabs serial to usb converter chip CP2101 > www.silabs.com/products/pdf/CP2101_Short.pdf Thanks for the Info. While I guess the data sheet is technically correct, I do believe it is a little misleading. The CP2101 is USB 2.0 complaint, but only runs a full speed (12Mbps) and worst still the exposed asynchronous interface to the FPGA has a maximum 921.6 kbps. You would have expected the datasheet to at least mention it uses a serial to USB bridge. In my opinion, if they wanted to use a simple USB to serial bridge type interface, they would have been better using a FTDI FT245BM which has a 1 byte wide Parallel FIFO bi-directional port to USB Virtual COM driver. It has a 1M Byte/sec transfer rate (8Mbits/sec).Article: 68640
> I'm trying to install the ISE 6.2 update under Linux. > My current version is 6.1 with no updates, > straight from the CDs. > > I get the following message : > "Xilinx Service Pack 6.2.01i Setup cannot be installed over Xilinx install > versions older than 6.2i." > > Since I have 6.1, this shouldn't happen. > You need to install ISE 6.2 first before you can install the service pack 1. HTH, Jim jimwu88NOOOSPAM@yahoo.com http://www.geocities.com/jimwu88/chipsArticle: 68641
Hello, Welcome aboard, Dave. davidg@altera.com (Dave Greenfield) wrote in message news:<5c156a0b.0404091635.6091f8fe@posting.google.com>... > While I don't know what "PM" means, there was no applicable follow-up In this context PM appears to be Pure Marketing. > Altera will respond to technical issues on this newsgroup (ideally > Altera's increased activity over the past 18 months has positively > contributed to this group). We will generally refrain from providing I for one have been delighted to see more Altera presence at this group. Greg, Vaughn, Paul, Hong and others have provided valuable support in this forum. It bears mention, however, that I have a paid Quartus subscription and an active mySupport account ! Yet the caliber of support I can get here, both from Altera and non-Altera folk, far surpasses what your company sees fit to provide through mySupport. For example, I posted 4 mySupport requests during the month of March. One generated a response "I submitted a Software Problem Report for this issue. It will be resolved in a future release of DSP Builder". Another -- in regard to AsyncClear on registered ports of Stratix memory blocks -- got me after 3 weeks a response "Asynclear is not support is stratix memory block", which I believe to be factually in error. The other two queries are gathering dust. The upshot of this is that you have a user like myself, who is happy with the Stratix chips and likes the Quartus software, yet I would not hesitate to do my next design in Xilinx. > marketing information here – though we may point requesters to a > location where they can get marketing data. However, we will > selectively respond with marketing information where it is warranted > (i.e. when responding to direct competitive questions, incorrect > information, or competitor's claims). > And this certainly applies to postings from any individual who > consistently uses a cloak of being just a technical person while > regularly dishing marketing data. I for one have not been put off by marketing content from Austin, nor for that matter from your colleagues at Altera. And here is a marketing question for you: What are Altera's plans with regard to DspBuilder ? I find it a buggy product, to the point where I find it amazing that it has been brought to us by the same team that brought us MaxPlusII and Quartus II -- both of which are truly first-rate. Is DspBuilder going to languish as a marketing counterpoint to Xilinx SystemGenerator, or is it going to brought up to the standard of Quartus ? Sincerely, -rajeev-Article: 68642
johnjakson@yahoo.com (john jakson) wrote in message news:<adb3971c.0404111020.1a27558d@posting.google.com>... > Ajey Patil <patilajeyb@netscape.net> wrote in message news:<1081664351.515136@sj-nntpcache-5>... > > Hi All FPGA Gurus, > > > > Can someone point me to verilog source to build > > 8bit x 16K Single Port Block Internal Ram to be used in integration > > and testing of Openrisc soc on Spartan 3 LC board. > > > > I am using Xilinx Webpack 6.2, so Core generator is > > not an option. > > > > Thanks in advance, > > Regards, > > AJ > > > Look in the templates menu, it gives Verilog/VHDL example code for > most useful structures that will be inferred from similar looking > code. For some reason it does not supply a template for a dual ported > Blockram writeable on 2 ports, only 1 so in that case I instance by > name and connect up ports, guess XST doesn't have that recognizer done > yet. > > OTOH something like this in your code might help > > reg [7:0] MyRam[16*1024-1:0]; > > .... > always @(ck) if (we) MyRam[i] <= data; > > ... > assign foo = MyRam[j]; > whoops, thatss a dual port R+W.Article: 68643
Hi Group, Lately there is a lot of talk about System C, is Xilinx or Altera planning to consider System C. I heard Forge tool from Xilinx is meant for Java programmers to do hardware designs, is xilinx/altera coming up with thier own tool set for doing design with C/C++. having said that I also want to know how complicated/easy it gets to design systems completely using C/C++ and letting the software takes care of diving the system into hardware modules and software programs. Streams C based product from Impulse Tech supports both Xilinx/altera soft processor cores,have anyone designed system with that. I started working with Virtex2pro ( thats my introduction into the world of FPGAs and embedded systems ) for over a year and now cosidering to start exploring ways to configure FPGAs. Actually I am a student doing my master's so I would like to think about how the growth will be on designing systems with C/C++ - its obvious using high level languages makes life much easier but not sure abt the difficulties your suggestions, criticism are all welcome Regards RamArticle: 68644
Ajey Patil wrote:
> John,
> Thanks for your response, I am newbie to FPGA, so please
> excuse my ignorance. If I use reg [7:0] MyRam[16*1024-1:0],
> will that ensure that this ram will be allocated from Block Ram
> in Spartan3 ?
>
> I found a module in Xilinx library for 8 x 2k Block Ram
> but I not sure how to extend it to build 8 x 16k, (I have a
> general idea on generating EN for each block
> from ADDR[14:11] , but not sure how to interface DO
> and DI from all blocks )
Ajey,
There are two ways you can get that RAM block into your design
without Coregen. You can build it structurally or you can infer it by
describing its behavior. Each has its pluses and minuses. Inferring
the RAM will simulate faster, likely take less code to describe and will
"in theory" be more portable but you leave it up the synthesis tool to
figure out how to best map it. If you describe it structurally, what
you see is what you get and when you simulate, it should behave more
accurately to what the end result will be however it can be more wordy
to build the design this way and can make it harder to take this code
and target another device. If you want to go structurally, you were on
the right path with the HDL Template you found however if you want a
8-bit wide by 16k deep RAM, you would probably be best off using 8,
RAMB16_S1's to build the RAM. It is generally best to not mess with
addressing if you want a larger RAM than can be contained in a single
RAM Block and instead go for the deeper RAM and split up your data
signals. You could use the new Verilog-2001 generate statement (Verilog
--> Synthesis Constructs --> Generate --> Generate Multiple Instances)
to generate the 8 instances of RAM if you want to go that route and that
could save you some typing.
The other way to do this is to infer the RAM. This might be easier for
you to do so I would actually suggest you go this route unless you
prefer the structural route. If you want to learn how to infer the RAM,
that too is in the HDL Templates. If you open the template and go to:
Verilog --> Synthesis Constructs --> Common Functions --> RAM -->
BlockRAM --> Single Port, you will see three coding templates for a No
Change, Read First and Write First RAM. Choose the one that best fits
your needs, copy that code into your design and modify the signal and
parameters in there (the items listed in-between the <>) to integrate
this into your design. That should be the easiest way to get what you
are looking for.
Good luck,
-- Brian
> RAMB16_S9 RAMB16_S9_inst (
> .DO(DO), // 8-bit Data Output
> .DOP(DOP), // 1-bit parity Output
> .ADDR(ADDR), // 11-bit Address Input
> .CLK(CLK), // Clock
> .DI(DI), // 8-bit Data Input
> .DIP(DIP), // 1-bit parity Input
> .EN(EN), // RAM Enable Input
> .SSR(SSR), // Synchronous Set/Reset Input
> .WE(WE) // Write Enable Input
> );
>
> Any help in this regard would be highly appreciated.
>
> Thanks,
> Ajey
>
Article: 68645
Hendra Gunawan wrote:
> 10% of the time, it works perfectly. But 90% of the time, I get an error
> while downloading the bit stream to the FPGA. Impact gives me the following
> error messages:
>
I had a problem like this with a batch of cpu boards.
The first set worked, with no problem.
The second set, failed like you describe.
The only difference in the boards, were day-codes on the SIO chip.
The problem was INIT getting glitched, I think.
Try it on some different machines, or a USB parallel port.
You may have to get out the scope to find it.
--
Gary A. Gorgen | "From ideas to PRODUCTS"
tunxis@comcast.net | Tunxis Design Inc.
| Cupertino, Ca. 95014
Article: 68646Hi Magnus, strange application but anyhow: I guess, when I look at ieee802.3ae appendix 44a figure 44a-1 the "sync header bits" were prepended every 64 scrambled bits, by the way a great way to synchronize via barrel shifter. I think if you don´t want that behavior search for a switch in the xilinx manual to switch of sync header generation, or scramble by yourself. (Do you only rely on the balancing character of the scrambler polynom?) kind regards, thomasArticle: 68647
It's a bug in the software. Ask Xilinx about "Case # 526088 Timing Analyser Clock Skew" for more information. They're gonna fix it! Cheers, SYms.Article: 68648
> I for one have been delighted to see more Altera presence at this group. > Greg, Vaughn, Paul, Hong and others have provided valuable support in > this forum. Oops ! Left Subroto out. -rajeev-Article: 68649
I'm glad I'm not the only one who's given up on mySupport. I think it is seriously broken. A number of times, I had to argue with whoever's on the other end that I really was experiencing a Quartus bug. Often, the response I got was a cut-and-paste of the Quartus error message, as if I wouldn't have looked at it myself already. I'm very thankful there are knowledgeable Altera people because this is the first place I go now for q&a now. -- Pete > > I for one have been delighted to see more Altera presence at this group. > Greg, Vaughn, Paul, Hong and others have provided valuable support in > this forum. > > It bears mention, however, that I have a paid Quartus subscription > and an active mySupport account ! Yet the caliber of support I can > get here, both from Altera and non-Altera folk, far surpasses what > your company sees fit to provide through mySupport. > > For example, I posted 4 mySupport requests during the month of March. > One generated a response "I submitted a Software Problem Report for > this issue. It will be resolved in a future release of DSP Builder". > Another -- in regard to AsyncClear on registered ports of Stratix > memory blocks -- got me after 3 weeks a response "Asynclear is not > support is stratix memory block", which I believe to be factually > in error. The other two queries are gathering dust. > > The upshot of this is that you have a user like myself, who is happy > with the Stratix chips and likes the Quartus software, yet I would > not hesitate to do my next design in Xilinx. >
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