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"Göran Bilski" <goran.bilski@xilinx.com> wrote in message news:cnapf8$n0p1@cliff.xsj.xilinx.com... > Stefan Oedenkoven wrote: > > Hi ng, > > > > im searching for a soft processor IP core with the following capabilities: > > - Interrupt (more than one interrupt / e.g. saving registers in stack) > > - 32 Bit ALU > > - common Instructionset (e.g. MIPS or an open source assembler included) > > - 'easy' to enhance special purpose registers and their neccesary additional > > instructions (e.g. Real Time Clock and load RTC-Register to Accumulator) there is one full SoC environment, all tools, simulator, debugger, plug and play bus - peripherals, etc... its all GPLed! (except the debug monitor) look at GRLIB www.gaisler.com LEON3 based SoC is larger than Microblaze system :( S3-400 is smallest device where it fits at all, and that almost bare CPU and RAM system > > I found at opencores.com many IP-Cores: > > -miniMIPS: > > miniMIPS seems to be a good choice, but it doesn't fit in a Spartan3 - 200k > > Gates (108% of LUTs). Did i miss to adapt some Xilinx-specific > > synthesize-adaptions? Hm, I did smalles MB system synthesis, I think MB soc can fit into S2-100, into S3-200 it fits also, but not very much peripherals :( > > - CPUgen > > not very good commented source-code... and i think it can only handle one > > interrupt, right?? CPUgen: that projects seems to be dead, if you have some arch of some .exe files and no full sources and if that has been static no updates for 6+ months, its dead (or not being public any more, other possibility) > > - Xilinx Microblaze (not free) > > does it really occupie only 1000 LUTs with a 32Bit ALU and multiple > > interrupts? > > Big disadvantage is the relative high prize of 75Cent per implemented core. > > > > if you have some experience with soft processor cores, please help me with > > some suggestions. > > > > thanks, > > stefan > > > Hi, > > Yes, MicroBlaze occupies 1000 LUTs. > MicroBlaze is shipped as part of EDK which cost $495. > There are no license fee or royalty fee with the usage of MicroBlaze as > long as you have bought the EDK. > The 75 cent is the cost of the 1000 LUTs that MicroBlaze occupies. > > Göran :) the 75 cent is some marketing stuff, if could be the price of MB only in the cheapest cell/dollar device in 250,000 qty. in real applications the MB SoC price (FPGA fabric price...) would calculate a little above dollar at least, more likely several dollars (or more in small qty design). AnttiArticle: 75801
Help, I've been trying to find a definitive answer to this question. Can I connect Virtex II pins configured as pure outputs (LVCMOS33 or LVTTL) directly to 5v LSTTL, ACT, or FCT INPUTS without any resistors and not risk any damage ? I've used the quickswitch design from the appnotes for my bidirectional pins, and 175 ohm series resistors for 5v TTL inputs to the Virtex II, but I tied the fpga outputs directly to 5v input logic pins and now I think I have a Virtex II part failure. Any feedback greatly appreciated. Thanks JimArticle: 75802
Jim, See below, Austin Jim wrote: > Help, > I've been trying to find a definitive answer to this question. Can I connect > Virtex II pins configured as pure outputs (LVCMOS33 or LVTTL) directly to 5v > LSTTL, ACT, or FCT INPUTS without any resistors and not risk any damage ? Yes (you can connect directly a 3.3V output to a 5V input). It is the reverse that you can not do without a resistor. > > I've used the quickswitch design from the appnotes for my bidirectional > pins, and 175 ohm series resistors for 5v TTL inputs to the Virtex II, but I > tied the fpga outputs directly to 5v input logic pins and now I think I > have a Virtex II part failure. Unlikely this is the cause. Unless the inputs can behave as outputs? Check during power ON? power OFF? > > Any feedback greatly appreciated. When you say a "part failure" what kind of failure? > > Thanks > Jim > >Article: 75803
Hi,
> There are no license fee or royalty fee with the usage of MicroBlaze as
> long as you have bought the EDK.
> The 75 cent is the cost of the 1000 LUTs that MicroBlaze occupies.
I found this statement in the MB FAQ:
10. If I understand you correctly, after purchasing the MicroBlaze
soft processor with the development kit for $495, we can use MicroBlaze in
as many projects and products as we want?
Yes. When you buy the MicroBlaze kit, you have a license to use the
MicroBlaze processor in as many Xilinx FPGA designs as you want at that
site. (A site is defined as a geographic location including a five mile
radius.) There is no limit to the number of Xilinx FPGA projects in which
you can implement MicroBlaze. There is no per device or project royalty.
What do they mean with this obscure site limitation? So for a big company
(with departments >5miles away from each other) i need more licences over
even for selling it to customers living somewhere >5 miles away? ;-) I've
never seen such a clause...
Hmmm... but without the 'per instance' licence the mb-core becomes more
attractive for me.
Maybe you can tell me, if there is a online gate-count application for the
mb-core. i can only find this 950 logic blocks minimum statement on the
xilinx site.
And is it possible to (easily) add own peripherals units (time
capture/release arrays) to the peripheral bus of the mb?
regards,
Stefan
>
> Göran
Article: 75804Stefan Oedenkoven wrote: (snip) > 10. If I understand you correctly, after purchasing the MicroBlaze > soft processor with the development kit for $495, we can use MicroBlaze in > as many projects and products as we want? > Yes. When you buy the MicroBlaze kit, you have a license to use the > MicroBlaze processor in as many Xilinx FPGA designs as you want at that > site. (A site is defined as a geographic location including a five mile > radius.) There is no limit to the number of Xilinx FPGA projects in which > you can implement MicroBlaze. There is no per device or project royalty. > What do they mean with this obscure site limitation? So for a big company > (with departments >5miles away from each other) i need more licences over > even for selling it to customers living somewhere >5 miles away? ;-) I've > never seen such a clause... My guess, given that there is no per device cost, is that development machines need to be within the 5 mile radius. For $495 you can probably afford more than one if the company is spread out more. That doesn't say anything about remote connections, either text only or remote viewing of graphics (such as VNC), from machines within the 5 mile radius. I would check for such restrictions, also. -- glenArticle: 75805
Stefan Oedenkoven wrote: > > Hi ng, > > im searching for a soft processor IP core with the following capabilities: > - Interrupt (more than one interrupt / e.g. saving registers in stack) > - 32 Bit ALU > - common Instructionset (e.g. MIPS or an open source assembler included) > - 'easy' to enhance special purpose registers and their neccesary additional > instructions (e.g. Real Time Clock and load RTC-Register to Accumulator) > > I found at opencores.com many IP-Cores: > -miniMIPS: > miniMIPS seems to be a good choice, but it doesn't fit in a Spartan3 - 200k > Gates (108% of LUTs). Did i miss to adapt some Xilinx-specific > synthesize-adaptions? > > - CPUgen > not very good commented source-code... and i think it can only handle one > interrupt, right?? > > - Xilinx Microblaze (not free) > does it really occupie only 1000 LUTs with a 32Bit ALU and multiple > interrupts? > Big disadvantage is the relative high prize of 75Cent per implemented core. > > if you have some experience with soft processor cores, please help me with > some suggestions. I believe there is an open source version of microBlaze called Mblaze, IIRC. There are also tons of 32 bit risc cores that have been developed and are supported by versions of the gnu compiler, again IIRC. Check out www.opencores.org -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 75806
Hi Stefan, Stefan Oedenkoven wrote: > Hi, > > >>There are no license fee or royalty fee with the usage of MicroBlaze as >>long as you have bought the EDK. >>The 75 cent is the cost of the 1000 LUTs that MicroBlaze occupies. > > > I found this statement in the MB FAQ: > > 10. If I understand you correctly, after purchasing the MicroBlaze > soft processor with the development kit for $495, we can use MicroBlaze in > as many projects and products as we want? > Yes. When you buy the MicroBlaze kit, you have a license to use the > MicroBlaze processor in as many Xilinx FPGA designs as you want at that > site. (A site is defined as a geographic location including a five mile > radius.) There is no limit to the number of Xilinx FPGA projects in which > you can implement MicroBlaze. There is no per device or project royalty. > > > What do they mean with this obscure site limitation? So for a big company > (with departments >5miles away from each other) i need more licences over > even for selling it to customers living somewhere >5 miles away? ;-) I've > never seen such a clause... > I don't think we will go out and start measuring the distance at customer sites. There are some tools (not Xilinx tools) which checks on what timezone you are in. I know since I tried to connect to a license server in San Jose, USA from my home in Sweden and the tool reported that the license didn't allow this due to that I was in a different continent. > Hmmm... but without the 'per instance' licence the mb-core becomes more > attractive for me. > Maybe you can tell me, if there is a online gate-count application for the > mb-core. i can only find this 950 logic blocks minimum statement on the > xilinx site. It really depends on the target FPGA and what options you enable on MicroBlaze. There are too many combinations of targets and options to make this table easy to use. It's far more easier to implement what you want feature that you need in the tools and see what you get. > And is it possible to (easily) add own peripherals units (time > capture/release arrays) to the peripheral bus of the mb? > Yes, It's easy to do this in the tools. There are two different buses you can use for MicroBlaze. The OPB and the FSL. Which to use is depending on what you want to do. > regards, > Stefan > > > > > >>Göran > > > Regards, Göran BilskiArticle: 75807
I read the ibis modell for my fpga (http://www.xilinx.com/support/sw_ibis.htm)... >|--------------------------- XC2S200 ------------------------------ >| >| XC2S200 with Package type PQ208: > variable typ min max >|R_pkg 182.50m 180.00m 185.00m >|L_pkg 13.350nH 11.700nH 15.000nH >|C_pkg 1.5500pF 1.3000pF 1.8000pF Ok, but that doesn't mean any short circuit protection, as 180mOhm isn't that much... >[Temperature Range] 27.0000 100.0000 0.000 >[Voltage Range] 2.5000V 2.3750V >2.6250V >[Pulldown] >| voltage I(typ) I(min) I(max) >| > -2.5000 -35.2520mA -24.0630mA -41.1300mA > ... > 4.8000 0.2267A 0.1802A 0.2622A > 5.0000 0.2513A 0.1997A 0.2917A I'm not sure if I understand this : When connecting a 5V voltage source to the fpga-io-pin (as pulldown-output), a current of 0.25A would be fed ? > As long as you stay within the Absoulte Maximum (Table 1, section 3) This is a thing that I can't find in the file spartan2.ibs... > Shorting ten or more to ground for a long time just might damage the > device. And that is a thing that I want to prevent. So I thought putting a resistor between an A/D-converter and falsely output-switched io-pin to prevent a hughe current. What I simply wanted to ask is, how much current is acceptable ? Regards, TimoArticle: 75808
Hi, I´m asking me if the REFCLK has a closer relationship to the recovered clock than mentioned in the user guide. Could this be possible: Using a fixed osc. with a frequ. of 100MHz as REFCLK. Receiving data with a variable datarate? TXCLK= 50..100MHz (TX) ----- fiber ------> RXRECCLK = (50..100MHz), REFCLK=100MHz Does the recovered clock has phase jumps, nice duty cycle etc - in other words: is it possible to use that clock as an input clock for an external clock synthesizer? kind regards, thomasArticle: 75809
In article <2vsl6fF2lpgieU1@uni-berlin.de>, Stefan Oedenkoven <stefan-oedenkoven@gmx.de> wrote: >What do they mean with this obscure site limitation? So for a big company >(with departments >5miles away from each other) i need more licences over >even for selling it to customers living somewhere >5 miles away? ;-) I've >never seen such a clause... My bet is that it is for economy-of-tech-support reasons: With two distinct geographic locations, Xilinx probably figures that the tech support load is increased as opposed to a single co-located development shop where you are more likely to ask a coworker first. -- Nicholas C. Weaver. to reply email to "nweaver" at the domain icsi.berkeley.eduArticle: 75810
Hi, I´m thinking about using the internal TAP controller and the boundary scan chain of the virtex devices to test our board. Currently we using special bitstreams for this purpose. As I found in the manual I only have to issue the EXTEST command and feed data to the 3bit/per IO chain. Is this the right order? Or should the first command the SAMPLE command and then - when all data is written - the EXTEST command? Some advices would be welcome ;-) Thank you! kind regards, thomasArticle: 75811
Part failure as in 3.3v sucking mucho current > 5 amps, when normally the module takes less than 100ma idle. When problems began, measured 2 ohms from 3.3v to gnd. 30ohm from 1.5v to gnd. Haven't done a full analysis yet, but the only active 3.3v parts on the board are the virtexII xc2v40, xcf02s, 2 quickswitch idtqs3r861 Thanks for replying, will post more when more info is available. Jim "Austin Lesea" <austin@xilinx.com> wrote in message news:cnb541$kht1@cliff.xsj.xilinx.com... > Jim, > > See below, > > Austin > > Jim wrote: > > > Help, > > I've been trying to find a definitive answer to this question. Can I connect > > Virtex II pins configured as pure outputs (LVCMOS33 or LVTTL) directly to 5v > > LSTTL, ACT, or FCT INPUTS without any resistors and not risk any damage ? > Yes (you can connect directly a 3.3V output to a 5V input). It is the > reverse that you can not do without a resistor. > > > > I've used the quickswitch design from the appnotes for my bidirectional > > pins, and 175 ohm series resistors for 5v TTL inputs to the Virtex II, but I > > tied the fpga outputs directly to 5v input logic pins and now I think I > > have a Virtex II part failure. > Unlikely this is the cause. Unless the inputs can behave as outputs? > Check during power ON? power OFF? > > > > Any feedback greatly appreciated. > When you say a "part failure" what kind of failure? > > > > Thanks > > Jim > > > >Article: 75812
Praveen, Comments included. "praveen" <praveenkumar1979@rediffmail.com> wrote in message news:ff8a3afb.0411150318.18b7f111@posting.google.com... > Hello, > > I want to know what is criteria for selecting the amount of gap > between two layers. Can i make the gap equal?. I have a PCB of Unequal > length gap and i want to make it equal length (PCB manfacturer time > deduces). > The gap between two layers is generally equal! ;-) You need to rewrite this paragraph so I can understand it properly. Your English is far superior to my Hindi, but maybe you could get someone to help proof read this for you? Also, explain what kind of signals you're using and what rise time they have. > > About the bypass capacitor value. IC manufacturer specify a value of > 0.01microfarad to .0 microfarad....I think bypass capacitor value > depending on the switching frequency....what is the relationship > between value of capacitor and switching frequency? any formula has > such? > Be careful here. At higher frequencies the size of the capacitor is the limiting factor to its impedance, not its capacitance. There's bugger all point in using a range of capacitances in an 0402 package, for example. I use a mix of 0805 and 0402 caps, 22u and 1u respectively. If you're a cheapskate, you could use smaller capacitances and it'd make very little difference at higher than 5MHz for the 0805 and 20MHz for the 0402. ( Check out http://www.murata.com/designlib/mcsil.html ) I use the big values because I need to kill the c.1-3MHz noise from my switchers, and a drinking buddy sells ceramic caps! ( http://www.component.tdk.com/TDKMLCCCapRange.pdf ) I'd stick with X5R ceramic, don't use Y5V. > > Waiting for reply > Wait no longer! Best, Syms.Article: 75813
Hi folks, Prentice Hall is going to release Xilinx ISE 6.3i Student Version. http://vig.prenhall.com/catalog/academic/product?ISBN=0131858394 Does anyone know the difference between this one and the Webpack or BaseX? HendraArticle: 75814
Timo,
Page 1, Table 1. Look at the allowed voltage. Then use the diode IV
table in the IBIS model to find current.
From the file,
[POWER_clamp]
| voltage I(typ) I(min) I(max)
|
-3.30 6.17A 6.28A 6.12A
-3.20 5.90A 6.01A 5.86A
-3.10 5.64A 5.75A 5.60A
-3.00 5.38A 5.49A 5.33A
-2.90 5.11A 5.23A 5.07A
-2.80 4.85A 4.96A 4.80A
-2.70 4.59A 4.70A 4.54A
-2.60 4.32A 4.44A 4.28A
-2.50 4.06A 4.18A 4.01A
-2.40 3.80A 3.91A 3.75A
-2.30 3.54A 3.65A 3.49A
-2.20 3.27A 3.39A 3.23A
-2.10 3.01A 3.13A 2.97A
-2.00 2.75A 2.87A 2.71A
-1.90 2.49A 2.61A 2.44A
-1.80 2.23A 2.35A 2.18A
-1.70 1.97A 2.10A 1.93A
-1.60 1.72A 1.84A 1.67A
-1.50 1.46A 1.59A 1.41A
-1.40 1.21A 1.33A 1.16A
-1.30 0.96A 1.08A 0.91A
-1.20 0.71A 0.84A 0.66A
-1.10 0.47A 0.60A 0.42A
-1.00 0.25A 0.38A 0.21A
-0.90 78.20mA 0.18A 53.88mA
-0.80 14.96mA 44.93mA 18.61mA
-0.70 6.69mA 8.78mA 10.98mA
-0.60 2.80mA 2.96mA 5.51mA
-0.50 0.68mA 0.83mA 1.82mA
-0.40 81.59uA 0.14mA 0.29mA
-0.30 5.30uA 14.08uA 20.76uA
-0.20 0.23uA 1.07uA 0.81uA
-0.10 8.35nA 67.32nA 24.93nA
0.00 1.14nA 6.95nA 4.38nA
So, if -0.5 V is the abs max, then the anything less than 1.82 mA is
perfectly safe.
Generally speaking, less than 10 mA will not affect operation, and will
not hurt anything. Anything more than that, will probably affect
functionality. Damage will occur above ~ 100 mA.
Austin
Timo Dammes wrote:
> I read the ibis modell for my fpga
> (http://www.xilinx.com/support/sw_ibis.htm)...
>
> >|--------------------------- XC2S200 ------------------------------
> >|
> >| XC2S200 with Package type PQ208:
> > variable typ min max
> >|R_pkg 182.50m 180.00m 185.00m
> >|L_pkg 13.350nH 11.700nH 15.000nH
> >|C_pkg 1.5500pF 1.3000pF 1.8000pF
>
> Ok, but that doesn't mean any short circuit protection, as 180mOhm isn't
> that much...
>
>
> >[Temperature Range] 27.0000 100.0000 0.000
> >[Voltage Range] 2.5000V 2.3750V
> >2.6250V
> >[Pulldown]
> >| voltage I(typ) I(min) I(max)
> >|
> > -2.5000 -35.2520mA -24.0630mA -41.1300mA
> > ...
> > 4.8000 0.2267A 0.1802A 0.2622A
> > 5.0000 0.2513A 0.1997A 0.2917A
>
> I'm not sure if I understand this :
> When connecting a 5V voltage source to the fpga-io-pin (as
> pulldown-output), a current of 0.25A would be fed ?
>
>> As long as you stay within the Absoulte Maximum (Table 1, section 3)
>
> This is a thing that I can't find in the file spartan2.ibs...
>
>> Shorting ten or more to ground for a long time just might damage the
>> device.
>
> And that is a thing that I want to prevent. So I thought putting a
> resistor between an A/D-converter and falsely output-switched io-pin to
> prevent a hughe current.
> What I simply wanted to ask is, how much current is acceptable ?
>
>
> Regards,
> Timo
>
Article: 75815Yo! Does anyone know about about a port of an OpenCore USB 2.0 core to either Xilinx, Altera or plain vhdl (of reasonale price).Article: 75816
Don't forget to look at the Altera's NIOS II. You can buy a developers kit (board and development tools) for about $1000.00. You can download Quartus II Webpack and NIOS II Evaluation from their website. DerekArticle: 75817
Thank you mk for your reply.
I pasted here the failed annotations, SDF file and verilog model.
What shall I do now with this kind of failures?
Thank you.
Here are the failed annotations.
---------------
ncverilog: v03.40.(s004): (c) Copyright 1995 - 2002 Cadence Design Systems,
Inc.
ncverilog: v03.40.(s004): Started on Nov 12, 2004 at 17:59:04
ncverilog
+access+r
-f sim
../../synthesis/netlist/sdm_wlan_net.v
./sdm_top_tbg.v
./include_lib.v
..............................<cut>
ncelab: *W,SDFNET: Failed Attempt to annotate to non-existent timing check
(RECOVERY (posedge CL) (posedge CK) (64.11)) of instance
tsdg.sdm_wlan.\r_sumout4_reg[2] of module SCJFD21S20.
ncelab: *W,SDFNET: Failed Attempt to annotate to non-existent timing check
(SETUP (posedge D) (posedge CK) (188.037)) of instance
tsdg.sdm_wlan.\r_sumout4_reg[2] of module SCJFD21S20.
ncelab: *W,SDFNET: Failed Attempt to annotate to non-existent timing check
(SETUP (negedge D) (posedge CK) (187.369)) of instance
tsdg.sdm_wlan.\r_sumout4_reg[2] of module SCJFD21S20.
ncelab: *W,SDFNET: Failed Attempt to annotate to non-existent timing check
(HOLD (posedge D) (posedge CK) (114.384)) of instance
tsdg.sdm_wlan.\r_sumout4_reg[2] of module SCJFD21S20.
ncelab: *W,SDFNET: Failed Attempt to annotate to non-existent timing check
(HOLD (negedge D) (posedge CK) (114.766)) of instance
tsdg.sdm_wlan.\r_sumout4_reg[2] of module SCJFD21S20.
Here is the SDF segment.
---------------
(DELAYFILE
(SDFVERSION "OVI 2.1")
(DESIGN "sdm_wlan")
(DATE "Fri Nov 12 14:28:19 2004")
(VENDOR "cs91sn_uc_core_worst_max")
(PROGRAM "Synopsys Design Compiler cmos")
(VERSION "2001.08")
(DIVIDER /)
(VOLTAGE 1.10:1.10:1.10)
(PROCESS "DEFAULT")
(TEMPERATURE 125.00:125.00:125.00)
(TIMESCALE 1ps)
........<cut>
(CELL
(CELLTYPE "SCJFD21S20")
(INSTANCE r_sumout4_reg\[2\])
(DELAY
(ABSOLUTE
(IOPATH CK Q (364.590:364.590:364.590) (349.149:349.149:349.149))
(IOPATH CL Q (0.000:0.000:0.000) (132.917:132.917:132.917))
)
)
(TIMINGCHECK
(WIDTH (posedge CK) (231.800:231.800:231.800))
(WIDTH (negedge CK) (269.800:269.800:269.800))
(RECOVERY (posedge CL) (posedge CK) (64.110:64.110:64.110))
(HOLD (posedge CL) (posedge CK) (233.606:233.606:233.606))
(SETUP (posedge D) (posedge CK) (188.036:188.037:188.037))
(SETUP (negedge D) (posedge CK) (187.369:187.369:187.369))
(HOLD (posedge D) (posedge CK) (114.385:114.384:114.384))
(HOLD (negedge D) (posedge CK) (114.766:114.766:114.766))
(WIDTH (negedge CL) (212.800:212.800:212.800))
)
)
And here is the cell verilog mode.
------------------
`resetall
`timescale 1ps/1ps
`celldefine
`ifdef verifault
`suppress_faults
`enable_portfaults
`endif
`ifdef FAST_FUNC
`delay_mode_unit
`else
`delay_mode_path
`endif
module SCJFD21S10( Q, CL, D, CK );
input CL, D, CK;
output Q;
reg notifier ;
supply1 clip_1 ;
`ifdef FAST_FUNC
`ifdef cwave
UDP_DFFQ I_00p01( N_00, CK_fjcw, D_fjcw, CL_fjcw, clip_1, notifier);
buf #1 ( Q, N_00);
buf ( CL_fjcw, CL);
buf ( D_fjcw, D);
buf ( CK_fjcw, CK);
`else
UDP_DFFQ I_00p01( N_00, CK, D, CL, clip_1, notifier);
buf #1 ( Q, N_00);
`endif
`else
`ifdef cwave
UDP_DFFQ I_00p01( N_00, CK_fjcw, D_fjcw, CL_fjcw, clip_1, notifier);
buf ( Q, N_00);
buf ( CL_fjcw, CL);
buf ( D_fjcw, D);
buf ( CK_fjcw, CK);
`else
UDP_DFFQ I_00p01( N_00, CK, D, CL, clip_1, notifier);
buf ( Q, N_00);
`endif
// TIMING CHECK NETLIST
// SDF format V2.1
UDP_EE1 ( CLe1, CL, clip_1);
UDP_EE0 ( CKe0, CK, clip_1);
and ( CLe1andDn0, CLe1, Dn0);
UDP_NE0 ( Dn0, D, clip_1);
specify
// PATH DELAY
(CL +=> Q) = (0 : 0 : 0 , 36.8 : 61.4 : 101.3);
(CK => Q) = (107.0 : 178.4 : 294.4 , 106.8 : 178.1 : 293.8);
`ifdef no_ifnone
`else
`endif
`ifdef bus_con_float_check
`ifdef dcmos
specparam BUSCHECK$ = 0;
`else
specparam BUSCHECK$ = 0;
`endif
`else
`ifdef dcmos
specparam BUSCHECK$ = 0;
`endif
`endif
`ifdef finfo
specparam
AREA$ = 198.000000,
BC$ = 7.000000,
ILF$CL = 0.00364,
ILF$D = 0.00166,
ILF$CK = 0.00228;
`endif
// Timing Checks
specparam
TCLW1_CL_CL = 67.20 : 112.00 : 184.80 ,
TCKWH2_CK_CK = 65.40 : 109.00 : 179.85 ,
TCKWL3_CK_CK = 85.80 : 143.00 : 235.95 ,
TSCL4_CL_CK = 262.35 : 437.26 : 721.47 ,
THCL5_CK_CL = 221.11 : 368.52 : 608.05 ,
TSD6_D_CK = 117.13 : 195.22 : 322.11 ,
THD7_CK_D = 86.10 : 143.50 : 236.77 ;
$width( negedge CL , TCLW1_CL_CL , 0 , notifier );
$width( posedge CK &&& CLe1 , TCKWH2_CK_CK , 0 , notifier );
$width( negedge CK &&& CLe1 , TCKWL3_CK_CK , 0 , notifier );
// SDF format V2.1
`ifdef sigstm
$setup( posedge CL &&& CKe0 , posedge CK &&& CLe1andDn0 ,
TSCL4_CL_CK , notifier );
$hold( posedge CK &&& Dn0 , posedge CL , THCL5_CK_CL ,
notifier );
$setup( posedge D &&& CKe0 , posedge CK &&& CLe1 , TSD6_D_CK
, notifier );
$setup( negedge D &&& CKe0 , posedge CK &&& CLe1 , TSD6_D_CK
, notifier );
$hold( posedge CK &&& CLe1 , posedge D &&& CLe1 , THD7_CK_D
, notifier );
$hold( posedge CK &&& CLe1 , negedge D &&& CLe1 , THD7_CK_D
, notifier );
`else
`ifdef pre_sdf
$recovery( posedge CL &&& CKe0 , posedge CK &&& CLe1andDn0 ,
TSCL4_CL_CK , notifier );
$hold( posedge CK &&& Dn0 , posedge CL , THCL5_CK_CL ,
notifier );
$setup( posedge D &&& CKe0 , posedge CK &&& CLe1 , TSD6_D_CK
, notifier );
$setup( negedge D &&& CKe0 , posedge CK &&& CLe1 , TSD6_D_CK
, notifier );
$hold( posedge CK &&& CLe1 , posedge D &&& CLe1 , THD7_CK_D
, notifier );
$hold( posedge CK &&& CLe1 , negedge D &&& CLe1 , THD7_CK_D
, notifier );
`else
$setup( posedge CL &&& CKe0 , posedge CK &&& CLe1andDn0 ,
TSCL4_CL_CK , notifier );
$hold( posedge CK &&& Dn0 , posedge CL , THCL5_CK_CL ,
notifier );
$setup( D &&& CKe0 , posedge CK &&& CLe1 , TSD6_D_CK ,
notifier );
$hold( posedge CK &&& CLe1 , D &&& CLe1 , THD7_CK_D ,
notifier );
`endif
`endif
endspecify
`endif // end of FAST_FUNC
endmodule
"mk" <kal@delete.dspia.com> wrote in message
news:mdl9p0tcocvg0jpukn2etofcsm65kfhc4i@4ax.com...
> On Fri, 12 Nov 2004 18:14:45 +0800, "Kelvin" <thefatcat28@hotmail.com>
> wrote:
>
> >Why my NCVerilog fail to annotate these three timing checks?
> > Annotating SDF timing data:
> > Compiled SDF file: sdm_wlan_worst_max.sdf.X
> >ncelab: *W,SDFNET: Failed Attempt to annotate to non-existent timing
check
> >(RECOVERY (posedge CL) (posedge CK) (64.11)) of instance
>
> Check your verilog models and you'll see that the check is from CL to
> posedge CK so there is really no (posedge CL) check. You need to
> replace
> (RECOVERY (posedge CL) (posedge CK) (64.11)) of instance
> with
> (RECOVERY CL (posedge CK) (64.11)) of instance
>
Article: 75818am looking for an usb2.0 ip core for plb and opb bus to connect to PPC or Microblaze?Article: 75819
Thank youArticle: 75820
"mike_treseler" <tres@fl_ke_networks.com> wrote in message news:<ee219f9f76e4cd8005f2e4e5ec5cb587@localhost.talkaboutelectronicequipment.com>... > > In which module do I find that LPM_MODULUS? > > It's in your "magic" megafunction code: > > entity LPM_COUNTER is > generic (LPM_WIDTH : positive; > LPM_MODULUS: natural := 0; > LPM_DIRECTION : string := "UNUSED"; > LPM_AVALUE : string := "UNUSED"; > LPM_SVALUE : string := "UNUSED"; > LPM_PVALUE : string := "UNUSED"; > LPM_TYPE: string := "LPM_COUNTER"; > LPM_HINT : string := "UNUSED"); > For details see: > http://www.edif.org/lpmweb/more/220model.vhd > > This is the sort of thing that inspires > some to banish the wizards and write > n ;= n + 1; > > -- Mike Treseler Does it have any effect on my design if I ignore this warning? Rgds AndréArticle: 75821
Hi again, The plot at "http://mitglied.lycos.de/vazquez78/" shows the situation: The blue plot represents the PLL output E measured at the dedicated clock output pin. The pink plot shows that the PLL does not lock (LOCKED signal does not get high). The green plot shows the input clock of the PLL.It is fed via the dedicated clock input pin. As the plot shows the PLL begins to tune but it does not lock. At the same time the voltage swing of the input signal is reduced while keeping the frequency stable. Is it possible that neighbor pins of the dedicated input/output clock pins may be hot-wired with the clock pins (I could not find any short) ? I have defined all unused pins to "input tristated" so that in a short case there should arise no problem. What other possibilities could be taken into consideration? I have made a timing simulation in Modelsim and the PLL does lock. Thank you for your help. Kind regards AndréArticle: 75822
Mounard le Fougueuxt a écrit: > Yo! > Does anyone know about about a port of an OpenCore USB 2.0 core to either > Xilinx, Altera or plain vhdl (of reasonale price). Verilog can be mixed with VHDL, and of course be synthesized alone. Keep in mind that this core, when implemented in an FPGA, must associated with an external PHY chip. -- ____ _ __ ___ | _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le - | | | | | (_| |_| | Invalid return address: remove the - |_| |_|_|\__|\___/Article: 75823
Im just beginning to read about Chipscope from Xilinx, and up to now, Im impressed by the product, and how easy it is to use. But the obvious question that comes to my mind is that... Is this doable; to extend the capture mem of ICON by connecting it somehow to external async SRAM. For our purpose (~5MHZ clk), which is slow by BRAM standard, it would be just a waste to spend all the bram of my XCV300 on the ILA. I think it is actually feasible, disconnecting the busses going to the BRAM, maybe using FPGA editor, from the ICON core and reroute them to external ram, but without proper documentation, this might take a while. Has anyone done something like that? Regards JacArticle: 75824
"Antti Lukats" <antti@case2000.com> wrote in message news:<cnahse$v3k$03$1@news.t-online.com>... > "Moti Cohen" <moti@terasync.net> wrote in message > news:c04bfe33.0411150553.707c63b1@posting.google.com... > > Hi all, > > > > I've just came back from the Electronica 2004 exhibition that took > > place in munich - Germany, I wanted to ask the guys here or the Altera > > guys - how come that they weren't there...? > > Altera was there, you had to find them, and they even had free T-Shirts! > So my wife changed from Z to A ;) her previous T shirt was Zilog-Z8 I looked for them in the Electronica web site and they werent there so I figured out that they wont be there.. and due to the fact that I also didnt saw them in the A4/A5 area I was under the impression that they didnt come at all.. And now after u told me about the T-shirt I'm realy realy sorry that I didnt found them ;) Maybe next time... > > Read my posting about my Electronica Trip, posted here a few days ago! > > > Xilinx has been there and so is Actel (their booths were located back > > to back) > > Lattice was also there (altough they were located a little far from > > the others). > > > > I know that in the past years Altera showd for this exhibition and it > > was very disappointing to see that they werent there this year. > > > > However I finally got to meet Ken Chapman from xilinx - he presented > > us with some new stuff for the spartan 3 picoblaze and it was very > > interesting. > > It's always nice to meet Ken, the real english-english gives one a warm > feeling instantly! Here I have to agree with you, he is a very nice guy - I also took our picture together. Moti. > > Antt
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