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"bh" <spam_not@nosuch.com> wrote in message news:<pAOld.5262$GV4.3584986@news4.srv.hcvlny.cv.net>... [snip] > Just meeting/exceeding the timing of the original > component is not good enough (IMHO) since there may be > unknown dependencies on timing that might have been caught > in the original qualification program. Tee hee. How very true. Many years ago I worked on an academic project that involved modifying an existing industrial robot controller (an ASEA IRb6, if anyone's interested). It was a very early design with a single Intel 8008 CPU, and it had no useful external data comms links. So we replaced the CPU board with our own version that had a Z80 on it instead (advanced stuff, eh!) and, at least to start with, we wanted to run the original code on it. We disassembled the maker's 8008 machine code and re-assembled it for the Z80 (the Z80 opcodes and architecture were a proper superset of the 8008, but the binary instruction codings were different). Everything worked perfectly except that, in one mode of operation, the robot moved at double speed. It turned out that the original designers had not been able to make the 8008's interrupt service routine run fast enough, and therefore it missed every second clock interrupt when in that particular mode. They had knowingly compensated for that by multiplying all the "speed" constants by two. Our Z80 design processed everything about 5x faster than the old version, and therefore it *didn't* miss alternate clock interrupts. We had not anticipated this behaviour, because we knew that everything was controlled by clock interrupts and therefore assumed that the timing and speeds would all be OK. Happy days, when it was possible to reverse-engineer by hand the whole embedded firmware of a non-trivial product... -- Jonathan BromleyArticle: 75776
"Subroto Datta" <sdatta@altera.com> wrote in message news:<M34ld.28263$Qv5.9268@newssvr33.news.prodigy.com>... > Based on the choices made in the Demote assignments dialog box, you can > convert LE assignments into LAB assignments and so on. Demote assignments > would be useful if you have an overconstrained placement and would then like > to relax these placement constraints. Therefore to answer your question your > LE assignments would be removed and added back as LAB assignments. If you > want to keep a backup of your LE assignments create a new revision using the > current revision which has the LE assignments as the base. Then do a Demote > assignments on the new revision. You can switchback to the old revision if > needed. > > > - Subroto Hi, thank you for your explanation. How can I switchback to the old revision ?Article: 75777
Hi Mark, > > Do you want the filter to run at 12MHz (i.e. full-parallel) or do you >> have a faster clock available that could be used to share hardware >> over multiple clock cycles? > > I've got a 65MHz clock and currently dividing by 6 to give 13MHz. OK - do you want the filter to run at 13MHz (I thought you said 12 before?) and use more area or run at 65MHz and use less area? I can generate something immediately for you that would run at 13MHz. Cheers, KenArticle: 75778
Hello, I want to know what is criteria for selecting the amount of gap between two layers. Can i make the gap equal?. I have a PCB of Unequal length gap and i want to make it equal length (PCB manfacturer time deduces). About the bypass capacitor value. IC manufacturer specify a value of 0.01microfarad to .0 microfarad....I think bypass capacitor value depending on the switching frequency....what is the relationship between value of capacitor and switching frequency? any formula has such? Waiting for reply Regards PraveenArticle: 75779
You have welth of info on Xilinx website. I think it's a XAPP623, XAPP189, XAPP158 ... Cheers, M. "praveen" <praveenkumar1979@rediffmail.com> wrote in message news:ff8a3afb.0411150318.18b7f111@posting.google.com... > Hello, > > I want to know what is criteria for selecting the amount of gap > between two layers. Can i make the gap equal?. I have a PCB of Unequal > length gap and i want to make it equal length (PCB manfacturer time > deduces). > > About the bypass capacitor value. IC manufacturer specify a value of > 0.01microfarad to .0 microfarad....I think bypass capacitor value > depending on the switching frequency....what is the relationship > between value of capacitor and switching frequency? any formula has > such? > > Waiting for reply > Regards > PraveenArticle: 75780
Dear Mark, Seems to be a half-band filter (half of the Nyquist freq of 6 MHz) so, when you use a FIR filter you can leave out half of the taps. The Xilinx core generator can generate a nice filter for you. For the tap values use some FIR design tool, look at www.mediatronix.com/tools for a free one, it can export to Xilinx .coe files. Regards, Henk van Kampen www.mediatronix.com "markp" <map.nospam@f2s.com> wrote in message news:2vn75sF2o7m4kU1@uni-berlin.de... > Hi All, > > I need to implement a low pass digital filter on 12 bit ADC data in a > Spatan > IIE device, but I'd like it to be multiplier free - in other words just > use > adders and bit shifting for the coefficients. The sample rate is 12Mhz and > I > need a sharp cut-off at around 3MHz. Does anyone know of a simple design > (IIR?) to do this, or a website/tutorial to give me some pointers? I've > seen > several websites with coefficient calculators, there are always a few > coefficients that can't be easily calculated with bit shifting and adding. > > Thanks! > > Mark. > >Article: 75781
Thanks Dave -- it sounds like all our views agree here (see other mails in thread) that 5-6Gb/s as a next step avoids the issues which become difficult at 10-12Gb/s. Also given the number of channels available (from Altera and Xilinx) this will meet our requirement (up to about 100Gb/s total throughput). Ian davidg@altera.com (Dave Greenfield) wrote in message news:<5c156a0b.0411121500.176f0fdb@posting.google.com>... > Ian, > Stratix II GX will elevate LE count, increase transceiver speed, and > increase channel count. I think the majority of chip-to-chip and > backplane requirements in the next generation will be better addressed > by transceiver speeds in the 5-6 Gbps range than in the 10-12 Gbps > range based on supporting infrastructure required. More details on > Stratix II GX are available today with an NDA. > > Dave Greenfield > Altera Marketing > > > > > > I've been trying to work out what total serial I/O capability is > > > available on the latest (and near future!) FPGAs, but it's not always > > > easy. In the timescales I'm looking at I guess that the likely > > > candidates are Virtex-4 (for which little information is available on > > > the MGTs), and whatever the "next-generation" Altera device is > > > (Stratix-II doesn't have serial I/O, Stratix GX does but may be > > > lacking in processing power) -- can anyone at Altera give any clue > > > about this? > > > > > > > > > > > Cheers > > > > > > Ian Dedic > > > Chief Engineer > > > Mixed Signal Division > > > Fujitsu Microelectronics Europe > > > > > > P.S. If there are things which can only be revealed under NDA, please > > > contact me off-list since we have NDAs with both Xilinx and Altera.Article: 75782
Hi all, I've just came back from the Electronica 2004 exhibition that took place in munich - Germany, I wanted to ask the guys here or the Altera guys - how come that they weren't there...? Xilinx has been there and so is Actel (their booths were located back to back) Lattice was also there (altough they were located a little far from the others). I know that in the past years Altera showd for this exhibition and it was very disappointing to see that they werent there this year. However I finally got to meet Ken Chapman from xilinx - he presented us with some new stuff for the spartan 3 picoblaze and it was very interesting.Article: 75783
24 I/O pins is not too much for most FPGA's that have the guts to do a reasonable job of processing video. What you don't want is direct connections to the camera. Many modern industrial cameras use the Camera Link standard, which provides high-speed LVDS signals on 5 twisted pairs. The receiving hardware is usually a National DS90CR288, which comes out with parallel data, control signals and clock that can be used by any FPGA. Newer FPGA's can probably take the high-speed serial data directly, but then I would still suggest adding an external LVDS buffer to avoid blowing out the more expensive FPGA if you get ESD on the line. Check out Pulnix, Dalsa, Cohu websites for some Camera Link examples and links to the Camera Link specification. If you want to start with an analog RGB camera instead, there are some good I.C.'s available for LCD panels that do a good job of digitizing the equivalent of P.C. video. The Analog Devices AD9888 has high performance, but will use more pins of the FPGA at the highest pixel rates. If you don't need really high performance video (high pixel clock rate) I would suggest starting with a digital video camera instead. Some older digital video cameras used parallel LVDS or RS422 and very fat cables to connect to a framegrabber. This method has mostly been replaced with Camera Link, and also USB or FireWire in lower performance cameras. For something more like TV resolution you could get a very inexpensive NTSC, PAL or SECAM analog camera and digitize with something like the Philips SAA7111A. Good luck. htj@es.lth.se (Hongtu) wrote in message news:<842b837e.0411140315.12403f17@posting.google.com>... > Hi, > I am trying to implement a system for video segmentation on xilinx > FPGAs. The application need raw RGB stream data from a video camera > and process it on FPGAs in real-time. Since using 24 pins(8 bits for > each color) is not a wise way to hook up cemera with an FPGA, I was > wondering what is usually done in such cases. About the camera, I will > get it from a company, and they promise they could provide any type of > camera I will need. > > > HongtuArticle: 75784
Hello When connecting external circuits to the fpga's IO-pins, should I use something like 10k-resistors to protect the IO-pins from overload ? I'm trying to be careful, but I could imagine a high signal on an output-IO-pin and connecting the pin to ground at the same time could destroy the fpga... Or do the Xilinx fpgas have an internal protection ? Regards, TimoArticle: 75785
Markp,
You can use a distributed arithmetic filter if you take advantage of the higher
available
clocks. With a 65 MHz clock, you have 5 clocks (13 MHz is 1/5 of 65, not 1/6)
per
pixel available. By using a two bit parallel distributed arithmetic filter you
can
get a quite compact filter. DA 'hides' the coefficient multiplies by summing
all the
bit partial products from all the taps before doing the shift-accumulate. The
Spartan
II has DLLs in it that can easily be used to double the 65 MHz clock to obtain a
130 MHz
clock. Doing that will cut the physical size of the filter in half, since then
you'd be able to
handle a 10 bit input with the serial filter. DA Filter designs at 130 MHz are
quite acheivable
in any of the SpartanII devices. I have a tutorial on distributed arithmetic on
my website at
http://www.andraka.com/distribu.htm . Also, the xilinx Coregen includes a
filter generator
that will create a distributed filter given a set of coefficients and a number
of parameters. The
major drawback to the coregen filter is that you cannot look inside to see how
it works nor to
improve the design. You can also take advantage of coefficient symmetry to
reduce the filter
size, and if it is acceptable to have the filter characteristic symmetic about
Fs/4 you can use a
half-band filter which has all the odd coefficients except the center one equal
to zero.
markp wrote:
> "Ken" <aeu96186@NOSPAM.yahoo.co.uk> wrote in message
> news:cn69m5$rme$05$1@news.t-online.com...
> > > I need to implement a low pass digital filter on 12 bit ADC data in a
> > > Spatan
> > > IIE device, but I'd like it to be multiplier free - in other words just
> > > use
> > > adders and bit shifting for the coefficients. The sample rate is 12Mhz
> and
> > > I
> > > need a sharp cut-off at around 3MHz. Does anyone know of a simple design
> > > (IIR?) to do this, or a website/tutorial to give me some pointers? I've
> > > seen
> > > several websites with coefficient calculators, there are always a few
> > > coefficients that can't be easily calculated with bit shifting and
> adding.
> >
> > Hi Mark,
> >
> > I can help you out with this by automatically generating VHDL for an FIR
> > implementation for your filter that uses shifts and adds.
> >
> > Please post the following details:
> >
> >
> > Do you want the filter to run at 12MHz (i.e. full-parallel) or do you have
> a
> > faster clock available that could be used to share hardware over multiple
> > clock cycles?
> >
> > Is the filter single-rate or are you decimating?
> >
> > Input bit-width?
> >
> > Signed/unsigned input?
> >
> > Quantised filter coefficients (integers ideally but fixed-point will do)
> or
> > more detailed spectral requirements (what -dB gain at 3MHz, pass-band
> ripple
> > etc., start rolling off at what freq, stop rolling of at what freq. etc.)
> >
> >
> > Cheers,
> >
> > Ken
>
> Hi Ken,
>
> Well I've gone for a rolling average filter at the moment, but the specs
> are:
>
> > Do you want the filter to run at 12MHz (i.e. full-parallel) or do you
> > have a faster clock available that could be used to share hardware
> > over multiple clock cycles?
>
> I've got a 65MHz clock and currently dividing by 6 to give 13MHz.
>
> > Is the filter single-rate or are you decimating?
>
> Single rate so far.
>
> > Input bit-width?
>
> 12 bit ADC data.
>
> > Signed/unsigned input?
>
> Unsigned.
>
> > Quantised filter coefficients (integers ideally but fixed-point will
> > do) or more detailed spectral requirements (what -dB gain at
> > 3MHz, pass-band ripple etc., start rolling off at what freq, stop
> > rolling of at what freq. etc.)
>
> -3db @ 3MHz, 4th order Butterworth type roll-off ideally, unity gain
> otherwise.
>
> Thanks!
>
> Mark.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 75786
It is far easier to do extended hold in the digital domain. If you are bent on
doing
it in the analog domain, you'll need a sample/hold amplifier for each channel.
In the end, this is going to require more circuit than if you abandoned the DAC
you have and replaced it with one for each channel. If you insist on going the
analog route, you will relieve the requirements somewhat by refreshing the
output
channels much more frequently than the external update rate.
Perhaps a better solution would be to do a Sigma-Delta DAC for each channel.
All that is required outside of the FPGA for that case is a simple one pole RC
filter for each channel, and one FPGA pin to dedicate to each channel. Inside
the FPGA the DAC is basically a couple adder/subtractors. I think Xilinx has an
app-note on this subject complete with the code for the FPGA macro. The macro
itself is quite small, and the signal coming out can be of very high quality
when the
update rate is low. The effective resolution depends on the chip rate, which
equates
to the FPGA clock rate relative to the output sample rate.
Veronica Matthews wrote:
> Just to put my aim in perspective: I'm neither trying to fool you nor trying
> to get my homework solved (like a given individual presumed). Why I am
> talking about a basic condition with respect to the "one D/A converter for
> multiple output channels"-configuration is that this single D/A converter
> already exists in hardware. It is there, physical, for me to touch, already
> bought... And now I want to use this very D/A converter to feed several
> output channels. Of course I could buy a DAC for every channel but that's
> not my intention. The hardware setup does not allow to solder other devices
> on the board. So PLEASE just take it as it is! I want to solve the problem
> that way. So don't try to proselytize me like that jehovah's witnesses
> guys... ;-)
>
> Hope you come up with more constructive suggestions!
>
> Veronica
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 75787"Moti Cohen" <moti@terasync.net> wrote in message news:c04bfe33.0411150553.707c63b1@posting.google.com... > Hi all, > > I've just came back from the Electronica 2004 exhibition that took > place in munich - Germany, I wanted to ask the guys here or the Altera > guys - how come that they weren't there...? Altera was there, you had to find them, and they even had free T-Shirts! So my wife changed from Z to A ;) her previous T shirt was Zilog-Z8 Read my posting about my Electronica Trip, posted here a few days ago! > Xilinx has been there and so is Actel (their booths were located back > to back) > Lattice was also there (altough they were located a little far from > the others). > > I know that in the past years Altera showd for this exhibition and it > was very disappointing to see that they werent there this year. > > However I finally got to meet Ken Chapman from xilinx - he presented > us with some new stuff for the spartan 3 picoblaze and it was very > interesting. It's always nice to meet Ken, the real english-english gives one a warm feeling instantly! AnttArticle: 75788
Ian, There is a definite advantage to using a transceiver designed to work at 10 Gbs at 6.25 Gbs -- there is a lot of margin! Using a 6.25 Gbs transceiver at 6.25 Gbs means that every one of them has to be just perfect, and pass the production BER test. We are in production. At 10 Gbs. And, you can see (and get delivery of) the Pro-X transceivers (today at the many RocketLab(tm) demo sites we have around the world). No "will", "more details under NDA", or any of that. Just product, working, on the shelf, shipping NOW. Austin Ian Dedic wrote: > Thanks Dave -- it sounds like all our views agree here (see other > mails in thread) that 5-6Gb/s as a next step avoids the issues which > become difficult at 10-12Gb/s. Also given the number of channels > available (from Altera and Xilinx) this will meet our requirement (up > to about 100Gb/s total throughput). > > Ian > > davidg@altera.com (Dave Greenfield) wrote in message news:<5c156a0b.0411121500.176f0fdb@posting.google.com>... > >>Ian, >>Stratix II GX will elevate LE count, increase transceiver speed, and >>increase channel count. I think the majority of chip-to-chip and >>backplane requirements in the next generation will be better addressed >>by transceiver speeds in the 5-6 Gbps range than in the 10-12 Gbps >>range based on supporting infrastructure required. More details on >>Stratix II GX are available today with an NDA. >> >>Dave Greenfield >>Altera Marketing >> >>>>I've been trying to work out what total serial I/O capability is >>>>available on the latest (and near future!) FPGAs, but it's not always >>>>easy. In the timescales I'm looking at I guess that the likely >>>>candidates are Virtex-4 (for which little information is available on >>>>the MGTs), and whatever the "next-generation" Altera device is >>>>(Stratix-II doesn't have serial I/O, Stratix GX does but may be >>>>lacking in processing power) -- can anyone at Altera give any clue >>>>about this? >>>> >>>> >>>>Cheers >>>> >>>>Ian Dedic >>>>Chief Engineer >>>>Mixed Signal Division >>>>Fujitsu Microelectronics Europe >>>> >>>>P.S. If there are things which can only be revealed under NDA, please >>>>contact me off-list since we have NDAs with both Xilinx and Altera.Article: 75789
Gunther, There will be no damage, as the FPGA IOs are tristated, so they don't care. Austin Gunter Knittel wrote: > Hi, > > I have a driver (244) with its OE-pins strapped to ground driving > towards I/O-pins of a 2V4000 FPGA. I will make sure these are > pure inputs once the configuration is loaded. I'm also aware of the > fact that the FPGA tristates its IOs prior to configuration. > All devices are connected to the same VCC, the 244 is never > powered when the FPGA is not, and vice versa. > My question is: what happens during Power-up (or Power-down)? > Is it possible that the FPGA-IOs are damaged during power > transition when the 244 is already (still) firing at full force? > > Any thoughts on this are appreciated. > Gunter > >Article: 75790
Timo, If you look in the IBIS models (there are in ASCII), you will find the protection diode IV curves. As long as you stay within the Absoulte Maximum (Table 1, section 3) limits of the specifications for any currents and voltages, everything will be just fine. Shorting an IO pin to ground momentarily will not damage the device. Shorting it for months just might damage it. Shorting more than one pin to ground momentarily will also not damage the device. Shorting ten or more to ground for a long time just might damage the device. Driving an output pin with another chip is likely to damage the other chip, not the FPGA. Austin Timo Dammes wrote: > Hello > > > When connecting external circuits to the fpga's IO-pins, should I use > something like 10k-resistors to protect the IO-pins from overload ? I'm > trying to be careful, but I could imagine a high signal on an > output-IO-pin and connecting the pin to ground at the same time could > destroy the fpga... > Or do the Xilinx fpgas have an internal protection ? > > Regards, > Timo >Article: 75791
"Gabor Szakacs" <gabor@alacron.com> wrote in message news:8a436ba2.0411150625.6bcad4d5@posting.google.com... > If you want to start with an analog RGB camera instead, there are > some good I.C.'s available for LCD panels that do a good job of > digitizing the equivalent of P.C. video. The Analog Devices AD9888 > has high performance, but will use more pins of the FPGA at the > highest pixel rates. If this is not for production you can get away with using the 9888 in non-demultiplex mode at frequencies much higher than the datasheet would suggest.Article: 75792
Hi, when compiling my project in QuartusII I get the warning: LPM_MODULUS input value is <integer>. It should be within the range of 1 to 2^<integer>. Assume no modulus input In the HELP it is explained like the following: -------------------------------------------------------------------------------- CAUSE: The LPM_MODULUS is set to value that is not valid. Valid range should be between 1 to 2^LPM_WIDTH. ACTION: Change the LPM_MODULUS value to a value within the valid range. Can somebody shed some light on it? In which module do I find that LPM_MODULUS? Rgds AndréArticle: 75793
"markp" <map.nospam@f2s.com> wrote in message news:2vq56eF2odbq7U1@uni-berlin.de... > <snip> >> >> OK, done, I think. >> >> John > > Thanks John. I'm not really sure how to tweek this for my system, but very > interesting stuff nonetheless. I decided in the end to go for a 'rolling > average' type filter (rectangular) with 16 taps, and this seems to be > working quite nicely so I think I'll stick with this. > But previously you said a sharp cutoff. You won't get that with an average. If your clock is at 12 MHz, and you want an LPF with a 3MHz cutoff, I would use a half-band filter. All even coefficients will be 0 (with the exception of a0 at 0.5). Also, the filter is symmetric in the time domain allowing you to use a folded ladder topology to use half the "multipliers". This will give you a response that's skew symmetric around fs/4.Article: 75794
Hi ng, im searching for a soft processor IP core with the following capabilities: - Interrupt (more than one interrupt / e.g. saving registers in stack) - 32 Bit ALU - common Instructionset (e.g. MIPS or an open source assembler included) - 'easy' to enhance special purpose registers and their neccesary additional instructions (e.g. Real Time Clock and load RTC-Register to Accumulator) I found at opencores.com many IP-Cores: -miniMIPS: miniMIPS seems to be a good choice, but it doesn't fit in a Spartan3 - 200k Gates (108% of LUTs). Did i miss to adapt some Xilinx-specific synthesize-adaptions? - CPUgen not very good commented source-code... and i think it can only handle one interrupt, right?? - Xilinx Microblaze (not free) does it really occupie only 1000 LUTs with a 32Bit ALU and multiple interrupts? Big disadvantage is the relative high prize of 75Cent per implemented core. if you have some experience with soft processor cores, please help me with some suggestions. thanks, stefanArticle: 75795
I havent found a lot of information on current happenings relating to implementation of neural networks on FPGA. What I am really looking for right now is a real world application which would actually exploit the reconfigurability aspect of the FPGA. One of those many fields holding interest were Density enhancement using FPGA. This is much based on work published by Bringham Young university, but since the hardware available would allow us to work a lot more in depth, and the reconfiguration time has gone down a lot, I am looking to see if the density of neurons can further be enhanced by piplelining and cashing the modularity of neural networks. I am new to this and so am not sure if it is even worth trying, as to concerns about time ( obviously would want to get a speed up over the software) Please help me with some more ideas for applications, and please let me know if my idea holds any weight. Regards, PradeepArticle: 75796
Stefan Oedenkoven wrote: > Hi ng, > > im searching for a soft processor IP core with the following capabilities: > - Interrupt (more than one interrupt / e.g. saving registers in stack) > - 32 Bit ALU > - common Instructionset (e.g. MIPS or an open source assembler included) > - 'easy' to enhance special purpose registers and their neccesary additional > instructions (e.g. Real Time Clock and load RTC-Register to Accumulator) > > I found at opencores.com many IP-Cores: > -miniMIPS: > miniMIPS seems to be a good choice, but it doesn't fit in a Spartan3 - 200k > Gates (108% of LUTs). Did i miss to adapt some Xilinx-specific > synthesize-adaptions? > > - CPUgen > not very good commented source-code... and i think it can only handle one > interrupt, right?? > > - Xilinx Microblaze (not free) > does it really occupie only 1000 LUTs with a 32Bit ALU and multiple > interrupts? > Big disadvantage is the relative high prize of 75Cent per implemented core. > > if you have some experience with soft processor cores, please help me with > some suggestions. > > thanks, > stefan > > > Hi, Yes, MicroBlaze occupies 1000 LUTs. MicroBlaze is shipped as part of EDK which cost $495. There are no license fee or royalty fee with the usage of MicroBlaze as long as you have bought the EDK. The 75 cent is the cost of the 1000 LUTs that MicroBlaze occupies. GöranArticle: 75797
> In which module do I find that LPM_MODULUS?
It's in your "magic" megafunction code:
entity LPM_COUNTER is
generic (LPM_WIDTH : positive;
LPM_MODULUS: natural := 0;
LPM_DIRECTION : string := "UNUSED";
LPM_AVALUE : string := "UNUSED";
LPM_SVALUE : string := "UNUSED";
LPM_PVALUE : string := "UNUSED";
LPM_TYPE: string := "LPM_COUNTER";
LPM_HINT : string := "UNUSED");
For details see:
http://www.edif.org/lpmweb/more/220model.vhd
This is the sort of thing that inspires
some to banish the wizards and write
n ;= n + 1;
-- Mike Treseler
Article: 75798markp wrote: > I need to implement a low pass digital filter on 12 bit ADC data in a Spatan > IIE device, but I'd like it to be multiplier free - in other words just use > adders and bit shifting for the coefficients. The sample rate is 12Mhz and I > need a sharp cut-off at around 3MHz. Does anyone know of a simple design > (IIR?) to do this, or a website/tutorial to give me some pointers? I've seen > several websites with coefficient calculators, there are always a few > coefficients that can't be easily calculated with bit shifting and adding. It would seem that if the coefficients are constants it would not be hard to generate the appropriate shift and add hardware, pipelined as appropriate. Presumably you could use adders and subtractors, and the design could be optimized toward minimizing the number of adder/subtractor stages. (I think that can be done, but I haven't tried to do it.) -- glenArticle: 75799
glen herrmannsfeldt <gah@ugcs.caltech.edu> writes: > markp wrote: > > > I need to implement a low pass digital filter on 12 bit ADC data in a Spatan > > IIE device, but I'd like it to be multiplier free - in other words just use > > adders and bit shifting for the coefficients. The sample rate is 12Mhz and I > > need a sharp cut-off at around 3MHz. Does anyone know of a simple design > > (IIR?) to do this, or a website/tutorial to give me some pointers? I've seen > > several websites with coefficient calculators, there are always a few > > coefficients that can't be easily calculated with bit shifting and adding. > > It would seem that if the coefficients are constants it would not > be hard to generate the appropriate shift and add hardware, pipelined > as appropriate. Presumably you could use adders and subtractors, and > the design could be optimized toward minimizing the number of adder/subtractor > stages. (I think that can be done, but I haven't > tried to do it.) See <<http://www.mathworks.com/products/filterhdl/>> for one product that can do exactly this (and more). You can for example create multiplier-free filters in two styles with optional pipelining. There are many other products in the marketplace for filter code generation; just look around. Disclaimer: I work for The MathWorks.
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