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Hello anyone! Does someone works with CS8900 under NIOSII? It's really works? Please, write works it with HAL? Thanks.Article: 75826
"T. Irmen" <tirmen@gmx.net_NO_SPAM> wrote in message news:cnb9m2$umt$1@online.de... > Hi, > > I´m thinking about using the internal TAP controller and the boundary scan > chain of the virtex devices to test our board. Currently we using special > bitstreams for this purpose. As I found in the manual I only have to issue > the EXTEST command and feed data to the 3bit/per IO chain. Is this the right > order? Or should the first command the SAMPLE command and then - when all > data is written - the EXTEST command? > > Some advices would be welcome ;-) you can do it all by using EXTEST command alone, if you know safe values for all iopads. in case you dont and dont wanna blow your circuitry you can use SAMPLE to pre-sample the current values and then use that readback to construct your new data for EXTEST command. in your case I would say EXTEST alone is sufficent you can sense and force any FPGA io pin and test or program any circuits connected to the FPFA AnttiArticle: 75827
Does anyone uses the PLB DDR Chip on the PLB Bus of the PPC? Does anyone uses the burst modus. According to the xilinx docu the timing constraints has to be set to 2ns for the burst modus to a specific clock domain connection. I have a lot of problems when i set the bust modus and in special because i do set the 2ns in the ucf. If i set 3ns the timing is easy fullfilled. Just to share some experiences i want to know if others do get the same problems with the DDR Chip? Does anyone uses SDRAM an the burst modus? Are there also any problems with that burst modus? Thanks for any feedback at all.Article: 75828
colin@beyondboxes.com (Colin Anderson) writes: > Has anyone here worked on or have run across a hobbyist-scale project > using DVI video/graphics? I would like to experiment with a DVI > transmitter fed by a dedicated SDRAM framebuffer, but I do not know > where to start. We've done DVI, using a TFP410 physical layer with the pixel data fed from an FPGA. It's not terribly difficult - sync timings are available from the information-mega-web in various places, and you just present one pixel after another. Pulling that data out of SDRAM isn't too tricky, the data sheets and appnotes from Micron are helpful here. You may also need to do some I2C setup of the DVI chip. My experience is with PIC- and SX-based projects, but > I'm about to start working with FPGA projects. Any advice is > appreciated! Start small and work up.... Generate the sync signals, view them on a scope. Generate some counters and use them to display grid patterns and things (generate the pixel data on-the-fly) Get the SDRAM interface working on it's own Then hook up the SDRAM to the display - voila. Have fun! Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 75829
> Hello anyone! Does someone works with CS8900 under NIOSII? It's really I've used the CS8900 with JOP, but not with the NIOS. However, the CS8900 is a VERY simple chip to interface (old ISA bus). You can take a look in the JOP sources (available at the link below): isa.vhd and iotal.vhd for the VHDL files and CS8900.java for the driver in Java (ported from the Linux sources). Martin ---------------------------------------------- JOP - a Java Processor core for FPGAs: http://www.jopdesign.com/Article: 75830
Jim, That sounds like a complete electrical overstress of Vcco (basically, complete oxide and/or junction failure). That is usually something caused by a power supply grossly overshooting on turn on (as in way beyond the abs max ratings), or momentary negative voltage being forced on the IO pins, or the Vcco supply (as in a momentary short to -48V -- always sure and sudden death!). Austin Jim wrote: > Part failure as in 3.3v sucking mucho current > 5 amps, when normally the > module takes less than 100ma idle. When problems began, measured 2 ohms from > 3.3v to gnd. 30ohm from 1.5v to gnd. > > Haven't done a full analysis yet, but the only active 3.3v parts on the > board are the virtexII xc2v40, xcf02s, 2 quickswitch idtqs3r861 > > Thanks for replying, will post more when more info is available. > Jim > > > "Austin Lesea" <austin@xilinx.com> wrote in message > news:cnb541$kht1@cliff.xsj.xilinx.com... > >>Jim, >> >>See below, >> >>Austin >> >>Jim wrote: >> >> >>>Help, >>>I've been trying to find a definitive answer to this question. Can I > > connect > >>>Virtex II pins configured as pure outputs (LVCMOS33 or LVTTL) directly > > to 5v > >>>LSTTL, ACT, or FCT INPUTS without any resistors and not risk any damage > > ? > >>Yes (you can connect directly a 3.3V output to a 5V input). It is the >>reverse that you can not do without a resistor. >> >>>I've used the quickswitch design from the appnotes for my bidirectional >>>pins, and 175 ohm series resistors for 5v TTL inputs to the Virtex II, > > but I > >>>tied the fpga outputs directly to 5v input logic pins and now I think I >>>have a Virtex II part failure. >> >>Unlikely this is the cause. Unless the inputs can behave as outputs? >>Check during power ON? power OFF? >> >>>Any feedback greatly appreciated. >> >>When you say a "part failure" what kind of failure? >> >>>Thanks >>>Jim >>> >>> > > >Article: 75831
Thanks everybody for your help, this will definitely help me make a decision. So far I have always worked with SRAM (Synchronous SRAM), but these beasts tend to get expensive when you need bigger sizes. To answer Rickmans question, I do need to read the written data, but it can be done at much slower speed. This also implies that there will need to be some refreshing done when the SDRAM is not written to at high speed. Alex rickman <spamgoeshere4@yahoo.com> wrote in message news:<4193BAAB.9A6DB107@yahoo.com>... > Alex Ungerer wrote: > > > > Hello, > > > > I am not sure if this is the right NG, but since it concerns memory > > driven by an FPGA, here goes. > > > > My question is about burst writes to SDRAM memory (be it standard, DDR > > or DDR2). > > > > Is it possible to sustain a burst write for an undefined number of > > words? Here is my setup: > > I have some incomming flow of data arriving at a constant speed of, > > say 250 MWords/s, which needs to be written to memory in a sequential > > order, until a Stop signal ends the burst. The length of the flow can > > be as long as several times the size of the memory, in that case the > > latter data overwrites the old one. > > > > Do SDRAM require dedicated refresh cycles, even if the write cycles > > will access in turn every possible location in the memory? > > > > Alternatively, would there be a way of refreshing a bank while writing > > into another one, without interrupting the 250 MWrd/s data flow? > > > > If this is technically possible, do SDRAM Controller IPs available > > from FPGA vendors (i.e. Xilinx, Altera) support sustained writes with > > no gaps in data flow? > > > > Any pointers to litterature, memory types, SDRAM controller IPs, would > > be appreciated. > > Looks like you have several different answers to your question. The > data sheet I looked at says you can do this. > > "Precharging one bank while accessing one of the other three banks will > hide the precharge cycles and provide seamless, high-speed, > random-access operation." > > I did something very much like this once and had a printed app note > (that's how long ago it was...) from Micron that described the operation > of SDRAMs pretty well. I can't find an electronic version, but most of > the info in the Micron data sheet which is not too bad. That Asian data > sheets are not nearly as good, but they all work the same other than > initialization details and they all are compatible with some basic init > sequence. > > The way to make this work without gaps is to overlap the precharge and > read/write commands with the current command. So just make sure you set > things up enough so that you meet all the timing specs, and there are a > lot of them!!! If your clock speed varies it will be a lot harder to > design. > > BTW, you didn't say if you needed to do this on reads as well? Doesn't > the unit play back too, or does it go directly into a PC? > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 75832
Hi Göran & Nicholas, thank you for this infos. i think for further details i'll contact your colleagues in the Munich office. regards, stefan "Göran Bilski" <goran.bilski@xilinx.com> schrieb im Newsbeitrag news:cnb8j8$n0p2@cliff.xsj.xilinx.com... > Hi Stefan, > > Stefan Oedenkoven wrote: > > Hi, > > > > > >>There are no license fee or royalty fee with the usage of MicroBlaze as > >>long as you have bought the EDK. > >>The 75 cent is the cost of the 1000 LUTs that MicroBlaze occupies. > > > > > > I found this statement in the MB FAQ: > > > > 10. If I understand you correctly, after purchasing the MicroBlaze > > soft processor with the development kit for $495, we can use MicroBlaze in > > as many projects and products as we want? > > Yes. When you buy the MicroBlaze kit, you have a license to use the > > MicroBlaze processor in as many Xilinx FPGA designs as you want at that > > site. (A site is defined as a geographic location including a five mile > > radius.) There is no limit to the number of Xilinx FPGA projects in which > > you can implement MicroBlaze. There is no per device or project royalty. > > > > > > What do they mean with this obscure site limitation? So for a big company > > (with departments >5miles away from each other) i need more licences over > > even for selling it to customers living somewhere >5 miles away? ;-) I've > > never seen such a clause... > > > I don't think we will go out and start measuring the distance at > customer sites. > > There are some tools (not Xilinx tools) which checks on what timezone > you are in. > I know since I tried to connect to a license server in San Jose, USA > from my home in Sweden and the tool reported that the license didn't > allow this due to that I was in a different continent. > > > Hmmm... but without the 'per instance' licence the mb-core becomes more > > attractive for me. > > Maybe you can tell me, if there is a online gate-count application for the > > mb-core. i can only find this 950 logic blocks minimum statement on the > > xilinx site. > It really depends on the target FPGA and what options you enable on > MicroBlaze. There are too many combinations of targets and options to > make this table easy to use. > It's far more easier to implement what you want feature that you need in > the tools and see what you get. > > And is it possible to (easily) add own peripherals units (time > > capture/release arrays) to the peripheral bus of the mb? > > > Yes, It's easy to do this in the tools. > There are two different buses you can use for MicroBlaze. > The OPB and the FSL. Which to use is depending on what you want to do. > > > regards, > > Stefan > > > > > > > > > > > >>Göran > > > > > > > Regards, > Göran BilskiArticle: 75833
Thanks for all the replies. What I was looking for is actually in the library guide. It's RAMB16, two entries of about 25 different flavors of RAM. There doesn't seem to be a wrapper that turns it into a ROM. (But I can turn off WE.) I just didn't find either when searching... I think I was googling for BLKRAM which is probably why I didn't find much that way. The software generates a ROM (like I wanted) if I feed it either a big case statement or use a constant array. (I fat fingered one attempt and left out the clock. That made a blizzard of LUTs, but it all ran at 100 MHz. :) I also got it working instantiating a RAMB16_S9 with a bunch of INIT_xx ... The suggestion of using data2mem is one of the ways I was looking for. (It doesn't support the parity bit.) The normal tool flow doesn't really support this approach. You can add a .mem file as a source, but you have to add a couple of magic command line options to make it do anything. (Or at least that's what I did.) data2mem needs a .bmm file to tell it where to put the bits. It seems as though the tools should generate that automagically, or at least semi-automatically. I couldn't figure out how to do that. The doc for data2mem describes the -mf option. I couldn't get it to work. I'm not sure it even makes sense - that info isn't in the bit file. But if you make a .bmm file by hand, the LOC info does get used by the tool chain. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 75834
How about creating a ethernet to jtag cable replacement? In that case, you only need to write a user mode program to tunnel (forward) info from network <-> JTAG. It will make the xmd, xst, etc on both windows and Unix platform much easier to develop, maintain and use. TCP/UDP Socket programming is so much easier to develop nad debug for all the platform. Right now, I have to build xilinx_pp drivers for different version of linux kernels. Does anyone have a patch for xilinx_pp driver for 2.6 kernel (Redhat FC 3 release)? -TonyArticle: 75835
> Maybe you can tell me, if there is a online gate-count application for the > mb-core. i can only find this 950 logic blocks minimum statement on the Just back from an practical "hands-on" seminar on Microblaze. Didn't try that during the lab session, but was said that a reference design exists for a Spartan 3-50 fit (just 2 slices free!). Obviously it's very limited, but it works. Something like 766 slices... they said it can be really routed. In my opinion, Mb excels when you need also some hardware co-processing functions made by surrounding FPGA logic, so you need some more free space, beside the core.Article: 75836
Hal Murray wrote: > Thanks for all the replies. > > What I was looking for is actually in the library guide. It's RAMB16, > two entries of about 25 different flavors of RAM. There doesn't seem > to be a wrapper that turns it into a ROM. (But I can turn off WE.) > I just didn't find either when searching... > > I think I was googling for BLKRAM which is probably why I didn't find > much that way. > > The software generates a ROM (like I wanted) if I feed it either a big > case statement or use a constant array. (I fat fingered one attempt > and left out the clock. That made a blizzard of LUTs, but it all ran > at 100 MHz. :) > > I also got it working instantiating a RAMB16_S9 with a bunch > of INIT_xx ... > > The suggestion of using data2mem is one of the ways I was looking for. > (It doesn't support the parity bit.) The normal tool flow doesn't > really support this approach. You can add a .mem file as a source, > but you have to add a couple of magic command line options to make > it do anything. (Or at least that's what I did.) > > data2mem needs a .bmm file to tell it where to put the bits. > It seems as though the tools should generate that automagically, > or at least semi-automatically. I couldn't figure out how to do that. > The doc for data2mem describes the -mf option. I couldn't get it to > work. I'm not sure it even makes sense - that info isn't in the > bit file. But if you make a .bmm file by hand, the LOC info does > get used by the tool chain. > I am a novice on this area but... IIRC data2mem allows one to reconfigure the tables. Do you need this feature? I have followed the link provided by Marc Randolph (XST user guide) and implemented a ROM using a constant. To make the vhdl module small I created a package to encapsulate the rom table. The data width is 18 bits as my design requirements. I had previously implemented this table following the app note guidelines and created the INIT_xx entries with a C program. Another simple C program to create the table and, at least in the simulation, it worked as expected. Regards. Elder.Article: 75837
"usman yousaf" <yousaf_usman@hotmail.com> wrote in message news:<ee89e07.-1@webx.sUN8CHnE>... > have 1701 eeprom and i want to configure two spartan fpgas how can i do this Usman, Check out the following link and see if it answers your questions. http://direct.xilinx.com/bvdocs/publications/ds027.pdfArticle: 75838
T Lee wrote: > How about creating a ethernet to jtag cable replacement? > > In that case, you only need to write a user mode program to > tunnel (forward) info from network <-> JTAG. > > It will make the xmd, xst, etc on both windows and Unix > platform much easier to develop, maintain and use. > > TCP/UDP Socket programming is so much easier to develop nad > debug for all the platform. > > Right now, I have to build xilinx_pp drivers for different > version of linux kernels. > > Does anyone have a patch for xilinx_pp driver for 2.6 kernel > (Redhat FC 3 release)? > > > -Tony Or use Chameleon POD on www.amontec.comArticle: 75839
tony.p.lee@gmail.com (T Lee) writes: > How about creating a ethernet to jtag cable replacement? I've made my own Ethernet based programmer. Works on virtually any OS and does not require a device driver. Also works with Xilinx Impact and Altera Quartus. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 75840
Thank you guys! that is very helpful for me. I just wanna ask one last question: After processing the input video stream, I got a binary outputs to be displayed in a either a monitor or sent back to a computer for real-time supervision, any recommendations on how to implement this? BR, HongtuArticle: 75841
vboykov@yandex.ru (vladimir) wrote in message news:<d6aed45c.0411160149.48a2bf4a@posting.google.com>... > Hello anyone! Does someone works with CS8900 under NIOSII? It's really > works? Please, write works it with HAL? Thanks. Hello, We still support the CS8900 for Nios II in "legacy SDK" mode -- you will find the driver source under the cs8900 folder's 'sdk/lib' folder. However, as we have not added a HAL driver as the lan91c111 MACs have replaced the 8900 in our development kits. You can port the existing legacy driver to HAL by following the directions in Altera app note 350 (www.altera.com/literature/an/an350.pdf) and in the Nios II software dev. manual chapter on creating device drivers for HAL (www.altera.com/literature/hb/nios2/n2sw_nii52005.pdf). Hope this helps! Regards, Jesse Kempa Altera Corp. jkempa at altera dot comArticle: 75842
Hi Mark, If you need synthesizable VHDL, testbenches etc, our software Tyd-IP Code Generator and ONEoverT Digital Filter Designer will give you all you need. There are other development packages out there also. Have a look around to make sure you get exactly what you need. Good Luck Alan www.tyder.com "markp" <map.nospam@f2s.com> wrote in message news:2vn75sF2o7m4kU1@uni-berlin.de... > Hi All, > > I need to implement a low pass digital filter on 12 bit ADC data in a Spatan > IIE device, but I'd like it to be multiplier free - in other words just use > adders and bit shifting for the coefficients. The sample rate is 12Mhz and I > need a sharp cut-off at around 3MHz. Does anyone know of a simple design > (IIR?) to do this, or a website/tutorial to give me some pointers? I've seen > several websites with coefficient calculators, there are always a few > coefficients that can't be easily calculated with bit shifting and adding. > > Thanks! > > Mark. > >Article: 75843
Thanks Austin, will check the power supplies more carefully and post back when I have more info. Jim "Austin Lesea" <austin@xilinx.com> wrote in message news:cnd7kg$iv81@cliff.xsj.xilinx.com... > Jim, > > That sounds like a complete electrical overstress of Vcco (basically, > complete oxide and/or junction failure). > > That is usually something caused by a power supply grossly overshooting on > turn on (as in way beyond the abs max ratings), or momentary negative > voltage being forced on the IO pins, or the Vcco supply (as in a momentary > short to -48V -- always sure and sudden death!). > > Austin > > Jim wrote: >> Part failure as in 3.3v sucking mucho current > 5 amps, when normally the >> module takes less than 100ma idle. When problems began, measured 2 ohms >> from >> 3.3v to gnd. 30ohm from 1.5v to gnd. >> >> Haven't done a full analysis yet, but the only active 3.3v parts on the >> board are the virtexII xc2v40, xcf02s, 2 quickswitch idtqs3r861 >> >> Thanks for replying, will post more when more info is available. >> Jim >> >> >> "Austin Lesea" <austin@xilinx.com> wrote in message >> news:cnb541$kht1@cliff.xsj.xilinx.com... >> >>>Jim, >>> >>>See below, >>> >>>Austin >>> >>>Jim wrote: >>> >>> >>>>Help, >>>>I've been trying to find a definitive answer to this question. Can I >> >> connect >> >>>>Virtex II pins configured as pure outputs (LVCMOS33 or LVTTL) directly >> >> to 5v >> >>>>LSTTL, ACT, or FCT INPUTS without any resistors and not risk any damage >> >> ? >> >>>Yes (you can connect directly a 3.3V output to a 5V input). It is the >>>reverse that you can not do without a resistor. >>> >>>>I've used the quickswitch design from the appnotes for my bidirectional >>>>pins, and 175 ohm series resistors for 5v TTL inputs to the Virtex II, >> >> but I >> >>>>tied the fpga outputs directly to 5v input logic pins and now I think I >>>>have a Virtex II part failure. >>> >>>Unlikely this is the cause. Unless the inputs can behave as outputs? >>>Check during power ON? power OFF? >>> >>>>Any feedback greatly appreciated. >>> >>>When you say a "part failure" what kind of failure? >>> >>>>Thanks >>>>Jim >>>> >>>> >> >>Article: 75844
I launch Modelsim from the Xilinx IDE. I would like it run all the way through, to a wait; statement in the testbench. How do I do that? In fact, since my testbed outputs to text files, I would rather not see the ModelSim workings at all, and would rather just stay in the Xilinx IDE. Brad SmallridgeArticle: 75845
I would eventually like to be able to read a BMP file directly into the ModelSim simulator. I understand now with VHDL the only file you can read are text files. Is there a way to read in binary data in another way, perhaps by using Verilog? Brad SmallridgeArticle: 75846
Hi Brad, Brad Smallridge wrote: > I would eventually like to be able to read a BMP file directly into the > ModelSim simulator. I understand now with VHDL the only file you can read > are text files. Is there a way to read in binary data in another way, > perhaps by using Verilog? It depends where your time is most profitably spent - VHDL can handle binary file IO, but the question is if you want to write your own BMP library in VHDL, or if you can obtain one at a cost you find acceptable. There are many variants in BMP, compression types, colour widths, the works... I'd be more inclined to use some existing (free) tool like the ImageMagick suite to convert your input BMP into a trivial RAW format, either ASCII or binary, and read those into your test benches. You can of course automate the conversion process with scripts, so it doesn't have to be fiddly at all. Regards, JohnArticle: 75847
Hi, Well, let me know if you figure this one out. I had a similar issue -- I wanted a Verilog simulation to write out a TIFF file. I couldn't find a way to write out a binary file, so wrote out ASCII data values to text file and then post-processed it into a binary TIFF file using a small program I wrote in C. Hoping there's a better way... Eric Brad Smallridge wrote: > > I would eventually like to be able to read a BMP file > directly into the ModelSim simulator. I understand > now with VHDL the only file you can read are text files. > Is there a way to read in binary data in another way, > perhaps by using Verilog? > > Brad SmallridgeArticle: 75848
I was looking for information on driving Spartan-3 inputs from 5V CMOS signals using series resistors, and eventually found answer record 19146 which covers this in detail. Executive summary: for LVCMOS33 input with Vcco min/max of 3.0/3.45V and 5V+/-10% CMOS signal, use minimum 263 ohms series resistance. That answers my question. But... Before I found that, I found XAPP 429, on interfacing 5V to CoolRunner-II CPLDs. On page 3, it says "A simple series terminating resistor is NOT an acceptable solution to interfacing 5V signals. In this situation, the current applied to the pin is not the offending factor. Since the cumulative damage to the gate oxide impedance is caused by voltage, merely limiting the input current does not protect the oxide." Why is the Spartan-3 different than the CoolRunner-II in this regard? XAPP 429 goes into great detail on the gate oxide, but doesn't make any mention of clamp diodes in the input pad structures. Did the CR-II really not have clamp diodes on the inputs? Or were the CR-II clamp diodes rated for significantly less current than those of the S-3? Without some understanding of why such different advice is given for the CR-II and S-3, I'm reluctant to use the series resistor approach. EricArticle: 75849
Brad Smallridge wrote:
> I would eventually like to be able to read a BMP file directly into the
> ModelSim simulator.
Here's one possibility:
http://groups.google.com/groups?q=vhdl+char_array
-- Mike Treseler
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