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Hi Dan, You need to draw wave forms of the 3 clocks and their individual select signals to make sure that they will not generate glitches at the transition time. (Think of a circuit when the select signal goes low and clock edge goes high at the same time, will an unwanted glitch be generated?) If the clocks are totally independent with each other, you need to use double-FFs to synchronize between async boundary for each transition to eliminate meta-stable possibilities. The circuit is a lot more complex than the circuit below. It is a little simpler (but you still need to check the waveforms thoroughly) if the 3 clocks are generated from the same source. The counter should be simple to implement. ChingArticle: 76426
Well, you are partly correct.
Everything you want placed has to have RLOCs down to the primitive. RLOCs are
hierarchical (unlike most of the rest of the xilinx tools, but that is another
story).
You can construct larger macros out of smaller ones, by putting an RLOC on a
placed macro. I use this capability extensively to build up large placed designs
in
relatively short time (you can see examples on the gallery page of my website at
http://www.andraka.com/gallery.htm ). The constructed macros are relatively
placed
within themselves, but the macro will 'float' allowing it to be picked up and
placed
absolutely either in floorplanning or automatically by the tools. VHDL permits
computation of the constants used in attributes, which allows you to use the
generate
statement to construct macros out of primitives complete with relative placement.
Doing so with Verilog is considerably more awkward, as it does not have the
constructs in it to do it.
Jacob Bower wrote:
>
> The problem with using RLOCs directly, firstly is that (as far as I
> understand them anyway) they only let me place individual logic elements like
> flip-flops for example. They won't let me place a macro-block which contains
> two multipliers and an adder for example. Not at least without first
> manually placing all the sub-elements of the multipliers and adder
> anyway, which brings me back to my original problem.
>
> The second problem is that RLOCs require relative co-ordinates specified in
> rows, columns and slice. This is useless if I want to say "put large logic A
> right of large logic B" or even perhaps "put small logic A and the bottom
> left hand corner of large logic B". In theory this should be possible in
> JHDL.
>
> At least this is my understanding, please correct me if I am wrong.
>
> - Jake
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 76427
Hi,
I'm working on some AES code.
I've declared the values of a particual register in one of the blocks
to be a constant.
[snip]
4'h0: rcon_func=32'h01_00_00_00;
[snip]
When synthesizing the design,the bits {23:0] are being trimmed and
it's leading to cutting out a whole buncgh of mappings .essentially a
useless synth output.
Any suggesteions on how to work around this latch trimming and force
the ISE not to trim latches/ff? or is there a better way to declare
values?
Article: 76428"Fred" <Fred@nospam.com> wrote in message news:41ab5c09$0$1059$db0fefd9@news.zen.co.uk... > > "ALuPin" <ALuPin@web.de> wrote in message > news:b8a9a7b0.0411250721.5b1e7f98@posting.google.com... > > "Fred" <Fred@nospam.com> wrote in message > news:<41a49114$0$1067$db0fefd9@news.zen.co.uk>... > > > I see that Micron SDRAMs are claimed to support Concurrent auto > precharge. > > > Is this a common feature amongst SDRAMs? > > > > > > I'm using a sample of a ICSI SDRAM at present and this feature isn't > > > mentioned in the data sheet. Is it safe for me to presume it doesn't > > > support Concurrent auto precharge? > > > > > > I am trying to write and read blocks of 4 words and don't really want to > > > extend the buffering to accommodate an 8 word burst! > > > > Hi, > > > > do you mean that you want to precharge for example bank A while > > still accessing bank B ? > > > > Rgds > > André > > Sorry for the delay in replying but yes it is where I can have 2 banks > active and use auto precharge to close a bank. The select another row, in > the bank just closed, to give a near continuous data flow. > > ICSI have admitted that this device is from an old batch of silicon which doesn't have this feature. I find it a bit annoying that there isn't a revision code on the IC which could have had a corresponding datasheet. Amazing lack of change control. Beware!Article: 76429
Patrick Kulle wrote: >Before I had a look at the power consumption using XPower I simulated >the FSM absolutely technology independent and only observed the >switching activity. The difference between the best and the worst >encoding is up to 40 percent of the switching activity. In the example that I gave there even is a 100% increase in switching activity (2 DFF as oposed to 1 DFF) but I am sure you can not see the difference in power consumption. >[...]The results for the Virtex 2 are equal for each encoding, there is not >even a difference between two encodings of more than 1 mW. If I try the >same experiment using a CoolRunner 2 I get different results for >different encodings again. Virtex-II has smaller device geometries than the Spartan-2, so the switching power will be lower. Running XPower gives the following results per event: DFF - 353fJ SR16 - 4853fJ RAMLut - 653fJ LUT+carry - 2756fJ If you have a LUT and a DFF per state bit you need about 300M bit transitions per second so see 1mW in power supply difference. How large is you state machine and how fast do you clock it? Kolja SulimmaArticle: 76430
Hello, I'm Ricky, an Italian student in eln eng. I'm working with a Xilinx Spartan3, I've designed a project that calculate a 12bit fft. The core reads data (in serial mode) from the ISSI 1M RAM block, calculates the fft, and then writes the results in an other zone of the memory. My problem is to put the initial data into the memory (from my pc) and read them at the end, to verify if the fft works! I knew that XESS corp. provides programs for their boards that permit to easily download and upload data to/from the RAM, but what about DIGILENT-XILINX boards? Do you know if there's a program that could help me? Please, help me, I'm working on a thesis, and I have no more time!!!.... Heeeeelp!!!Article: 76431
I've done this some time ago with a XC2S30 having 2 LUTs left and successfully p&r and then targettting onto some real hardware. I also have a test build that we use on our Broaddown2 XC3S400 that uses every I/O and 99%+ of registers with no problems. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "Adarsh Kumar Jain" <adarsh.jain@cern.ch> wrote in message news:coi7rq$nce$1@sunnews.cern.ch... > Should we ever get to that ? > I know typically A and X bother recommend 80-85% resource usage and so do a > lot of others > But besides having no provision for expansion of design and probably > extremely long p&r times, what are the other dangers of such a high resource > utilisation, if our clock is only 40 MHz. > Also what if we are using all 8 Rocket IOs in a device ? > > >Article: 76432
"Matthew Plante" <maplante@iol.unh.edu> wrote in message news:coih22$k99$1@tabloid.unh.edu... > Hi folks, > > I'm working on developing an embedded system with a xilinx v2pro fpga. I > have all my code for the ppc (including 2 block rams, one on the plb and the > other on the opb) done in xps, and exported it to the project navigator. I > am trying to add an additional block rom, but I don't want to add it in the > EDK, I just want it to communicate directly with fpga fabric. So, I used > the core generator, and created a bram instance that is 70 bits wide, and 8k > deep. The core generator doesn't create a .bmm or .mem file to accompany > this. So how do I go about adding the proper lines to the current bmm file? > I haven't found much for documentation on this. If I don't add any > information for the new ram to the bmm file created by xps, then when I > import the projnav files back into xps, and regenerate the bitstream, > data2mem errors out on me. 1) importing/exporting to XPS is generically bad approuch, try to create ISE toplevel and include the XPS system as module there 2) the .BMM file you need to create yourself and thats sort of pain 3) you can not use XPS to update your non EDK block ram created and included in ISE/coregen ok here is what is needed todo 1) create .BMM reads the docs, its doable 2) open the design in floorplanner, look up complete instance names of the BRAM block 3) add all the [2] in .UCF manually locking all the bram instances used by your block 4) rerun synthesis, now the block ram is in known locations 5) update the .BMM to inlcude the locked down positions 6) after the edk memories are updated (XPS) run data2mem using the .BMM you made and your .MEM file for the contents of your block ram as of today I know no other way of doing it. It should be possible (it actually is) to add .BMM files to ISE project but I had no luck so far with that approuch. NB: DATA2MEM was (at least few service packs ago) not able to update the par ity bits, so if the 70bit wide memory is using parity bits it maybe cant be updated at all with data2mem AnttiArticle: 76433
We use a XC2S15 in a consumer app with something on the order of 10-20K units per year. Does easypath make sense in this range? Or is easypath really only for larger FPGAs and larger volumes? Also, from scanning the newsgroup logs I get the idea that the NRE is much larger than you might think given that there are no masks to make. Does anyone have any war stories good or bad about using easypath? thanks.Article: 76434
"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:31495nF35d628U1@individual.net... > > "Nicholas Weaver" <nweaver@soda.csua.berkeley.edu> schrieb im Newsbeitrag > news:coikr1$11p9$1@agate.berkeley.edu... > > I'm doing a pretty complex state machine, which is perfect for in > > memory (blockRAM based) encoding. > > > > Before I go through and build my own state machine compiler out of > > python hack-scripts or Excel macros, does someone already have such a > > compiler available? > > XST offers an option to put logic into BRAMS. But I dont know if it is smart > enough to put the FSM into the BRAM. NO AnttiArticle: 76435
"Jeff Cunningham" <jcc@sover.net> wrote in message news:nUErd.4718$Fg2.1920656@newshog.newsread.com... > We use a XC2S15 in a consumer app with something on the order of 10-20K > units per year. Does easypath make sense in this range? Or is easypath > really only for larger FPGAs and larger volumes? only for larger > Also, from scanning the newsgroup logs I get the idea that the NRE is > much larger than you might think given that there are no masks to make. from xilinx.com I did see NRE of 75,000$ for easypath ! > Does anyone have any war stories good or bad about using easypath? > > thanks.Article: 76436
Kolja Sulimma wrote: > [...] Running XPower gives the following > results per event: > DFF - 353fJ > SR16 - 4853fJ > RAMLut - 653fJ > LUT+carry - 2756fJ > [...] Hellp Kolja, thanks for your post, now it gets clearer for me. Could you please tell me, where I can find the results per event you gave above? Thanks in advance PatrickArticle: 76437
Ray,
> Everything you want placed has to have RLOCs down to the primitive. RLOCs are
> hierarchical (unlike most of the rest of the xilinx tools, but that is another
> story).
> You can construct larger macros out of smaller ones, by putting an RLOC on a
> placed macro. I use this capability extensively to build up large placed designs
> in
> relatively short time (you can see examples on the gallery page of my website at
> http://www.andraka.com/gallery.htm ). The constructed macros are relatively
> placed
> within themselves, but the macro will 'float' allowing it to be picked up and
> placed
> absolutely either in floorplanning or automatically by the tools.
Unfortunately this again brings me back to the crux of my problem, which is
that in future I may have some macro blocks only available to me as EDIF.
Manually annotating each primitive in the EDIF with RLOCs, really isn't
feasible : )
Is there really no way at all that it is possible to use for example the
Xilinx map and par tools to map and relatively place a design and then
provide this in an EDIF form (possibly via some transformation utility)?
If this really is impossible, is there some automated/programmable way I can
modify a placed & routed design from the Xilinx tools, and then re-p&r them
to take into account the changes?
Thanks,
- Jake
Article: 764382S15 are usually a very cheap part and it should/would be difficult to justify a NRE charge on your volume. If you are not getting a good price on 2S15s then work your distributor a bit harder. We do this as a matter of course for our client projects but the trick is knowing what can be achieved. Otherwise consider a board re-spin and go to Spartan-3 but the gain may be marginal if good 2S15 pricing is in place. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "Jeff Cunningham" <jcc@sover.net> wrote in message news:nUErd.4718$Fg2.1920656@newshog.newsread.com... > We use a XC2S15 in a consumer app with something on the order of 10-20K > units per year. Does easypath make sense in this range? Or is easypath > really only for larger FPGAs and larger volumes? > > Also, from scanning the newsgroup logs I get the idea that the NRE is > much larger than you might think given that there are no masks to make. > > Does anyone have any war stories good or bad about using easypath? > > thanks. >Article: 76439
Ray Andraka <ray@andraka.com> wrote in message news:<41AE683C.E925DA23@andraka.com>... > John, > > There is something you can do about it: use a local copy of the control > signal and put a keep buffer on it. The snippet below is a simple VHDL > example: > snipping Thanks Ray, I will Verilog those suggestions into the layout, I'm sure that will help. regards johnjakson_usa_comArticle: 76440
Jeff, Easypath for us only makes sense on large devices, and large volumes. The NRE is to cover the test program which then provides a device that is tested for your pattern, as opposed to a regular FPGA which is not tested for your pattern. The newly introduced Easypath program did reduce the NRE, as well as allowing changes to parts of the design which we must test 100% (eg: LUTs, IO standards, etc.). This allows changes to be made as long as you do not change the routing. Often we have had customers come back to us and say "we just need one inversion here instead of what we had before." Changing the LUT contents is perfect for these simple changes. Can't do that with your ASIC! If an even larger change is required, we will work with you on that as well. In any event, even with Easypath, you are not totally lost when a problem comes up (like you would be with an ASIC or other "hard" product). Austin Jeff Cunningham wrote: > We use a XC2S15 in a consumer app with something on the order of 10-20K > units per year. Does easypath make sense in this range? Or is easypath > really only for larger FPGAs and larger volumes? > > Also, from scanning the newsgroup logs I get the idea that the NRE is > much larger than you might think given that there are no masks to make. > > Does anyone have any war stories good or bad about using easypath? > > thanks. >Article: 76441
"Victor Schutte" <victors@mweb.co.za> wrote in message news:<cojo15$edj$1@ctb-nnrp2.saix.net>...
> The CS8900 is a rather slow chip. I am running several applications at 60MHz
> at which the chip does not operate well. Edit the class.ptf file and
> increase the wait states and setup/hold times. Then add the component and
> recompile.
In addition to Victor's advice:
If you are using a modern (Quartus II 4.1 or later) version of our
tools, SOPC Builder has the capability to dynamically calculate
peripheral latency/wait states/tsu/th. Instead of specifying an
integer as below ("5" for example), specify an integer with unit time
(for example "50ns"). SOPC Builder will interpret the time in
nanoseconds and calculate the number of clocks based on your desried
system clock frequency... that way you can read timing parameters out
of the data sheet and apply them to your peripheral.
> "vladimir" <vboykov@yandex.ru> wrote in message
> news:d6aed45c.0411301115.d80a628@posting.google.com...
> > I've made a board with CS8900 for proto of NIOS Development kit board.
> > It works very strange, I read internal registers and sometimes they
> > was read correctly but in generaly incorrectly. Writing is correctly
> > as seem to me.
> > I'm using core of SOPC. Maybe someone gives me some advise.
> > Thx.
About the problem Vladamir is seeing: It is difficult to say without
more information about your system. Victor's timing advice is an
excellent place to start. After ensuring that timing requirements are
met and that signal integrity on your board is okay (FPGA IO to
CS8900). I think the next step would be to do basic register tests as
you seem to be performing, either with a C program or the legacy GERMS
monitor... if the above doesn't work it is time to get out a scope and
see how the signals Nios is presenting to the external device look.
A side note: I am submitting a bug report to request that we update
the cs8900 component's timing to use the above convention, even though
we are no longer shipping with it in the product.
Jesse Kempa
Altera Corp.
jkempa at altera dot com
Article: 76442Jacob Bower wrote: > Unfortunately this again brings me back to the crux of my problem, which is > that in future I may have some macro blocks only available to me as EDIF. > Manually annotating each primitive in the EDIF with RLOCs, really isn't > feasible : ) > > Is there really no way at all that it is possible to use for example the > Xilinx map and par tools to map and relatively place a design and then > provide this in an EDIF form (possibly via some transformation utility)? > > If this really is impossible, is there some automated/programmable way I can > modify a placed & routed design from the Xilinx tools, and then re-p&r them > to take into account the changes? > > Thanks, > - Jake Hi Jake, A different approach would be to use the Floorplanner feature which generates a reusable RPM core. You have the option of generating UCF constraints or a fully annotated core in NGC format (a binary file similar to the NGO file). Then as Ray mentioned you can add RLOCs throughout the hierarchy to further manipulate the relative placement. http://toolbox.xilinx.com/docsan/xilinx6/help/floorplanner/floorplanner.htm You also made a reference to reusing routing information. The Directed Routing feature in FPGA Editor can do this, also by generating UCF constraints. These two features are not incompatible with each other. http://toolbox.xilinx.com/docsan/xilinx6/help/fpga_editor/html/fe_hidd_directedroutecst.htm BretArticle: 76443
Jacob Bower wrote: > > Unfortunately this again brings me back to the crux of my problem, which is > that in future I may have some macro blocks only available to me as EDIF. > Manually annotating each primitive in the EDIF with RLOCs, really isn't > feasible : ) > > Is there really no way at all that it is possible to use for example the > Xilinx map and par tools to map and relatively place a design and then > provide this in an EDIF form (possibly via some transformation utility)? > > If this really is impossible, is there some automated/programmable way I can > modify a placed & routed design from the Xilinx tools, and then re-p&r them > to take into account the changes? I honestly don't understand your constraints. How do you plan to express your relative constraints if you don't want to put them in the EDIF file? What is your input format? Are you saying that you don't want to add the RLOCs, but rather you want the Xilinx tools to do it and then reproduce your original EDIF file with the RLOCs? Perhaps you could explain your intended tool flow more clearly. Like Denzel Washington said in "Philadelphia", "explain it to me like I'm a 6 year old". :) -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 76444
Yaju, The xchecker cable has been obsolete for about 4 years. You will neither find it nor its schematic on the Xilinx web site. Because the RS232 port has a standard communications protocol, doing boundary-scan operations through the xchecker entailed sending encoded command packets through the port to the cable where they were interpreted to perform specific functions. These included things like going to particular TAP states, pulsing TCK, and the like. So, in part, the answer to your question is "no, JTAG isn't simply a translationof voltage logic levels" JTAG is communications protocol that involves transitions through a 16 state controller. An implementation through an RS232 port would have to comprehend that. Also, I should note that boundary-scan control driven through RS232 is usually quite slow because of the overhead associated with the RS232 protocol and its speed and packet size limitations. Y Nagaonkar wrote: >I am trying to program my FPGA board without a Xilinx Parallel Cable. > >I would like to able to program the FPGA using the Serial Cable and >Serial Port (DB9). > >Also I am not sure if I understand JTAG correctly, but is there a way >to implement the JTAG interface on serial cable, the way the Xilinx >XChecker Cable does. Isnt JTAG simply a translationof voltage logic >levels. > >I was not able to find a schematic for the Xchecker cable. > >Any help is very much appreciated. > >Thanks > >Yaju Nagaonkar > >==================================================== >y a j u at B Y U edu >Electrical and Computer Engineering Department >Brigham Young University >Provo Utah USA 84604 > >Article: 76445
Jacob Bower wrote: > > Rickman, > > > Since you are targeting Virtex parts, you can use the Xilinx RLOC > > attributes to place your logic in a relative way. I know this can be > > done from VHDL and Verilog, but I know nothing about JHDL. Can JHDL > > provide attributes in a way that the Xilinx software can understand? > > Ultimately, the place functions in JHDL map down to RLOC properties in the > EDIF output. I could also explicitly annotate things with EDIF properties if > I wanted. > > The problem with using RLOCs directly, firstly is that (as far as I > understand them anyway) they only let me place individual logic elements like > flip-flops for example. They won't let me place a macro-block which contains > two multipliers and an adder for example. Not at least without first > manually placing all the sub-elements of the multipliers and adder > anyway, which brings me back to my original problem. > > The second problem is that RLOCs require relative co-ordinates specified in > rows, columns and slice. This is useless if I want to say "put large logic A > right of large logic B" or even perhaps "put small logic A and the bottom > left hand corner of large logic B". In theory this should be possible in > JHDL. > > At least this is my understanding, please correct me if I am wrong. I have not used RLOCs in quite a while, but if they still work the way they used to, you can specify a group of logic and associate that to any rectangular area with an RLOC without specifying how any of the internal logic will be placed. The area does not even have to be a "tight" fit and IIRC, other logic can fit into any of the holes that result. An RLOC can be as specific or as lax as you choose to make it and it can be applied to a single element or to any group. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 76446
erjs wrote:
> Hi,
> I'm working on some AES code.
> I've declared the values of a particual register in one of the blocks
> to be a constant.
> [snip]
> 4'h0: rcon_func=32'h01_00_00_00;
> [snip]
> When synthesizing the design,the bits {23:0] are being trimmed and
> it's leading to cutting out a whole buncgh of mappings .essentially a
> useless synth output.
So you mean it isn't really a constant? If it is the logic should be
right. If it isn't put a register off of some input pins so that
you can store a value into it. A shift register will only need a
few pins for all your non-contant constants.
-- glen
Article: 76447Johnson wrote: > > Thanks, > > When I clicked the link you provided, it led me to > http://groups.google.com/ > > Yes, I can read and reply from here. However, it will take me more > than 4 hours to see my new posts. I think it is too slow. Do some searching for online newsgroup access. I am pretty sure I have heard about at least one good source for free access that does not have the long delays of Google. I can't remember the name though, sorry. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 76448
erjs wrote:
>
> Hi,
> I'm working on some AES code.
> I've declared the values of a particual register in one of the blocks
> to be a constant.
>
> [snip]
> 4'h0: rcon_func=32'h01_00_00_00;
> [snip]
>
> When synthesizing the design,the bits {23:0] are being trimmed and
> it's leading to cutting out a whole buncgh of mappings .essentially a
> useless synth output.
>
> Any suggesteions on how to work around this latch trimming and force
> the ISE not to trim latches/ff? or is there a better way to declare
> values?
If your logic is being trimmed, it is because it is not doing anything.
The signals either have a fixed value or are never assigned a value and
remain at "unknown". When I have this problem and I can't figure out
what is causing it, I run a simulation and it will show you the logic
error you have made.
--
Rick "rickman" Collins
rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.
Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
Article: 76449
erjs wrote:
> Hi,
> I'm working on some AES code.
> I've declared the values of a particual register in one of the blocks
> to be a constant.
>
> [snip]
> 4'h0: rcon_func=32'h01_00_00_00;
> [snip]
>
> When synthesizing the design,the bits {23:0] are being trimmed and
> it's leading to cutting out a whole buncgh of mappings .essentially a
> useless synth output.
>
> Any suggesteions on how to work around this latch trimming and force
> the ISE not to trim latches/ff? or is there a better way to declare
> values?
>
You seem to be describing a synthesis issue which is not my expertise,
but I will comment on this to say that the constant register logic would
not survive the mapping process either.
An important distinction to make is that this is not actually trimming
behavior but optimization to a constant value. The optimization may then
trigger some trimming if for example, a FF control signal no longer has
any loads after a FF is optimized away. Trimming is easy to block with
an "S" property, but optimization can not currently be blocked. An
enhancement to the "S" property to block optimization during mapping is
currently scheduled for version 8.1i, which is not so close.
Meanwhile, an easy solution to prevent the optimization is to use an
INIT value for the register that is the opposite of the eventual
constant value.
Bret
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