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HAI I AM VIVEK. CAN YOU PLEASE GUIDE ME IN DESIGNING MULTIPLIER BY WALLACE TREE ARCHITECTURE IN VHDL/FPGAArticle: 77801
Nirav Shah wrote: > Has anyone come across an FPGA board with RF Front end at 2.4 GHz? > or any 2 development kit (FPGA and RF Front end kit), matching to each other > ? 2.4GHz RF Front end ? What would be its purpose : blue tooth, WLAN, ...? Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 77802
bill, email me at austin@xilinx.com directly to discuss, austin bill@viasic.com wrote: > Hi, Austin. > > IMO, the most important patent Xilinx filed in the field is 5068603. > It covers tons. > > However, I still need more info on the HardWire 1 and 2 families. > > Thanks, > Bill > > austin wrote: > >>Bill, >> >>Why didn't you say you were looking for prior art? >> >>Consult uspto.gov and do a search for xilinx, hardwire, etc. >> >>I am sure our IP lehal folks filed something! >> >>Best of luck with your endeavour (invention). >> >>If there is something you wish to discuss with Xilinx, I am gappy to >>direct you to th4e right folks, >> >>Austin >> >>Austin >> >>bill@viasic.com wrote: >> >>>Hi, Austin. >>> >>>Thank you for your description of the three families. This > > confirms > >>>what I've heard before. I've checked out about the first 200 links >>>yielded by Google when searching for 'xilinx hardwire'. Every one > > is > >>>about the most recent gate-array based family. The first two > > families > >>>seem to be hard to track down. >>> >>>My patent laywer is asking me for public documents on the first two >>>families, since these are considered strong prior art in the > > structured > >>>ASIC market. Unfortunately, these families were gone before the > > web > >>>took off, so there was never any on-line docs, so Google hasn't > > helped > >>>me. Of course, the devices themselves can still be found, and > > that's > >>>technically enough. >>> >>>Thanks, >>>Bill >>> > >Article: 77803
HI, I AM SYMON. I CAN USE GOOGLE. I SHOUTED WALLACE TREE MULTIPLIER INTO THE SEARCH BOX AND IT GAVE ME 7980 HITS. NUMBER 5 WAS THIS ONE http://www.andraka.com/multipli.htm Syms. <VIVEKEDU2003@YAHOO.CO.IN> wrote in message news:1105991360.684965.235960@f14g2000cwb.googlegroups.com... > HAI > I AM VIVEK. CAN YOU PLEASE GUIDE ME IN DESIGNING MULTIPLIER BY > WALLACE TREE ARCHITECTURE IN VHDL/FPGA >Article: 77804
On Sun, 16 Jan 2005 11:51:37 -0500, Mark Jones wrote: >Ken Smith wrote: (answering "What are the main stepps involved in circuit board design") >> >> >> 1) Decide what the bourd should do. >> .... >> 42) Loop back to 1 >> >> > > This is good! We should put this in a F.A.Q. ;) Done: http://www.fpga-faq.com/FAQ_Pages/0043_Steps_to_make_a_Printed_Circuit_Board.htm =================== Philip Freidin philip.freidin@fpga-faq.com Host for WWW.FPGA-FAQ.COMArticle: 77805
On Mon, 17 Jan 2005 06:07:15 GMT, Rich Grise <richgrise@example.net> wrote: >On Sun, 16 Jan 2005 11:51:37 -0500, Mark Jones wrote: > >Where's the FAQ? > >Thanks, >Rich The FPGA FAQ is at: http://www.fpga-faq.com =================== Philip Freidin philip.freidin@fpga-faq.com Host for WWW.FPGA-FAQ.COMArticle: 77806
Hi all,
I have a V2P design with data and clock coming from an A/D in LVDS format.
The clock of 210 MHz is an output from the A/D, so it is aligned with the
data with Data to Clock skew of 0.8 ns max according to the A/D datasheet.
Due to an error on the board, the clock polarity was reversed relative to
the data lines, so essentially I expect the "positive edge" to be in the
middle of the data phase at the FPGA pads. I have inserted a
wizard-generated DCM clk_deskew for fine tuning. Experimentally I found that
the design is most stable when the DCM is programmed to a fixed phase shift
of about 70 degrees (0.93 ns at 210 MHz). Below are the snippets from my
code and the timing constraints I am using as well as the related timing
report summary:
CLK_DESKEW_INST: clk_deskew port map(
rst_in => clk_deskew_rst,
clkin_p_in => clk_dco_P,
clkin_n_in => clk_dco_N,
locked_out => dcm_locked,
clkdv_out => open,
CLK180_OUT => clk_dco_180, -- I tried using this output, but it
didn't work well...
clkin_ibufgds_out => clk_dco_ibufgds,
clk0_out => clk_dco
);
G_1 :
for I in 0 to 11 generate
ADATBUF_INST: IBUFDS_LVDS_25
port map (adat_P(I), adat_N(I), adat(I));
ADAT_CLKIN_P:
process(clk_dco)
begin
if rising_edge(clk_dco) then
ll_adat(I) <= adat(I);
end if;
end process;
end generate;
NET "clk_dco" TNM_NET = "clk_dco";
TIMESPEC "TS_clk_dco" = PERIOD "clk_dco" 4.55 ns HIGH 50 %;
#INST "adat_N<*>" TNM = "TNM_ADAT_PADS" -- ISE doesn't like to see negative
side pads mentioned in constraints
INST "adat_P<*>" TNM = "TNM_ADAT_PADS";
TIMEGRP "TNM_ADAT_PADS" OFFSET = IN 2 ns BEFORE "clk_dco_P";
----------------------------------------------------------------------------
----
Constraint | Requested | Actual |
Logic
| | |
Levels
----------------------------------------------------------------------------
----
TS_clk_dco = PERIOD TIMEGRP "clk_dco" 4. | 4.550ns | 4.476ns | 7
550 nS HIGH 50.000000 % | | |
----------------------------------------------------------------------------
----
TIMEGRP "TNM_ADAT_PADS" OFFSET = IN 2 nS | 2.000ns | 1.598ns | 1
BEFORE COMP "clk_dco_P" | | |
----------------------------------------------------------------------------
----
While the design seems to be mostly working, I am not quite satisified for
the following reasons:
1. I am not sure why the numbers I use work the best;
2. According to my timing simulation the phase shift between the clk_dco_P
(positive side pad) and clk_dco (DCM output net) turns out to be 4.662 ns.
In functional mode I see it to be precisely 0.93 ns, i.e. equal to the
programmed fixed phase shift in the DCM. I am using Active HDL 6.3 and the
post-PAR model with the *.svf file generated by ISE6.3 for the timing
simulation.
3. The design is not rock solid. Despite the constraints are met, one build
might work, while another with a small irrelevant change in logic might not.
Perhaps the problem is somewhere else, but since tweaking the DCM
immediately makes the difference I tend to think that it is here.
4. I have tried to read all the Xilinx guides and appnotes realted to timing
constraints under different scenarios and I get confused every time I need
to apply my knowledge. It seems especially confusing for differential
signalling...
So, could someone please show me how this scenario should be properly dealt
with in terms of DCM settings and timing constraints and why?
Thanks,
/Mikhail
Article: 77807Hi, Anachip, Atmel and Lattice are the 3 vendors still supporting SPLDs. You can go to their web sites to find their distributors and find out which one offers the best price (parts+shipment cost). Ching Hu PS. I am an employee of Anachip USA in California. LaesQ wrote: > Hi, > > I am needing about 30 GAL22v10's for a small project I'm working on. > I've looked on most UK suppliers sites (RS, Farnell, etc.) but they > want to charge the earth (round £3 to £5) each for them. > > So I was wondering if anyone knows of a cheaper uk source. I'm looking > to pay around £1 each for them at the most. But all suggestions are > welcomed. > > Yours, > > LaesQArticle: 77808
Hi Mikhail, Soz, haven't the time to check your code, but a quick suggestion. Make sure the design is using the INFFs in the IOBs. Use FPGA editor to check. Also, your clock is on a global resource, right? It seems odd that design doesn't work 100% no matter what the DCM phase shift is. The aforementioned flaws could cause that. Good luck mate, Syms.Article: 77809
Hi, It's not following any particular protocol., but close to WLAN. Nirav "Rene Tschaggelar" <none@none.net> wrote in message news:41ec1e85$0$3397$5402220f@news.sunrise.ch... > Nirav Shah wrote: > > > Has anyone come across an FPGA board with RF Front end at 2.4 GHz? > > or any 2 development kit (FPGA and RF Front end kit), matching to each other > > ? > > 2.4GHz RF Front end ? > What would be its purpose : blue tooth, WLAN, ...? > > Rene > -- > Ing.Buero R.Tschaggelar - http://www.ibrtses.com > & commercial newsgroups - http://www.talkto.netArticle: 77810
Thank you Ken, your're right, I didn't adapted the data transitions relatively to the edge of my clock in the testbench. Now, during the simulations the violations has disappeared and the design responds has desired. Another question when you say : "I had the same problems in modelsim and solved it by making the testbench wait for a 1/4 clock period after an edge before supplying the next input. You may need to reflect your real system more closely than 1/4 clock period if you have detailed timing specs." Does it mean that your design has an offset in constraint equal to 1/4 of the period clock ? MichelArticle: 77811
> Atmel has the AT43USB380 OTG controller. Just had a look at this. It is very interesting. Now, the question is, can they be driven by a high-speed (100 MIPS) 8051 derivative? Of course, there's always the option to hook it into an unused PowerPC processor in the V2P. An extension to that is...one could also look into running Embedded Linux off the PPC on V2P and dispense with the pain an aggravation. -MartinArticle: 77812
Austin, I'm in a cranky mood due to dealing with a spuriously failing motherboard and this knee-jerk post of yours doesn't help either. > All: > > Proceed with extreme CAUTION! > > Stratix-2 Hardcopy is offered in two flavors: Roger is talking about a Stratix-1, which has a well established and proven design flow. Hardcopy II is not even fully there yet, as far as I, a lowly disti FAE from a postage-stamp-sized country, am aware of. > This kind of incompatibility between Altera?s FPGAs and their Hardcopy > cousins is prevalent across product families. Across many devices in the > Stratix family for instance, there exists a mismatch (between the > standard FPGA and the Hardcopy version) in memory blocks, user I/Os and > number of PLLs. These constraints can significantly hamper the > ?conversion? process and present customers with nasty surprises at a > critical juncture. I'm even polite enough to quote you... That's exactly why the HC 'virtual' parts were introduced into Quartus about a year and a half ago. If a customer has a hunch (s)he may want to go for Hardcopy later on, these devices can be used to test pin compatibility, timing and resource usage. If aforementioned customer runs into any incompatibilities at a critical juncture they have either (1) not listened to their Altera FAE, (2) not used the HC1Sxxx virtual device for prototyping, (3) use asynchronous design techniques, (4) not read the _very_ detailed design signoff checklist or (5) any of combination of the above. There may be more sources of problems, but all of these fall into the category 'didn't we tell you?'. Altera is very focused on having Hardcopy designs to run first time and provides very strict design rules to adhere to before accepting a design for conversion. > The net result is higher development costs, unit cost > and delayed time to market. Fuddyfuddyfuddy.... Note that I'm not making snide remarks about Xilinx's low-cost volume product. I could, but I won't. Urgh... hope I'm in a better mood tomorrow... BenArticle: 77813
Hello, I'm trying to create a submodule in EDK that contains microblaze and a custom core that basically just passes some of the OPB signals through to the top: --forward signals CLK <= Bus2IP_Clk; CS <= Bus2IP_CS; RdCE <= Bus2IP_RdCE; WrCE <= Bus2IP_WrCE; Reset <= Bus2IP_Reset; Addr <= Bus2IP_Addr; Data_out <= Bus2IP_DATA; IP2Bus_DATA <= Data_in; When I connect the signals to a test register in ISE I am able to properly write to the register from microblaze using XIo_Out32, but when I try to read the value back using XIo_In32 it always reads 0x00000000, even when I connect a constand value to the Data_in signal. I am able to read the register through other hardware to see that it is being written correctly, but never when using microblaze. Along the same lines, I am trying to trigger global interrupts to microblaze, but they are not working. I am enabling them in my code and have set the global interrupt handler. I make the microblaze INTERRUPT port external and trigger it in my VHDL code. Do you need to do something special with input signals when having microblaze as a submodule? Any advice would be appreciated. Thanks!Article: 77814
"Symon" <symon_brewer@hotmail.com> wrote in message news:352uobF4gtlijU1@individual.net... > > Make sure the design is using the INFFs in the IOBs. Use FPGA editor to check. Yes, I have checked this.... > your clock is on a global resource, right? Sure it is. /MikhailArticle: 77815
Speaking of Embedded Linux...there's also the Freescale(Motorola) MPC885. An interesting option in that, it can provide external intelligence for a design as well as run Linux, get you USB Host/Peripheral support, 10/100 Ethernet, serial, etc. What resources are available with regards to running Embedded Linux off a PPC on a V2P? -MartinArticle: 77816
Hi Vladan, Another very useful resource for help on a) command line scripting (i.e. passing arguments to the various executables on the command line, as well as b) procedural scripting (i.e. using Tcl commands for interpretation by the executables Tcl interpreter) can be found at http://www.altera.com/literature/manual/TclScriptRefMnl.pdf If you need finer control it is possible to call quartus_map, quartus_fit, quartus_tan, quartus_asm, quartus_pow, quartus_eda and quartus_sim separately with the appropriate options. The document referred to in the URL covers the options in full detail. Hope this helps, - Subroto Datta Altera Corp. <vladan2005@gmail.com> wrote in message news:1105989854.392822.192810@c13g2000cwb.googlegroups.com... >I hate to reply to my own posts, but I think I may have found a > solution, so I'll post it here for the sake of completeness. > > The following command will do a full compilation while taking into > account the project files generated by the GUI: > quartus_sh --flow compile <name of QPF> -c <name of desired revision> >Article: 77817
Create a tcl file. Then call Quartus on the command line mode. Read the documentation. Also check teh example Chip trip I believe, has an example tcl file. Bacically, it defines the project name, and any options you set. Such as fpga family and device. It'll use any schematic, vhdl, vhd files in the project. Much better that Xilinx. You can also use the Error Level to trap any errors if you call it from a Batch file. You can also call the programmer this way also. Cheers "Vladan" <vladan2005@gmail.com> wrote in message news:6e6977ba.0501171026.6e708d68@posting.google.com... > Hi, > > I have a Verilog project created through the Quartus II 4.1 GUI under > Windows. I am trying to build it (analyze, synthesize, fit, etc) > using the Windows command-line quartus_<name> tools. > > Is it possible to reuse the project files such as qpf and qsf with the > quartus_map, quartus_fit, etc tools? I don't see any way to pass them > in. > > Do I have to figure out the command line equivalents for every setting > in each file's corresponding qsf? > > Would it be easier to generate a TCL script from the GUI and then use > the quartus_sh TCL interpreter instead? > > I am looking for the fastest way to do this. > > Thank you, > > VladanArticle: 77818
Chuck Harris wrote:
> Hi Ales,
>
> Ales Hvezda wrote:
>
>> Hi,
>>
>> I usually like spending my free time working on the code rather than
>> posting to USENET, but I want to address some of the points from the
>> previous poster in this thread.
>
>
> Thank you, I appreciate your time. I would prefer not to use this
> forum for detailed debugging, but since I started this, and have no
> interest in performing a hit-and-run tar & feather job, I guess we have
> to resolve the problems here in public.
>
Hi Ales and Stuart,
I have finally spent the time to track down all of the problems I was
having installing the gEDA suite, and I now think I have a successful
build from using the CDROM.
The two things that messed up my build were:
1) I installed pkg-config using the package included with gEDA, only
I think I built it as user, and installed it as root. This made the
search paths all be based in my home directory, and not in /usr.
My redhat installed pkg-config was in /usr/bin, and my gEDA installed
pkg-config was in /usr/local/bin. /usr/local/bin comes first in my
path, so I was working with the defective version. That's what I get
for trying to upgrade pkg-config outside of the rpm/apt-get system.
2) my /etc/ld.so.conf file was stock RedHat, with some additions by other
package installations. It did not include /usr/local/lib in its search
paths.
Problems/complaints:
1) I don't like to see LD_LIBRARY_PATH and PKG_CONFIG_PATH globally set.
They provide a capability for testing new versions of system libraries.
I don't believe they were intended to be used system wide. For that
you should add the path to the appropriate /etc/xxxx.conf file. It's
a shame there isn't one for pkg-config (AFAIK)
2) The schematics in the examples are all composed of main pages with
the transistors and diodes being subpages. There is no obvious (to me
the new user) way of making the link so the transistors appear on the
schematic. Examples are presumably meant for new inexperienced users,
and as such should work flawlessly.
3) There are no examples of projects for use with the gEDA project manager.
4) I know it is easier for the developer to run ./configure at the root of
each package, but there ought to be a way to only do it once for the whole
system when you are using Stuart's installer program.
5) There is really no good reason to rebuild and reinstall the symbols a
dozen or more times. It significantly adds to the build time.
Anyway, it seems to be running, and I will begin to explore the construction
of a project from start to finish. I'm sure that task will keep me quite
busy.
Thanks for the help, and inspite of the problems I had installing, please
know that I think you guys have done a magnificent jog thus far.
-Chuck Harris
Article: 77819This looks kind of interesting: http://comsec.com/wiki?UniversalSoftwareRadioPeripheral -JeffArticle: 77820
hi Yes i was not giving any constraints while running the design.Actually i have Quartus version 4.0 which does not provide the facility of Timing Optimization advisor.so could not use that facility. Now when i am giving the constraints as Fmax =100 Mhz & tsu,tco constraint as suggested by Ben,i get Timing violations.How do i remove the Timing errors?? If i reduce the value of Fmax, again i get correct output for Stratix EP1S10F780C5 but not for EP1S10F780C6. I have broken down the combinational path by inserting FF's also?? Another thing i am using Asynchronous memory in my design (Look up tables).Will that have a negative impact on the result when targeting to Stratix device??Article: 77821
Hi Michel,
> Another question when you say :
>
> "I had the same problems in modelsim and solved it by making the testbench
> wait for a 1/4 clock period after an edge before supplying the next input.
> You may need to reflect your real system more closely than 1/4 clock
> period
> if you have detailed timing specs."
>
> Does it mean that your design has an offset in constraint equal to
> 1/4 of the period clock ?
No - the design I was working on was not destined for actual hardware so I
simply used 1/4 of the clock period as a suitable value as a time buffer
between my clock edges and input data transitions.
I had a half_clock_period generic in my testbench and so I could simply say
for example:
wait until rising_edge(CLK);
wait for HALF_CLOCK_PERIOD/2;
-- supply new data now
To avoid the setup errors from the simulator.
If I had more detailed timing information relating to data coming from a
device upstream of the FPGA I would have to been more diligent with how long
I waited after each clock edge.....
Cheers,
Ken
Article: 77822
Moti a écrit :
> Hi all,
> My problem is more of a VHDL problem but...
> I need to create the following pyramid alike design.
>
> in my declarative part i need to declare the following signals :
>
[...]
>
> It seems to be a job for a "generate loop" but I dont know how can I
> declare N signals...?
> Any suggestions for a nice and elegant way for creating such a
> structure.
Hi
As far as I can see, you can't declare n signals in a concise & elegant
way unless you declare an array (which will be twice bigger than what
you need but should be optimized by the synthesis tool)
I don't think "generate" is what you need.
I would write:
...
in_signal : in std_logic_vector(n-1 downto 0);
out_signal : out std_logic_vector(n-1 downto 0);
...
type bidim_array is array (n-1 downto 0, n-1 downto 0) of std_logic;
signal reg : bidim_array;
...
process (rst, clk)
if rst = '1' then
reg (others => others => '0'); -- not sure of the syntax here
elsif rising_edge(clk) then
for i in 0 to n-1 loop
reg(i, 0) <= in_signal(i);
if i > 0 then
for j in 1 to i loop
reg(i, j) <= reg(i-1, j-1);
end loop;
end if;
out_signal(i) <= reg(i, i);
end loop;
end if;
end process;
--
____ _ __ ___
| _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
| | | | | (_| |_| | Invalid return address: remove the -
|_| |_|_|\__|\___/
Article: 77823Hello, I am using Actel Libero 6.0. I would like to decrease the slew rate of some of the outputs of my FPGA. I found an option in Designer PinEdit where the slew rate can be set low or high. Does someone have an idea of what means low or high? Are there any numbers (in ns) available somewhere? Is it programmable in ns? Is it possible to see the rise time on the simulation (I use ModelSim)? Will the fall time also be influenced? Is it possible to influence it separately? Thank you very much. Marie Van QuickelbergheArticle: 77824
On Mon, 17 Jan 2005 11:46:53 -0500, Chuck Harris <cf-NO-SPAM-harris@erols.com> wrote: >I want to go to Debian, but I am finding it hard to get excited about >ripping my system apart and starting over...If only there was a safe >and easy way to move from RedHat to Debian... The EDA vendors only support RedHat, so I'm sticking with it, whatever its faults. And, finally, after all these years, we now actually have a professional Linux distribution, that's not just put together by hackers. But I'll tell you what really pi**es me off about it - they now charge an *annual* subscription for it. I've been buying Windoze distributions for 20-odd years, and I've never once had to pay an annual subscription. I bought my current Win2K 4 years ago, and I can still download updates and security fixes for free. What exactly makes RedHat think that they can charge year-on-year for that? If they'd just asked me for a one-off $200 then I'd have paid it. I'm running FC2 now, despite having to download the whole thing. Rick
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Compare FPGA features and resources
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