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Yes I have synthesized and placed and routed two times one time at 50 MHz and on time at 80 MHz. At each time, the .ucf file has been adapted to one of these two frequencies.. MichelArticle: 77776
> At 80 MHz, after my reset phasis, I see two kinds of warnings : > > 1. X_FF SETUP Low VIOLATION ON I WITH RESPECT TO CLK > 2. X_FF HOLD High VIOLATION ON I WITH RESPECT TO CLK > > appearing at each period of the simulation and the outputs of my > design aren't defined (all reds).. > > My problem is that the timing report detects no errors so I don't know > where to search. > > Does somebody has an advice to resolve these warnings > or pointers to have more informations about SETUP TIMING > or HOLD TIMING ??? Make sure that in your testbench you are not toggling input signals too close to your clock edges. Since you are doing a post par timing simulation (using an sdf file or similar I assume?) your TB must reflect the real world more closely and ensure that a suitable time-gap is present between clock edges and your input signal transitions. I had the same problems in modelsim and solved it by making the testbench wait for a 1/4 clock period after an edge before supplying the next input. You may need to reflect your real system more closely than 1/4 clock period if you have detailed timing specs. HTH, KenArticle: 77777
Anyone know of a device that makes implementing USB Host mode as painless as something like the FTDI chips? I need to hang a couple of USB Host ports on a V2P. No, I don't want to implement the USB functionality within the FPGA, those logic resources are far too valuable. Ideally, I'd like a simple single-chip solution that requires almost zero work to get up and going. I do control what devices will plug into this, so it doesn't need to be as intelligent (and/or complex?) as a full-blown USB framework on a PC. Thanks -MartinArticle: 77778
Martin <0_0_0_0_@pacbell.net> wrote: > Anyone know of a device that makes implementing USB Host mode as painless > as something like the FTDI chips? I need to hang a couple of USB Host on > ports a V2P. > No, I don't want to implement the USB functionality within the FPGA, those > logic resources are far too valuable. Ideally, I'd like a simple > single-chip solution that requires almost zero work to get up and going. > I do control what devices will plug into this, so it doesn't need to be as > intelligent (and/or complex?) as a full-blown USB framework on a PC. The cypress SL811HS can play the host or guest role on an USB bus, but for a USB bus, a lot of other software layers needed. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 77779
Hi, I have a problem with Forward-Annotating multicycle, false path constraints from Synplify Pro 7.7.1 to Quartus 4.2 . I have given all the multicycle and false path constraints to Synplify Pro. It is being taken by Synplify and writing to design.tcl file also. The same design.tcl file i am using for porting constraints to Quartus. Whatis happening is in the netlist output given by Synplify, some of the multicycle/false path destination registers have become combo logic(i really don't know why?), and being ignored by Quartus. In fact, there are some valid multicycle registers, terminated by (or through) that combo logic. But the destination register, is not forward annotated by Synplify. Since Quartus sees only a combo logic, and not able to find the destination register(which is the actual multicyle path), its ignoring my assignments. This gives me a lot of timing violations also. There are more than 100s of such multicycle registers, so manually searching and changing to correct registers, is not an easy task, and bound to mistakes. Have anybody encountered these types of problems? Please help me solve this issue. Thank you,Article: 77780
Thanks Ben, I'll take what you've said on board. Rog. "Ben Twijnstra" <btwijnstra@gmail.com> wrote in message news:7KJGd.103182$yn4.870@amsnews03-serv.chello.com... > Hi Roger, > >> Does anyone know what the basic costs are of doing an Altera HardCopy >> cycle? If, say I had a Stratix EP1S40 design that I wanted to make using >> HardCopy, would there be an initial set cost then a low cost per device? > > Yep. There's an NRE for the conversion process and the protos, then a > greatly reduced price per production device. Note that the HC1S devices > are > not all 100% equivalent to their EP1S counterparts - try to migrate your > design to a HC1S part in Quartus first. > >> If so what would the costs be? > > Contact your local Altera salesperson for this. There's no price list for > these projects. > > Best regards, > > > > Ben >Article: 77781
Martin wrote: > Anyone know of a device that makes implementing USB Host mode as painless as > something like the FTDI chips? I need to hang a couple of USB Host ports on > a V2P. > > No, I don't want to implement the USB functionality within the FPGA, those > logic resources are far too valuable. Ideally, I'd like a simple > single-chip solution that requires almost zero work to get up and going. > > I do control what devices will plug into this, so it doesn't need to be as > intelligent (and/or complex?) as a full-blown USB framework on a PC. > Yes, I heard Atmel has something under development/sale. Intended for a limited functionality, they are intending to deliver you some binaries according to your microprocessor and interface. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 77782
Grégory Mermoud wrote: > It works. That's fine. Thank you a lot guy. Nice to hear that. Which suggestion did you use? BretArticle: 77783
Minchuan Wang wrote: > Hello all, > > I'm a student, I didn't have any synthesis experience before, currently I > need to perform VHDL to EDIF netlist format. The netlist file should be > only limited to some specific resource, for example it contains only LUT > after mapping, or only AND gates or NAND gates before mapping. > > I already tried two synthesis tools, Xilinx XST and Synopsys Design > Compiler. I can successfully got netlist in EDIF format. However, by > checking user guide, I could not find how to constraint resource to a > specific set of primitives in both XST and Synopsys DC. Does anyone know if > this is possible? For XST, the set of primitives is defined by the selected device (project type). Xilinx has nothing to gain from offering tools that allow you to synthesize into an arbitrary set of primitives, since the point of XST is to target only Xilinx devices. That said, it is possible to restrict the output somewhat. You can disable RAM, Mux, or Shift register extraction. This is described in the online documentation (Constraints Guide). You can also force blocks to synthesize into a LUT, but the partitioning into LUTs then becomes manual. To map into only AND or NAND gates, for example, you should look for a synthesizer geared toward ASIC design rather than a (freebie) FPGA synthesizer. > > Thanks in advance > > SiminArticle: 77784
Bret Wade wrote: > Grégory Mermoud wrote: > >> It works. That's fine. Thank you a lot guy. > > > Nice to hear that. Which suggestion did you use? > > Bret I edit my macro by using xdl !Article: 77785
Rich Grise wrote: >>Pkg-config does live on my system, but it does nothing interesting >>because there are no .pc files on my RH9 system. AFAIK there never were. >>I have compiled numerous packages, and gEDA is the first I have found >>that requires pkg-config. Further, your detection of gtk2 is the only >>package in gEDA that ./configure misses. Until I built my first version >>of gEDA, PKG_CONFIG_PATH wasn't even set on my machine. (I cannot prove >>it, but I don't think it is set by any RH9 system) > > > Here's part of why I don't like Redmond^H^H^H^HHat: > richgrise@thunderbird:/opt/gEDA/Source/glib-2.4.8 > $ cat /etc/slackware-version > Slackware 10.0.0 > richgrise@thunderbird:/opt/gEDA/Source/glib-2.4.8 > $ uname -a > Linux thunderbird 2.4.26 #6 Mon Jun 14 19:07:27 PDT 2004 i686 unknown unknown GNU/Linux > richgrise@thunderbird:/opt/gEDA/Source/glib-2.4.8 > $ find / -name "*.pc" -print 2> /dev/null | wc > 120 120 4470 > richgrise@thunderbird:/opt/gEDA/Source/glib-2.4.8 > $ ls -l /var/log/packages/gtk* > -rw-r--r-- 1 root root 10282 2004-06-26 09:13 /var/log/packages/gtk+-1.2.10-i386-3 > -rw-r--r-- 1 root root 45775 2004-06-26 09:13 /var/log/packages/gtk+2-2.4.3-i486-1 > richgrise@thunderbird:/opt/gEDA/Source/glib-2.4.8 > > I'd never heard of .pc files until I stumbled onto this thread, and I've > been a Slacker for a number of years. > > But I have heard that Redmond^H^H^H^HHat changes configurations from what > works out of the box, such that you have to use Redmond^H^H^H^HHat RPM's > or it won't install right. There are Slack precompiled packages, or at > least they come with an install script that results in a binary and > configs that are the same as if you'd run ./configure, make, and install > from source. From what I've heard, RH doesn't do it that way. They modify > everything. > > This is much too close to the Gates of hell for comfort, for me. > > Thanks, > Rich > I have done some digging on my system, and found that the only use of pkg-config is in gui applications that use the gtk* system. I did some manual page reading and found that pkg-config is a reworked version of a utility that used to be called gtk-config. Ok, here's the rub: pkg-config is an attempt at making it easier to rebuild packages. It gives you somewhat useful information about the various compile and link options used in building a compliant package. But outside of gtk based gui applications, *nobody* uses it. And here's what is wrong with pkg-config. It has a built-in structure of paths to the various .pc files that are used to describe the system. The decision on what paths to incorporate in pkg-config is made by the install part of the "./configure, make, make install" sequence used to build pkg-config. It bases the paths on where it was originally aimed at installation. But it would appear that there is no documented way of asking the utility pkg-config what its default search paths are! And it would also appear that there is no system wide configuration file for pkg-config that allows you to tell it what directories to look in for .pc files. Just the kludge PKG_CONFIG_PATH, which, like LD_LIBRARY_PATH, is intended for test builds *ONLY*; things like checking to see if a new version of a library creams your system. Never for distributed packages! Now, why doesn't *my* pkg-config work. Well, a quick look shows me that my version was built on December 17th, 2004. I was futzing around with an earlier version of the gEDA suite around then. I wanted to see if I could run a trial design from schematic to pc layout. Because of the problem I had with gSCHEM linking up to transistor symbols, I tried rebuilding the system using the some mechanism or other, I forget now. Well, when I rebuilt the system I must have allowed the fool thing to install its own version of pkg-config over my native version. Only problem is the version was installed based in my home directory, so pkg-config's default search paths are based in /home/chuck/gEDA, which doesn't point to any useful .pc files. PHBBBBBT!!! I really hate it when folks use nonstandard stuff in distributions!!! -Chuck OBTW, Rich, when I first started linux it was with Yggdrisle's Slackware linux. My problem was *their* distribution couldn't be built from source because they put everything in the wrong places. They broke the many "#include ../../../../../../../foo.h" references that are endemic to unix programs. With RedHat, everything was where it belonged. I could build everything from sources without a hitch. As time passed, Slackware got smart and fixed their distribution, and RedHat got lazy and fixed everyone elses programs to match their file system layout ....sigh! I want to go to Debian, but I am finding it hard to get excited about ripping my system apart and starting over...If only there was a safe and easy way to move from RedHat to Debian...Article: 77786
Hi all, My problem is more of a VHDL problem but... I need to create the following pyramid alike design. in my declarative part i need to declare the following signals : signal reg1 : std_logic ; signal reg2 :std_logic_vector (1 downto 0); signal reg3 :std_logic_vector (2 downto 0); .. .. signal regN :std_logic_vector (N-2 downto 0); afterwards I need to connect them as follows : if rising_edge (clk) then reg1 <= in1; reg2(0) <= in2; reg3(0) <= in3; ... regN(0) <= inN; reg2 (1) <= reg2 (0); reg3 (2 downto 1) <= reg2 (1 downto 0); ... ... regN (N-1 downto 1) <= reg2 (N-2 downto 0); end if; -- outputs -- out1 <= reg1; out2 <= reg2 (1); out3 <= reg3 (2); ... ... outN <= regN (N-1); It seems to be a job for a "generate loop" but I dont know how can I declare N signals...? Any suggestions for a nice and elegant way for creating such a structure. I will appreciate any help. Thanks, Moti.Article: 77787
All: Proceed with extreme CAUTION! Stratix-2 Hardcopy is offered in two flavors: 1. One that is pin compatible with the FPGA but doesn’t offer significant die-size and price reduction and 2. The other that has a larger die size reduction (i.e. cost reduction), but does not maintain pin compatibility with the standard FPGA. This kind of incompatibility between Altera’s FPGAs and their Hardcopy cousins is prevalent across product families. Across many devices in the Stratix family for instance, there exists a mismatch (between the standard FPGA and the Hardcopy version) in memory blocks, user I/Os and number of PLLs. These constraints can significantly hamper the ‘conversion’ process and present customers with nasty surprises at a critical juncture. The net result is higher development costs, unit cost and delayed time to market. AustinArticle: 77788
"Moti" <moti@terasync.net> schrieb im Newsbeitrag news:1105981750.674974.162130@z14g2000cwz.googlegroups.com... > signal reg1 : std_logic ; > signal reg2 :std_logic_vector (1 downto 0); > signal reg3 :std_logic_vector (2 downto 0); > reg1 <= in1; > reg2(0) <= in2; > reg3(0) <= in3; > It seems to be a job for a "generate loop" but I dont know how can I > declare N signals...? Use a 2D array like this. type my_array is array(N downto 0) of std_logic_vector(N downto 0); signal my_pyramid is: my_array; Regards FalkArticle: 77789
Brian Dam Pedersen wrote: > Michael Schuster wrote: >> Uwe Bonnes wrote: >> >> >>>Ise works quite a long way. Calling >>>XST from ISE is dead slow, due to a Linux kernel bug. However you can't >>>use the programming tools talking to the hardware. >> >> I tried to install the ise 6.3 with wine, but it didn't work. Do you have >> some hints? (Using SuSE 9.2 prof) >> >> Michael > > The key to doing this is to install the vc6 support package on wine - > see my page <shameless plug> http://www.danbbs.dk/~kibria/xilinx.html > </shameless plug> for details. I'm currently running a 6.3 webpack with > no problems (other than configuration as usual) using wine. On SuSE 9.1 > I did this (very simple): > > 1) Install the binary dec. 1 distribution from www.winehq.com > 2) Install the support package as described on my page (no need to > manually override the windows version for the newest wine). > 3) Install the webpack using the self-extracting archive > > And it has been working ever since. > YES! It works! Supererb! Thanks for your hints! Michael -- Remove the sport from my address to obtain email www.enertex.de - Innovative Systemlösungen der Energie- und ElektrotechnikArticle: 77790
Hi, I have a Verilog project created through the Quartus II 4.1 GUI under Windows. I am trying to build it (analyze, synthesize, fit, etc) using the Windows command-line quartus_<name> tools. Is it possible to reuse the project files such as qpf and qsf with the quartus_map, quartus_fit, etc tools? I don't see any way to pass them in. Do I have to figure out the command line equivalents for every setting in each file's corresponding qsf? Would it be easier to generate a TCL script from the GUI and then use the quartus_sh TCL interpreter instead? I am looking for the fastest way to do this. Thank you, VladanArticle: 77791
In article <jighu0hfup9bj6sp9tbin91d25uecke1lk@4ax.com>, Nick <char-DONTBUGME-les@YY.iiedotcnam.france> wrote: >>Don't bother wasting the board space or design space on this. If you >>actually are paranoid enough that the threat of a $1M-100M lawsuit >>against someone who pirates your design is insufficient security, use >>a Cyclone II, Virtex II/IIPro, or Virtex 4, with their encrypted >>bitfile loading options. > >I just need to sell a fair security to my boss. The copyright is the >best protection IMHO, but he wants something more. Well, that's >something more and it sounds strong enough for me. The cost is minimal >compared to switching to a new device. Do the math. This will take at least $2-5k of design time (its something else to verify, test, include on the board, etc), and an extra $4/part in production cost. For protection which I could assign an undergraduate class to subvert. And which would be amusing, for sh*ts and giggles, to even write a tool to automatically bypass for Altera's reference code. This simply fails on a cost/benefit basis: I can understand using a chain made of bubblegum wrappers to lock something up. Sometimes bubble-gum chains are appropriate security. I just can't understand PAYING so much for the bubblegum-wrapper chain. And given that it is a bubble-gum wrapper, why not just use an LFSR instead of DES/3DES: its' much smaller and cheaper, and in the end, provides the same level of nearly-nonexistant security. Or just don't bother at all. -- Nicholas C. Weaver. to reply email to "nweaver" at the domain icsi.berkeley.eduArticle: 77792
If you want more information on using the PicoBlaze core, Xilinx has an application that comes with the PicoBlaze. It is a UART RTC. Essentially it connects to your PC through a serial port and allows the PC to control a Real Time Clock in the FPGA. This outputs an alarm on one of the outputs. There is another appnote at http://www.dulseelectronics.com/products/prod_seb3.html The appnote is titled Circuit Cellar Appnote. This appnote goes over the design of a PicoBlaze system for controlling all the resources on Dulse Electronics' SEB3 board (i.e. SRAM, LEDs, pushbuttons, LCD, etc.), but can be easily adapted to your own board. The source code can also be downloaded. My suggestion would be to use one of these appnotes (Xilinx or Dulse Electronics) and modify them a bit at a time until you get used to them and then do your own design. Note that the PicoBlaze is not programmable in C. It has a limitation of 1K instructions of code and is programmed in assembler. Philip Nowe www.dulseelectronics.com "Enzo B." <enzo_br@virgilio.it> wrote in message news:E49Gd.410095$b5.19829133@news3.tin.it... > Thanks for your replies. > I've (recently) seen there isn't possible to compile the Oregano System's > 8051 core with the ISE because it is written for another compiler. > I think it's possible to use it on Xilinx devices, but not without > modification. And I don't know how modify it. > > As I've read, the PicoBlaze is a soft core written purposely for Xilinx > FPGA > devices : requires much lower resources and is faster if compared with > another core. But how I can start to use it? In particular, what software > tools I need? Exists a small evaluation kit (or similar)? > > Another question : I've searched an 8051-compatible core because I have > experience with 8051 & derivates, a C compiler, some routines, etc. and > maybe (?) I can use this as a starting point. > I haven't idea of how much can be hard to put an entire 8051 on a FPGA, > but > if this is more over my possibilities, can I start by putting only the cpu > (with registers but without program ROM and data RAM) and adding an > external > program rom to the FPGA? Is this more simple? > > Thank you for any suggestion. > > Enzo > > ~ ~ ~ >> >> Good morning, >> >> >> >> I'm a beginner with FPGA. >> >> I've found an 8051 IP core here : http://oregano.at/ip/ip01.htm , and >> >> want to put it in a Spartan 3 FPGA like XC3S50 or XC3S200 (they have >> >> impressive number of LUT, and I suppose it's possible). >> >> Now, how I can do this ??? >> > >> > Just do it. Setup a new project, add the files, compile. >> > But if you want a powerfull uC in a Xilinx FPGA, you better go for the >> > famous KCPSM (xapp213). Its a very nice thing, much faster than any >> > 8051 clone and MUCH smaller!!! >> > >> > Regards >> > Falk >> >> No, you can't just do it with this 8051 core. It has some >> internal/external RAM/ROM modules that you will have to replace with >> BlockRAMs. Not hard to do, but you do say you are a beginner. >> >> Also, this 8051 requires more LUTs than the XC3S200 has. You will need >> at least an XC3S400 unless you want to devote some time to optimization >> and floorplanning. >> >> As suggested, using the Xilinx PicoBlaze is a better solution. But if >> you are truly just beginning with FPGAs, then I suggest you also take a >> look at http://www.xess.com/appnotes/webpack-6_3-xsa.pdf. >> >> >> -- >> ---------------------------------------------------------------- >> Dave Van den Bout >> XESS Corp. >> PO Box 33091 >> Raleigh NC 27636 >> Phn: (919) 363-4695 >> Fax: (801) 749-6501 >> devb@xess.com >> http://www.xess.com >> > >Article: 77793
> Anyone know of a device that makes implementing USB Host mode as painless as > something like the FTDI chips? I need to hang a couple of USB Host ports on > a V2P. > > No, I don't want to implement the USB functionality within the FPGA, those > logic resources are far too valuable. Ideally, I'd like a simple > single-chip solution that requires almost zero work to get up and going. > > I do control what devices will plug into this, so it doesn't need to be as > intelligent (and/or complex?) as a full-blown USB framework on a PC. > Atmel has the AT43USB380 OTG controller. This runs the USB host stack on an embedded micrcontroller and presents an API to the main processor which runs a library with the device classes. The library is delivered in object code only, so you will have to use a known architecture, or convince the Atmel USB group to support your choosen architecture. The AT91M40800 or the AT91R40008 are good chips to run the device classes on. Another limitation is the supported device classes. I think the most populoar classes are Mass Storage, HID and printer which are supported. CDC has been discussed some time ago, but I have no updated status. -- Best Regards, Ulf Samuelsson. Ulf at atmel dot com These comments are intended to be my own opinion and they may, or may not be shared by my employer, Atmel Nordic AB.Article: 77794
Has anyone come across an FPGA board with RF Front end at 2.4 GHz? or any 2 development kit (FPGA and RF Front end kit), matching to each other ? Any help is appriciated. Thanks NiravArticle: 77795
> > Does anyone know what the basic costs are of doing an Altera HardCopy > > cycle? If, say I had a Stratix EP1S40 design that I wanted to make using > > HardCopy, would there be an initial set cost then a low cost per device? > > Yep. There's an NRE for the conversion process and the protos, then a > greatly reduced price per production device. Note that the HC1S devices are > not all 100% equivalent to their EP1S counterparts - try to migrate your > design to a HC1S part in Quartus first. > > > If so what would the costs be? > Atmel has a similar program called ULC and that can be used regardless if it is Altera/Xilinx or whatever. You need to supply design data, test vectors and an order. If the design does not verify, using the test vectors, the customer does not pay anything, The ULC may or may not involve an NRE depending on technology and/or business level. -- Best Regards, Ulf Samuelsson. Ulf at atmel dot com These comments are intended to be my own opinion and they may, or may not be shared by my employer, Atmel Nordic AB.Article: 77796
hello all my current project requires that I build a Ultra160 SCSI interface controller that will act as an bus Initiator I'm think of implementing the protocol logic in a Virtex II FPGA .. is this feasible to do ? ...as any of you used a FPGA as a SCSI controller or know where I can get some information ? any information is much appreciated Thanks DennisArticle: 77797
I hate to reply to my own posts, but I think I may have found a solution, so I'll post it here for the sake of completeness. The following command will do a full compilation while taking into account the project files generated by the GUI: quartus_sh --flow compile <name of QPF> -c <name of desired revision>Article: 77798
On Tue, 11 Jan 2005 08:31:36 -0800, "Symon" <symon_brewer@hotmail.com> wrote: > >The point I think the author was trying to make was that if someone used the >diodes (and by definition the metal connections) to clamp a badly terminated >high speed bus, the repeated clamp current, albeit brief but in excess of >(say) 12mA, could cause a failure in time. Even though the average clamp >current was far below the 12mA you mention. > >> Now, if you intend to zap the pin with repeated capacitive discharges >> of 10,000 V backed by several 100 pF, that may be a different story. >> But I have not seen anything like that in real life. >> ESD damage occurs usually on the bare device, before it is soldered to >> a pc board. > >Indeed, as I said, ESD is something different, and well understood. I was >just curious about designs where the diodes are relied on to repeatedly >clamp over/under shoots. The article implies that the diode/metal >connections are there *only* to protect against a few ESD zaps in a >lifetime, not repeated stress caused by bad bus design. Which is something I >didn't know! Diode failure mode is typically short circuit, unless energy follow-through is sufficient to blow bonding wires or bonding pads open circuit. The latter is seldom the case in impedance-limited circuits. RLArticle: 77799
Hi, Austin. IMO, the most important patent Xilinx filed in the field is 5068603. It covers tons. However, I still need more info on the HardWire 1 and 2 families. Thanks, Bill austin wrote: > Bill, > > Why didn't you say you were looking for prior art? > > Consult uspto.gov and do a search for xilinx, hardwire, etc. > > I am sure our IP lehal folks filed something! > > Best of luck with your endeavour (invention). > > If there is something you wish to discuss with Xilinx, I am gappy to > direct you to th4e right folks, > > Austin > > Austin > > bill@viasic.com wrote: > > Hi, Austin. > > > > Thank you for your description of the three families. This confirms > > what I've heard before. I've checked out about the first 200 links > > yielded by Google when searching for 'xilinx hardwire'. Every one is > > about the most recent gate-array based family. The first two families > > seem to be hard to track down. > > > > My patent laywer is asking me for public documents on the first two > > families, since these are considered strong prior art in the structured > > ASIC market. Unfortunately, these families were gone before the web > > took off, so there was never any on-line docs, so Google hasn't helped > > me. Of course, the devices themselves can still be found, and that's > > technically enough. > > > > Thanks, > > Bill > >
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