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RobJ wrote: > Klaus Schleisiek wrote: >> I'm talking battery operated missions here. Yes, I am interested in >> 10 mWatts savings. >> > > I think your best bet then is to get an FPGA eval board and run some > experiments. Not with your real design. Just build a design with a > bunch of counters running at different rates. Then try a) vs. b) and > measure the actual core current consumption. You've got me curious > now. If you do it please post your results. > > Rob After poking around a little I've come to these conclusions: 1. I don't know enough about the details of FPGA power consumption to even comment on it. 2. FPGAs are not a good choice for very-low-power battery-operated applications. Bowing out of this thread. RobArticle: 77151
Hello all: I am sorry for troubling you for something this trivial, but I am new to EDK. I have instanced a generic sdram controller for a MicroBlaze on a Spartan 3. The problem is that the refresh is not functioning. The memory buss is totally quiescent except when reads or writes are occurring. I am sure there is some initialization command or signal I am overlooking. Thanks, FayetteArticle: 77152
Hello, When I try to synthesize OPB_ZBT controller its asking for a library common_v1_00_a. When I checked the EDK folder I found there are two folders with that name. One of which is in the compiled models directory and the other in pcores directory. I copied both these into my working directory and tried to synthesize it but it still gives me the same error message. ERROR:HDLParsers:3317 - c:/testdesigns/opb_zbt/opb_zbt_controller.vhd Line 53. Library common_v1_00_a cannot be found. ERROR:HDLParsers:3014 - c:/testdesigns/opb_zbt/opb_zbt_controller.vhd Line 54. Library unit common_v1_00_a is not available in library work. ERROR: XST failed I am not sure if this is even the correct way to go about it. I think I am missing something obvious. Can you point me out in the right direction? Thanks Harish avrbasic wrote: > set up compile scripts and run tools from shell or commandline. > attempting to load them to project navigotor is likely to cause problems. > similar things exists with LEON3 system > > it compiles with no problem from script but is not possible to load into > project navigator, PN simple messes up with the libraries. > > Antti > > > "Harish" <harish.vutukuru@gmail.com> wrote in message > news:1103852073.061564.154760@f14g2000cwb.googlegroups.com... > > Hello all, > > > > How can we simulate the EDK IP cores in ISE? I created a new project in > > ISE and copied the vhdl files that comes with EDK onto a new file and > > tried to synthesize it. However the synthesis failed as the library > > referred to in the design was not seen by ISE. Can anyone tell me how > > to overcome this? > > > > Thanks > >Article: 77153
"Purvesh" <purveshkhona@yahoo.com> wrote in message news:1104002898.931299.49860@z14g2000cwz.googlegroups.com... > Hi All, > > Anyone implemented SATA/SAS with FPGAs. Seems that neither rocketIO nor > MGT in stratix GX are capable of handling OOB signalling of SATA/SAS. > > My question is : Which serdes did you use to work around the OOB > problem ? > > -Purvesh > http://xilinx.openchip.org/ChipScope/ scroll down and look. SATA OOB with real SATA chip - on VP20 board no external components rocketIO direct to SATA. can be done. AnttiArticle: 77154
Hi all, I need to build a 120 cells FIFO (cell = 24 bits) and I wondered what is the best way of doing it.. My FIFO should work like a shift register, i.e. - each write strobe it should load a new value to the 1'st cell and discard the 120'th value. I'm using the Xilinx Spartan 2e FPGA. The write strobe frequency is 1Hz - so frequency is not an issue. p.s. - I'm fimiliar with the CORE GENERATOR FIFO but I dont know if it is the best solution. Thanks in advance, Moti.Article: 77155
"Purvesh" <purveshkhona@yahoo.com> wrote in message news:1104001659.687813.300080@z14g2000cwz.googlegroups.com... > Hi, > > I don't have hard nos. either but definately clock running all the time > is going to consume maximum power. As far as clock gating is concerned, > its is definately worth the effort if you want to have battery > operation with FPGAs, but that means that you won't be able to use > clock routing resources since you will be generating gated clock. Be > extremely careful in this case - I would recommed running formal > verification tool and also run gate level simulations with SDF. > > If you don't mind waiting, I believe Stratix II or Virtex IV is going > to have true gated clock support. If you use clock enable, you are only > saving flop switching power. > > -Purvesh > FPGA's usually have some external dedicated clock inputs. What about gating those (externally) with a gate? Then it's true gating. JeroenArticle: 77156
Hi there. I've been programming using a parallel byteBlaster-type lead, attatched to an old 486, via a network connection to my laptop. This is because my laptop is devoid of parallel or serial ports (oh, the foresight). I hear I can't use USB to Parallel adaptors (arse!) and I can't imagine me finding a pcmcia parallel adaptor (though I could make one..?) and looking on alteras site reveals they want about £150/$300usd for their USB baster. Nads to that - Anyone know of anywhere selling a usb programmer for sensible (hobbyist) amounts? Or a way out of my situation? Thanks. -Alan / randomdudeArticle: 77157
hi there, i have got a problem regarding simulation of my verilog source with gnu toolz. the source file compiles properly with iverilog. but when i invoke the 'vvp', it dosn't output a 'vcd' file required for gtkwave. i m running these gnu eda tools in native windows environment and not in linux/cygwin. the commands that i give are - iverilog -o my.vvp my.v vvp my.vvp -vcd without any vcd file output. what can be the possible problem? TIA Shreyas KulkarniArticle: 77158
I have encountered strange inconsistensies in simulation results of my design. First of all, the simulation results drastically change if a dummy port is connected or disconnected to an output of some logic block (my design is done fully in BDF). While simulating, suddenly, after I changed a name of one signal, other signal's values have drastically changed. I couldn't trace the problem but after I have disconnected an output port from that signal it suddenly started working as before and its values actually appeared on the disconected output port and showed up in the simulation. I have a 4 bit register that clocks-in a value. For some reason, again after modofying unrelated block, the register stopped clocking-in the value and its output was always stuck at 0000. After endless hours I just decided to add another register in parallel to see if it will clock-in the data. To my surprise, the original register suddenly started working again. I am currently stuck with another strange problem and feeling a little frustrated... Has anyone expereinced anything similar ??? Is there something wrong I might be doing ?Article: 77159
Hi all, I activate row R1 and Bank B1.After time Trcd read from Bank B1 and Column C1.Suppose next I want to read from the same row R1 but different Bank B2 should I precharge the row then issue a new Active command or issue a read command with Bank B2 or should I issue new Active command with Row R1 and bank B2 then issue read command. Please throw light on it. Thanks in advance... Raghavnedra.SArticle: 77160
Dear all,
I am a newbie in FPGA. I only know verilog coding, and may you guys
help me to kick start on learning FPGA? like which book to read, and the
basic "toys" or equipment (like howto connect fpga with a desktop)
thanx in advance!
Carson
Article: 77161Raghavendra wrote: > Hi all, > I activate row R1 and Bank B1.After time Trcd read from Bank B1 and > Column C1.Suppose next I want to read from the same row R1 but > different Bank B2 should I precharge the row then issue a new Active > command or issue a read command with Bank B2 or should I issue new > Active command with Row R1 and bank B2 then issue read command. > > Please throw light on it. The way to think about it is that each bank is a separate DRAM chip which can be closed (precharged) or open on a particular row. So, the fact that you switch to the same row in a different bank is completely irrelevant. What matters is the state of that bank. Now what probably could have confused you is that a lot of simple SDRAM controllers (such as previous version from XESS) only track the currently active bank, but AFAIR the lastest actually track each bank and can avoid reopening the row when not strictly needed. One of the nice benefits of this is fast access for multiple memory streams (sequential memory accesses) as long as they hit in different banks. Hope that helped, TommyArticle: 77162
Hello, 1.Can anyone provide me with some AMBA AHB VHDL models?or is there anyone who has designed one? 2. What is role played by wrapper??? Thanks and regards PraveenArticle: 77163
Hi In order to connect a DDR memory component (not the DIMM) to spartan-3 - Is it better to use DCI on spartan-3 pins ? If so is there an example ? - What sort of termination is required at the memory end. - Is there a reference schemetic ? Thanks SumitArticle: 77164
> Hi > > In order to connect a DDR memory component (not the DIMM) to spartan-3 > > - Is it better to use DCI on spartan-3 pins ? If so is there an example > ? > - What sort of termination is required at the memory end. > - Is there a reference schemetic ? > > Thanks > Sumit > Read XAPP200. I've build my own controller on base of that in XAPP and it works fairly well at 266 MHz.Article: 77165
Hello to all, I've followed a Hogenauer architecture. Can anyone help me out that what clock frequency should be provided for a 3-ordered CIC decimator, I've used 3 combs and 2 integrator stages in my design alongwith a rate changer. Thanks, SamiaArticle: 77166
Hi all, any hint why the built in web-update is dying at 84% download? Best Regards MarkusArticle: 77167
Jim, I'll put a new title on this. The internal logic is running off a lower voltage, so yes, it must manifest itself in some fashion. How it makes itself known is that with 100 mV of ground bounce, you now have more jitter internal to the core than you would have had with 100 mV on a higher voltage core device. More jitter means that the timing margins may have to be larger (more slack), or you have to manage the ground bounce, clock jitter, etc. to a greater extent than you may have had to in the past. This is a major headache, as the speed of the devices only gets faster, yet the jitter (may) get larger -- the two are incompatible! A great deal of design work is going into the management of jitter in our devices (ie differential clock trees), as well as prediction of jitter for a given application (software tools). Right now, the only way to guess at how much jitter will be present is to assume a worst case asynchronous multi-clock design environment with less than "best practices" bypassing, and IO's operating at the SSO limits. This worst case assumption leads to numbers that may be far too conservative for your application (but at least we errored on the side of caution, and better performance is achievable). Use of LVDS IO's, synchronous clock domains, switching some logic on altenate clock phases, best bypassing and decoupling practices, etc. are all able to provide even better jitter numbers than the worst case ones. Differences of 10:1 from your case to the worst case is not unusual. Contact your local Xilinx FAE for details and help on the subject of jitter, if you are designing high performance (tightly constrained) FPGAs. Austin Jim George wrote: > -snip- > > I think this question is more about the worse noise margin of > low-voltage devices than thier MTBF. I've heard the same question being > asked by designers of military products of 1.5V FPGAs like the V2Pro. > Any info? > > -JimArticle: 77168
Sumit, Check out Application XAPP768c "Interfacing Spartan–3 Devices With 166 MHz or 333 Mb/s DDR SDRAM Memories" which can be accessed after registering for it on: http://www.xilinx.com/memory Cheers, Shalin- do_not_reply_to_this_addr@yahoo.com wrote: > Hi > > In order to connect a DDR memory component (not the DIMM) to spartan-3 > > - Is it better to use DCI on spartan-3 pins ? If so is there an example > ? > - What sort of termination is required at the memory end. > - Is there a reference schemetic ? > > Thanks > Sumit >Article: 77169
Hi all, I think I remember sombody writing here, that the MicroBlaze gets an MMU in the next release. Anybody out here knows any details ? Cheers & thanksArticle: 77170
Markus Meng wrote: > Hi all, > > any hint why the built in web-update is dying > at 84% download? I don't know your case, but mine (Xilinx XC95144XL) once had the problem of dying in the middle of downloading. The problem was that the power supply voltage was not correct. It was caused by a faulty low drop voltage regulator. vax, 9000 > > Best Regards > MarkusArticle: 77171
vax, 9000 wrote: > Markus Meng wrote: > >> Hi all, >> >> any hint why the built in web-update is dying >> at 84% download? > I don't know your case, but mine (Xilinx XC95144XL) once had the problem > of dying in the middle of downloading. The problem was that the power > supply voltage was not correct. It was caused by a faulty low drop voltage > regulator. Sorry I misread your question. Please discard my post. vax, 9000Article: 77172
I've a general question regarding PicoBlaze IP core from Xilinx: If I'm using PicoBlaze as a controller on my design: Who programs the FPGA which contains PicoBlaze? Normally e.g. a uP loads the FPGA with the neccesary configuration file. But if the FPGA itselfs is the controller (e.g. PicoBlaze), how do I get the configuration file into the FPGA? Silly question, isn't it? Thanks for your help MartinArticle: 77173
Martin wrote: > I've a general question regarding PicoBlaze IP core from Xilinx: > If I'm using PicoBlaze as a controller on my design: Who programs the > FPGA which contains PicoBlaze? > Normally e.g. a uP loads the FPGA with the neccesary configuration > file. But if > the FPGA itselfs is the controller (e.g. PicoBlaze), how do I get the > configuration file into the FPGA? > Silly question, isn't it? > > Thanks for your help > Martin You can use a xilinx PROM that the FPGA will read on power-up.Article: 77174
Hi All, I am in search of some good references on FPGA implementation of Order-Statistic CFAR (constant false alarm rate) detector in radars. If anyone has any idea or information, please send-in the references. Thanx in advance.
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Compare FPGA features and resources
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Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z