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Messages from 77225

Article: 77225
Subject: SDRAM
From: "Fayette" <tortoisedundee@yahoo.com>
Date: Fri, 31 Dec 2004 00:15:33 -0500
Links: << >>  << T >>  << A >>
Hello,

I have instanced a generic sdram controller for a MicroBlaze on a Spartan 3.
The problem is that the refresh is not functioning. The memory buss is
totally
quiescent except when reads or writes are occurring. Is there is some
initialization command or signal I am overlooking.

Thanks,

Fayette



Article: 77226
Subject: Re: Xilinx + Modelsim *Please Help Tonight*
From: Vikram Pasham <Vikram.Pasham@xilinx.com>
Date: Fri, 31 Dec 2004 00:17:46 -0600
Links: << >>  << T >>  << A >>


Ricky Stern wrote:

>  ** Warning: (vsim-SDF-3440) c:/ecc/lab1test/ecc_multiply/ecc_sim.sdf:
> Failed to find any of the 85 instances from this file.
> # ** Warning: (vsim-SDF-3442) c:/ecc/lab1test/ecc_multiply/ecc_sim.sdf: Try
> instance '/multiply/nlwblockroc'. It contains all instance paths from this
> file.
> # ** Error: (vsim-SDF-3445) Failed to parse SDF file
> "c:/ecc/lab1test/ecc_multiply/ecc_sim.sdf".
> #    Time: 0 ns  Iteration: 0  Region: /multiply  File: ecc_sim.vhd

These errors indicate you are not using correct combination of post annotated
VHDL file and SDF file. You might have multiple versions of VHDL and SDF file
which aren't co-relating i.e. not generated from the same design.
Also, what version of Xilinx tools are you using?

Regards
Vikram


Article: 77227
Subject: Re: Quartus and Cyclone programming problem
From: Nick <char-DONTBUGME-les@YY.iiedotcnam.france>
Date: Fri, 31 Dec 2004 09:22:42 +0100
Links: << >>  << T >>  << A >>
I do not have the code for the week end but it begins like this

 PROCESS (clk, rst)
   BEGIN
     IF rst = '0' THEN	-- asynchronous reset (active low)
       state	    <= reset;
       oadr <= "00000000000000000000000";
       odat  <= "00000000000000000000000000000000";
       osel  <= "1100";
       counter	    <= 0;
       oled1	    <= '0';            -- light up when at 0
       oled2	    <= '0';
   ELSIF clk'event AND clk = '1' THEN	
-- here is the state machine

I came to the point of changing something in the state machine made
the led don't light up

Since the reset is asynchronous, it shouldn't be a clock related
problem, could it ?

Best regards, and thank you for your answer

Nick

On 30 Dec 2004 15:26:36 -0800, "Mike Treseler"
<mike_treseler@comcast.net> wrote:

>Sounds like a logic race.
>Maybe you don't have a clock input.
>Maybe you have a clock, but
>some inputs are not synchronizied to it.
>Consider posting your code.
>
>        -- Mike Treseler


Article: 77228
Subject: Inter FPGA communication
From: gordanic2003@yahoo.com.sg
Date: 31 Dec 2004 02:08:05 -0800
Links: << >>  << T >>  << A >>
Hi every1,

Can anyone teach me how to program in Handel-C to transmit the data
from the keyboard from 1 FPGA to another FPGA and display the key
pressed on the monitor of the 2nd FPGA?

It should be done using the 50 pins expansion header and input and
output.

I can transfer the ASCII codes from the 1st FPGA to the 2nd FPGA. But
how can the 2nd FPGA distinct between a single 'A' being pressed or
whether repetitive 'AAAAA's are pressed?

It is because while I can transfer the ASCII codes of a character but
there is no way to transfer out the key pressed/released status of that
character. 

I am very troubled by this.

Chen


Article: 77229
Subject: Xilinx ISE : How to make Modelsim reload when design changed ?
From: Mike Harrison <mike@whitewing.co.uk>
Date: Fri, 31 Dec 2004 12:31:36 GMT
Links: << >>  << T >>  << A >>
I've been experimenting with ISE Webpack, and have managed to create a simple schematic, and got the
output waveforms in modelsim, 
however what I can't figure out is how to get modelsim to reload the new data when I change the
schematic - 
After I change the schematic and do 'create schematic symbol', the only way I can get it to simulate
the new file is to close and re-launch modelsim - surely there is an easier way...? 'Restart'
doesn't seem to do it.

Article: 77230
Subject: Re: SDRAM
From: Mike Harrison <mike@whitewing.co.uk>
Date: Fri, 31 Dec 2004 13:06:06 GMT
Links: << >>  << T >>  << A >>
On Fri, 31 Dec 2004 00:15:33 -0500, "Fayette" <tortoisedundee@yahoo.com> wrote:

>Hello,
>
>I have instanced a generic sdram controller for a MicroBlaze on a Spartan 3.
>The problem is that the refresh is not functioning. The memory buss is
>totally
>quiescent except when reads or writes are occurring. Is there is some
>initialization command or signal I am overlooking.
>
>Thanks,
>
>Fayette
>
Are you sure the controller doesn't put the SDRAM into self-refresh mode between accesses ?


Article: 77231
Subject: Re: Xilinx ISE : How to make Modelsim reload when design changed
From: Mike Treseler <mike_treseler@comcast.net>
Date: Fri, 31 Dec 2004 05:54:37 -0800
Links: << >>  << T >>  << A >>
Mike Harrison wrote:

> After I change the schematic and do 'create schematic symbol', the only way I can get it to simulate
> the new file is to close and re-launch modelsim - surely there is an easier way...? 'Restart'
> doesn't seem to do it.

If the changes are already compiled,
try this from the modelsim prompt or .do file:

     restart -f;
     vsim test_mydesign;
     add wave *;
     run;


         -- Mike Treseler

Article: 77232
Subject: Re: Inter FPGA communication
From: Mike Treseler <mike_treseler@comcast.net>
Date: Fri, 31 Dec 2004 06:06:48 -0800
Links: << >>  << T >>  << A >>
gordanic2003@yahoo.com.sg wrote:

> I can transfer the ASCII codes from the 1st FPGA to the 2nd FPGA. But
> how can the 2nd FPGA distinct between a single 'A' being pressed or
> whether repetitive 'AAAAA's are pressed?
> 
> It is because while I can transfer the ASCII codes of a character but
> there is no way to transfer out the key pressed/released status of that
> character. 


Maybe your fpga is interfaced to a PC UART
and can't see the keyboard scan codes directly.

               -- Mike Treseler

Article: 77233
Subject: Re: Xilinx ISE : How to make Modelsim reload when design changed ?
From: "Gabor" <gabor@alacron.com>
Date: 31 Dec 2004 06:08:07 -0800
Links: << >>  << T >>  << A >>
If you're starting Modelsim from the ISE process view (e.g.
double click on "Simulate Behavioral Model") you are actually
starting Modelsim with a script that loads the design, compiles
it and runs the simulation (default for 1 microsecond, but this
is configurable in the ISE properties).
When you change a file inside ISE, make sure it is saved and
then rerun the script in modelsim.  I find the easiest way to
rerun the script is to click on the right pane of the main
Modelsim window and then use the up-arrow key to get
back the line that ran the script (something like "do
testbenchname.fdo")

This basically does the same thing as closing and re-running from
inside ISE, but without the added time of re-loading Modelsim.  It
also preserves your simulation options (like default radix and run
time),
but you'll need to save your waveform view between runs if you've
mad a custom signal list in the wave window.


Article: 77234
Subject: Re: Xilinx + Modelsim *Please Help Tonight*
From: "Ricky Stern" <knicks@speakeasy.net>
Date: Fri, 31 Dec 2004 11:29:14 -0500
Links: << >>  << T >>  << A >>
xilinx 5.3

I am using the post place and route to create a modelsim vhdl and sdf file 
that I named myself  so I am use I am using the right ones.

thanks

"Vikram Pasham" <Vikram.Pasham@xilinx.com> wrote in message 
news:41D4EF0A.A899ACB4@xilinx.com...
>
>
> Ricky Stern wrote:
>
>>  ** Warning: (vsim-SDF-3440) c:/ecc/lab1test/ecc_multiply/ecc_sim.sdf:
>> Failed to find any of the 85 instances from this file.
>> # ** Warning: (vsim-SDF-3442) c:/ecc/lab1test/ecc_multiply/ecc_sim.sdf: 
>> Try
>> instance '/multiply/nlwblockroc'. It contains all instance paths from 
>> this
>> file.
>> # ** Error: (vsim-SDF-3445) Failed to parse SDF file
>> "c:/ecc/lab1test/ecc_multiply/ecc_sim.sdf".
>> #    Time: 0 ns  Iteration: 0  Region: /multiply  File: ecc_sim.vhd
>
> These errors indicate you are not using correct combination of post 
> annotated
> VHDL file and SDF file. You might have multiple versions of VHDL and SDF 
> file
> which aren't co-relating i.e. not generated from the same design.
> Also, what version of Xilinx tools are you using?
>
> Regards
> Vikram
> 



Article: 77235
Subject: Re: Newbie looking for multiported-RAM to interface to a Spartan-III
From: "Marc Randolph" <mrand@my-deja.com>
Date: 31 Dec 2004 08:48:30 -0800
Links: << >>  << T >>  << A >>

savingsandloan wrote:
> Hi,
>
> I'm working on a buffer-type application using a Spartan-III that
> requires six bytes of data to be read and written to memory at rates
of
> about 100MHz. I was wondering two things:
>
> 1) Whether a Spartan-III is fast enough to send the required timing
> signals for a multiported memory at this speed. If not, I'll probably
> have to look into spending more money on a Virtex.

The S3 should have no problem 100 MHz, even if it were DDR.  S3's are
more or less comparable to Virtex 2's in terms of capability.

> 2) What companies sell multiported ram? Any suggestions will help.

Assuming you have already verified that you can't fit your data in the
FPGA block RAM (even going with a really large Spartan III maybe
cheaper, lower power, and smaller, than a small S3 + external RAM), the
list is quite long and varies depending on exactly what style of
multiport you desire.

This looks to be a pretty complete list, although I wouldn't
necessarily trust the classification of one vendor into one memory type
like they have:
http://www.interfacebus.com/memory.html  

Have fun,

   Marc


Article: 77236
Subject: Re: Altera NIOS II/Stratix II vs Xilinx Products
From: Tommy Thorn <foobar@nowhere.void>
Date: Fri, 31 Dec 2004 21:33:32 GMT
Links: << >>  << T >>  << A >>
DerekSimmons@FrontierNet.net wrote:
> If I'm considering buying the Altera NIOS Devlopment kit is there a
> similar Xilinx product with about the same price tag I should be
> considering?

I think your other questions have been fully answered, but as I was in 
exactly your situation let me fill in a few details.

First off, you need to consider the tools support.  If you're not going 
to pay for tools or live off time-limited evaluation version, then pay 
close attention to which devices are supported by the free (gratis) 
tools.  AFAIK, the EP2S60 is not supported by the free Quartus.

I'm still using the excellent Nios Development board, Cyclone edition, 
but wanted to move up.  The two choices were: (like you) Altera's Nios 
Dev kit, Stratix II edition, or the Xilinx ML401:

Hopefully you're using a fixed font at this point :-)


		Altera		Xilinx		X/A
Price		$1000		$500*		1/2 price
FPGA		EP2S60		Virtex4 LX25	~ similar size&speed
Free tools	No		No
DRAM		16MiB SDR	64MiB** DDR	4x size,2x speed
SRAM		1MiB async	1MiB ZBT	ZBT is ~2-3 speed
VGA		No***		24-bit/50MHz
CF		Yes		Yes
Ethernet	100Mbps		Gigabit
USB		No		Host&Client
RS232		2 ports		1 port

(*) Add ~$100 for programming cable.
(**) 256MiB with a board rework.
(***) Lancelot VGA,2xPS/2,audio out is ~$300

I'll let you be the judge, for me the choice was easy though I like the 
Quartus tools much better and would love to play with Stratix II.

Tommy

Article: 77237
Subject: Free tools
From: "Roger" <rogerwilson@hotmail.com>
Date: Fri, 31 Dec 2004 23:39:03 GMT
Links: << >>  << T >>  << A >>
It's a while since I looked at free tools but when I did, Altera's Web 
version of Quartus was a great deal. I've checked back and it appears that 
the Web version is time limited now, is this correct?

If so, does anyone know of any free tools from the main FPGA manufacturers?

TIA.

Rog.



Article: 77238
Subject: Dead FPGA?
From: milne@egenera.com
Date: 31 Dec 2004 18:38:18 -0800
Links: << >>  << T >>  << A >>
Recently I assembled a board containing (among other things)
a Spartan-IIE 300.  Unfortunately, after I powered on the board
I discovered that both the 1.8V and the 3.3V power rails were
shorted to ground.  After much head scrating, I realized that the
FPGA (in the PQ208 package) was rotated 90 degrees... (sigh).

I removed the FPGA and re-installed it in the proper position.
Now the 1.8V and the 3.3V rails are no longer shorted to ground,
but the resistance between the two rails is only 4.4 ohms and the
1.8V rail is reading about 2.9V.  The regulator put out 1.8V after
I had removed the FPGA before putting it back on again the right way.

Is there any hope for this device, or should I just give up and
replace it?  Does this sound like a known failure mode if the
power and ground pins on the device have previously been connected
to the wrong potential?  Any other ideas?
Thanks in advance for any replies.

-Ewan


Article: 77239
Subject: Re: Free tools
From: "Subroto Datta" <sdatta@altera.com>
Date: Sat, 01 Jan 2005 03:32:42 GMT
Links: << >>  << T >>  << A >>
The Quartus Web Edition is a free tool even today. The time limited license 
can be regenerated at any time by the user for another 6 month period. The 
reason the Web Edition license is kept time limited is that it allows Altera 
to know who is actively using their product. The Quartus tools both Web 
Edition and Full Subscription products from version 4.0 onwards take the 
user to the Altera license generation website to get a new license, when the 
existing license expires.

Hope this helps.
- Subroto Datta
Altera Corp.


"Roger" <rogerwilson@hotmail.com> wrote in message 
news:rqlBd.2593$A85.167@newsfe5-gui.ntli.net...
> It's a while since I looked at free tools but when I did, Altera's Web 
> version of Quartus was a great deal. I've checked back and it appears that 
> the Web version is time limited now, is this correct?
>
> If so, does anyone know of any free tools from the main FPGA 
> manufacturers?
>
> TIA.
>
> Rog.
>
> 



Article: 77240
Subject: Re: Dead FPGA?
From: "Bob" <nimby1_notspamm_@earthlink.net>
Date: Sat, 01 Jan 2005 06:25:19 GMT
Links: << >>  << T >>  << A >>

<milne@egenera.com> wrote in message
news:1104547098.154759.31260@z14g2000cwz.googlegroups.com...
> Recently I assembled a board containing (among other things)
> a Spartan-IIE 300.  Unfortunately, after I powered on the board
> I discovered that both the 1.8V and the 3.3V power rails were
> shorted to ground.  After much head scrating, I realized that the
> FPGA (in the PQ208 package) was rotated 90 degrees... (sigh).
>
> I removed the FPGA and re-installed it in the proper position.
> Now the 1.8V and the 3.3V rails are no longer shorted to ground,
> but the resistance between the two rails is only 4.4 ohms and the
> 1.8V rail is reading about 2.9V.  The regulator put out 1.8V after
> I had removed the FPGA before putting it back on again the right way.
>
> Is there any hope for this device, or should I just give up and
> replace it?  Does this sound like a known failure mode if the
> power and ground pins on the device have previously been connected
> to the wrong potential?  Any other ideas?
> Thanks in advance for any replies.
>
> -Ewan
>

Replace the FPGA, and any other device that uses the 1.8V supply. The FPGA
was obviously internally shorted between VCCINT (1.8V) and whichever pins
were hooked up to the 3.3V supply (VCCO and/or VCCAUX).

Bob



Article: 77241
Subject: Free IP-Core for FPGA Config from MMC-Cards
From: "avrbasic" <avrbasic@hotmail.com>
Date: Sat, 1 Jan 2005 12:18:58 +0100
Links: << >>  << T >>  << A >>
Hi all,

I have decided to make some presents to all in form of IP-Core donations:
http://www.opencores.org/projects.cgi/web/mmcfpgaconfig

There is working/tested IP-Core that allows FPGA configuration from MMC
Card. The IP as submitted to opencores does not support SD-Cards, but is
otherwise tested and useable. Tested with MMC, XC9536XL as config controller
and VP20 as target tot be configured.

Similar IP-Core (SD/MMC config IP-core for Altera) from an commercial vendor
costs around 1900EUR !

Antti






Article: 77242
Subject: Re: CIC filter implementation using FPGA
From: "Sam" <samiayunus1@yahoo.com>
Date: 1 Jan 2005 03:41:19 -0800
Links: << >>  << T >>  << A >>
Thanks for your reply.
I have used 256 rate changer (i.e. it is of 8bits ), This divided clock
will be provided to comb stages.
will it be suitable for my design if I provide 44.4khz frequency at the
integrator stages.
Can you please explain the clock frequency, data rate in detail.
Regards,
Sam


Article: 77243
Subject: Re: Altera NIOS II/Stratix II vs Xilinx Products
From: "Marc Randolph" <mrand@my-deja.com>
Date: 1 Jan 2005 05:41:32 -0800
Links: << >>  << T >>  << A >>
Tommy Thorn wrote:

> Hopefully you're using a fixed font at this point :-)

Howdy Tommy,

Unfortunately I'll bet the majority don't now-a-days, but it was still
readable!

> 		Altera		Xilinx		X/A
> Price		$1000		$500*		1/2 price
> FPGA		EP2S60		Virtex4 LX25	~ similar size&speed
> Free tools	No		No
> DRAM		16MiB SDR	64MiB** DDR	4x size,2x speed
> SRAM		1MiB async	1MiB ZBT	ZBT is ~2-3 speed
> VGA		No***		24-bit/50MHz
> CF		Yes		Yes
> Ethernet	100Mbps		Gigabit
> USB		No		Host&Client
> RS232		2 ports		1 port

I think there is a minor error in one line of your chart... If you
don't use the funny math from either company, the 2S60 has ~50k
four-input look-up tables, compared to ~21k LUTs on the LX25.  So
assuming all other things being equal (which they aren't because of all
extras that each have surrounding the lookup tables), I'd consider the
2S60 to be roughly 2x larger (very roughly).

Using the fudge factors from each company, it's 60k vs. 24k.

I'm sure they would *both* argue about which one is faster though...
the truth is that you need to target your design to each to find out
for sure.  Despite Altera's hyperactive chart generation department, I
think there are lots of applications that the Virtex-4 would be faster
than the Stratix II.

Happy New Year,

   Marc


Article: 77244
Subject: Re: Free IP-Core for FPGA Config from MMC-Cards
From: Sylvain Munaut <tnt_at_246tNt_dot_com@reducespam.com>
Date: Sat, 01 Jan 2005 15:02:44 +0100
Links: << >>  << T >>  << A >>
avrbasic wrote:
> Hi all,
> 
> I have decided to make some presents to all in form of IP-Core donations:
> http://www.opencores.org/projects.cgi/web/mmcfpgaconfig

Well, that's original ;)


Thanks and happy new year ;)


	Sylvain

Article: 77245
Subject: Re: Free tools
From: "Roger" <rogerwilson@hotmail.com>
Date: Sat, 01 Jan 2005 14:03:28 GMT
Links: << >>  << T >>  << A >>
Thanks, great news. I'm an occasional user of programmable logic but prefer 
to use Altera when I can so free tools are a big factor for me.

Roger
(RW Concepts)

"Subroto Datta" <sdatta@altera.com> wrote in message 
news:uRoBd.540$Vj3.313@newssvr17.news.prodigy.com...
> The Quartus Web Edition is a free tool even today. The time limited 
> license can be regenerated at any time by the user for another 6 month 
> period. The reason the Web Edition license is kept time limited is that it 
> allows Altera to know who is actively using their product. The Quartus 
> tools both Web Edition and Full Subscription products from version 4.0 
> onwards take the user to the Altera license generation website to get a 
> new license, when the existing license expires.
>
> Hope this helps.
> - Subroto Datta
> Altera Corp.
>
>
> "Roger" <rogerwilson@hotmail.com> wrote in message 
> news:rqlBd.2593$A85.167@newsfe5-gui.ntli.net...
>> It's a while since I looked at free tools but when I did, Altera's Web 
>> version of Quartus was a great deal. I've checked back and it appears 
>> that the Web version is time limited now, is this correct?
>>
>> If so, does anyone know of any free tools from the main FPGA 
>> manufacturers?
>>
>> TIA.
>>
>> Rog.
>>
>>
>
> 



Article: 77246
Subject: Re: PCBs for modern FPGAs.
From: Sylvain Munaut <tnt_at_246tNt_dot_com@reducespam.com>
Date: Sat, 01 Jan 2005 15:20:31 +0100
Links: << >>  << T >>  << A >>
Hello Symon,


I'd like more informations about the stackup you use, what are the thickness of the layers/prepreg ?
What are the consequences of not having the top layer referenced to a 'near' plane ?


Thanks,

	Sylvain


PS: Note I wrote both to the news group and bcc to you to make sure you see this answer,
as the topic is not recent.


Symon wrote:
> All,
> 
> After reading and contributing to a few interesting threads recently about
> PCBs for FPGA designs, I thought I'd post about the technology I've been
> using for the past 3-4 years. My job involves getting a lot of high density
> circuitry into a small space, and so awhile back I decided to use microvias
> (laser drilled vias) to pack more stuff onto my boards. The surprising thing
> was that the boards worked out cheaper for my application than if I hadn't
> used this method.
> 
> I'll explain why, but you might first want to download the picture at
> 
> http://www.fpga-faq.org/caf_pics/layer_1_2.gif
> 
> My stackup is ten layers, like this:-
> 
>  1) signal
> 
>  2) signal
> 
>  3) ground
> 
>  4) signal
> 
>  5) signal
> 
>  6) ground
> 
>  7) signal
> 
>  8) signal
> 
>  9) ground
> 
> 10) signal
> 
> 
> 
> There are laser drilled microvias between layers 1 and 2. The only other
> vias are through vias, i.e. from layer 1 through all layers to layer 10.
> This means there's still only one mechanical drilling process during
> manufacture. What you can see in the picture you downloaded is how to route
> out all but four of the signal pins on banks 2 and 3 of a V2PRO in a FG676
> package without using any through vias, just microvias between the two
> layers, blue and light green. The track and gap distance is 4mils or 100um.
> With this technology you can go 8 rows deep on a 1mm pitch BGA without using
> through vias.
> 
> In no particular order, here are the advantages.
> 
> It's no problem at all to put microvias in a pad. The microvia is just a
> 2mil deep pit that fills with solder, unlike a through via which must be
> plugged to stop the solder wicking away.
> 
> You can use fewer signal layers because the signal paths out from the FPGA
> aren't baulked by through vias.
> 
> You can use fewer (or no) power layers because it's possible to fit a lot of
> bypass caps on the back side of the board from the FPGA, with through vias
> direct from these to the FPGA power balls. (In the picture you can see the
> ground (green) balls and Vcco (yellow) balls. By the time this board went
> out, there were two through vias for each power ball.) With a conventional
> board, the through vias don't leave space on the backside to fit (m)any
> caps.
> 
> You get to have a decent ground plane(s) for your BGA devices, not one
> turned into Swiss cheese by a myriad through vias. Bye-bye ground bounce.
> 
> You gain board area all over the back side of the board simply because
> there's less space used by the vias from the topside.
> 
> Compared to a through via, the SI of a microvia is much better. After all,
> it's only 1/30th the length of a through via.
> 
> The components can be closer together, reducing SI issues.
> 
> 
> 
> I always follow some rules when routing FPGAs this way. Like these:-
> 
> Draw lines from the four corner balls to the very centre of the part. Don't
> let any layer 1 or 2 traces cross these lines, it always seems to screw
> things up.
> 
> Be prepared to put much more effort into the PCB. This doesn't work well
> unless you're prepared to sit down with the layout person and swap pins on
> the FPGA as you route things up to align with other components on the board.
> For diff pairs be prepared to swap Ps and Ns. You can fix up the inversion
> inside the FPGA.

Article: 77247
Subject: Re: Altera NIOS II/Stratix II vs Xilinx Products
From: Tommy Thorn <foobar@nowhere.void>
Date: Sat, 01 Jan 2005 18:54:18 GMT
Links: << >>  << T >>  << A >>
Marc Randolph wrote:
>>		Altera		Xilinx		X/A
>>Price		$1000		$500*		1/2 price
>>FPGA		EP2S60		Virtex4 LX25	~ similar size&speed
...
> I think there is a minor error in one line of your chart... If you
> don't use the funny math from either company, the 2S60 has ~50k
> four-input look-up tables, compared to ~21k LUTs on the LX25.  So
> assuming all other things being equal (which they aren't because of all
> extras that each have surrounding the lookup tables), I'd consider the
> 2S60 to be roughly 2x larger (very roughly).
> 
> Using the fudge factors from each company, it's 60k vs. 24k.

Oops, you're right.  I was thinking of the EP2S30 that will _normally_ 
be in the Altera board.  The EP2S60 is ~ 2x the size.

Good catch, thanks.

Tommy

Article: 77248
Subject: Getting started with Xilinx CPLD
From: rjs@friend.ly.net
Date: 1 Jan 2005 11:25:25 -0800
Links: << >>  << T >>  << A >>
Hello,

I have a need for something faster than a microcontroller and decided
on using logic IC's to do it. Well I don't need to say why I next
decided to use programable logic instead. I've have never used a PLD
before. After visting Xilinx web site I ordered the CPLD Design Kit to
get started.

Lets see know, all I have to do is program my logic schematic into one
of these CPLD devices! Wow, after that I might find the state machine
entry of intrest. And... after I'm an advanced user I could learn a new
language called VHDL. Now wait a minute... How come the Xilinx tutorial
starts with the advanced VHDL first? OK, I'll skip over to the next
tutorial "State Machines". Well, I don't need that yet. OK, the next
tutorial uses schematic entry. Oh no, this tutorial requires the
previous tutorials. It seems to me that Xilinx has it all backwards on
how one starts using programable logic for the first time.

Next I bought a book on ebay "Digital Electronics - Using the Xilinx
XC95108 CPLD" copyright 2001. This is perfect!! Its first CPLD example
uses a 3 input AND gate and a 3 input OR gate. The problem is that it
uses Xilinx foundation 1.5 which is nothing like ISE 6.3i that I have.
So my question is where can I get Xilinx foundation 1.5 ???


Article: 77249
Subject: Re: Getting started with Xilinx CPLD
From: "avrbasic" <avrbasic@hotmail.com>
Date: Sat, 1 Jan 2005 20:44:53 +0100
Links: << >>  << T >>  << A >>
<rjs@friend.ly.net> wrote in message
news:1104607525.385297.51090@z14g2000cwz.googlegroups.com...
> Hello,
>
> I have a need for something faster than a microcontroller and decided
> on using logic IC's to do it. Well I don't need to say why I next
[snip]
>So my question is where can I get Xilinx foundation 1.5 ???
forget that!

Just instal ISE WebPack, start schematic editor, place your logic, and run
synthesis!
Then to make it really work you only need to assing pins to correct pads
thats it.

Antti
www.openchip.org






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