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Hi Nick, It sounds like your reset is sometimes close to a clock edge, and hence skew on it leads to some of your flops coming out of reset one cycle (or more) before others. That leads to a bad reset, where the ones that come out of reset early grab a bad next-state value based on a circuit state where some FFs are still being held in reset, and some aren't. You should use Quartus' recovery and removal timing analysis feature to check that the reset will bring all flops out of reset in the same clock cycle, well away from an active clock edge. A good way to ensure that happens: - If all your logic is +ve edge-triggered, register your async reset signal with a series pair of -ve edge triggered FFs. This avoids metastability, and creates a synchronized reset that now changes well away from active clock edges. Quartus will automatically route this reset signal on a global network to minimize its skew. Its still best to run a recovery and removal analysis though, since this is a timing constraint, and in my opinion you should always check all your static timing constraints. Hope this is helpful, Vaughn Betz Altera v b e t z (at) altera.com [remove spaces and use proper @ to reach me] "Nick" <char-DONTBUGME-les@YY.iiedotcnam.france> wrote in message news:nkeft0p16he6k60fb2fnae6tood9gh3tt2@4ax.com... > On Sat, 01 Jan 2005 20:03:24 -0600, hmurray@suespammers.org (Hal > Murray) wrote: > > >>I have seen startup issues with state machines as well. > >>Using synch state machines and asynch resets. Using > >>Quartus 4 spX. A couple thoughts from what I read on Altera's > >>website and just trying stuff. Make sure your state > >>machine is using one-hot encoding, and define > >>all states. This may solve random startup issue. If > >>not try using a 3rd party tool like leonardo. (I think > >>this ultimately fixed our issue. > > > >Async resets are evil. They are, well, asynchronous. Using > >a one-hot state machine doesn't solve the problem. It might > >reduce the probability (size of window), maybe even enough so > >you won't see it easily. Are you running a few lab tests or > >do you need a solid system? > > > >This gets discussed here frequently. The usual context is > >the global reset signal that the hardware provides. It's slow > >enough so that even if it is synchronous at the pins, it's probably > >several clocks of prop time on high speed systems. (and hence > >logically asynchronous) > > > Well, basically for my test I use a switch for the reset, if it's at 1 > the state machine should start, if it's at 0 the state machine should > reset. I would really like to have a fairly long reset that I can > control for my tests. And my clock is only 32 MHz > As long as the design isn't too big it works. And after a certain > amount of complexity it doesn't anymore > > Thank you for your answer, I shall try using Leonardo, and i'll keep > you informed. > > Happy new year to you all > > NickArticle: 77401
Hi Nicolas, The FLEX 10K family only has one register in each IO cell. That means that with a bidirectional IO like you have, where both the dataout signal and the OE signal come from registers, only one register can be implemented in the IO cell itself. This won't affect functionality, but will increase your Tco for whatever signal doesn't go into the IO cell. To get the best Tco, you can lock the other register (that doesn't get moved into the IO cell) to the LAB next to the IO cell, if the fitter hasn't done that automatically. Stratix, Cyclone & beyond all have more registers in the IO cell, so you won't run into this issue with them. Vaughn "Nicolas Matringe" <matringe.nicolas@numeri-cable.fr> wrote in message news:1104942792.104162@quito.magic.fr... > Hello all > I have a perfectly reasonnable design with bidir pins, written in the > purest VHDL style: > lberr_b <= lberr_b_out when lberr_b_oen = '1' else 'Z'; > (as an example, I have a handfull of such outputs) > (note that lberr_b_out and lberr_b_oen are both registered and are not > used anywhere else in the design) > > I turned the "Fast Output Register" option on for these outputs and > Quartus tells me :"Warning: Can't pack non-peripheral register > local_if:local_if_inst_1|lberr_out to bidir I/O pin lberr_b -- output > register and TRI or OPNDRN primitives cannot both fan-out" > > What's wrong there? Is it a feature the Flex10K is missing? > > -- > ____ _ __ ___ > | _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le - > | | | | | (_| |_| | Invalid return address: remove the - > |_| |_|_|\__|\___/Article: 77402
> > Austin, > > > > I don't know where you're getting these surge numbers from. To my knowledge > > Altera never quoted surge currents that high for 2S180s. > > Bellnix Power supply guide, TI power supply guide, ST power supply > guide...basically your power supply parnters. So, all I can conclude is > that Altera told their power vendors what the start up surge was. > > http://dkc3.digikey.com/PDF/Marketing/FPGA_Altera.pdf > http://focus.ti.com/lit/ml/slyb113/slyb113.pdf > http://www.bellnix.com/fpga/P-M-R-G1.pdf > > ... > > all state 16 amperes. So if you didn't tell them, who did? If I am an > engineer, and I need to design a power system, I would be using these > guidelines. The TI and Bellnix app notes list 16 amperes for the 2S180, but don't state that it is surge current, for the simple reason that it is not. The digikey app note does imply this is a power-up current, which is wrong, and we will tell them to fix that. The current numbers in the app notes are "reasonable worst-case" *total* current draws during operation. That means dynamic power + leakage power, during operation of a high-speed, high-utilization design with a high, but not extreme, switching probability per clock cycle for registers & combinational logic. Dynamic power dominates. Since dynamic power is such a strong function of what you're doing with a device, we recommend that you use the Altera Early Power Estimator, or even better, the Quartus Power Analyzer to get an accurate number for your specific design, as I've previously explained. > > The TI App note you quoted appears to be a miscommunication, since those > > numbers are much too high to be either surge or leakage currents. > > > > Very effective miscommunication there. Better go talk to all your power > vendors and let them know that they all quoted the wrong numbers. I > have supplied you with the list above, so you're welcome. The poor communication on our part was that we did not ensure that what the current draws in these app notes represent (reasonable worst-case total power during operation) was well explained. We thought it would be clear that that was the case, but certaintly this exchange shows that it was not clear to you Austin, so we'll make sure the app notes get updated to be as immune to misinterpretation as possible. Interestingly the equivalent TI app note for Xilinx lists the smaller and slower Virtex2Pro family as requiring up to 10 A of Vccint current. It doesn't say what that current is. I think a good guess would be that it is the "reasonable worst-case" total Vccint current during operation for a large V2Pro device, although it seems your guess would be surge current. http://focus.ti.com/lit/ml/slpb008a/slpb008a.pdf The 2S180 has 1.8X the logic capacity of the largest Virtex2Pro device (the 2VP100). The 2S180 also runs 50% faster, on average. So you get ~2.7X the processing power in the 2S180 that you do in the 2VP100. If I assume that Xilinx and Altera both defined "reasonable worst-case total power" in the same way (a big if, I'll admit), power in the largest V2Pro is 15 W (10 * 1.5) vs. the 19.2 W (16 * 1.2) for the largest Stratix II. So for 26% more power, I get 2.7X the processing power. Put another way, for equivalent processing capability, you only need 46% of the power in Stratix II that you do in V2Pro. This TI app note has no data on Virtex4 power, so I can't compare to Virtex4. > > The 5.3 A value is power-up current for worst-case silicon characteristics, > > at 85 C. Is your 3.3 A leakage number for the worst-case power process > > corner silicon at 85 C, > > Yes, it is. > > or just typical or unspecified silicon at 85 C? > > No, it is not. How about Vccaux power? The Xilinx web calculator lists a Virtex4 LX200 power on the Vccint supply of 661 mW -- 6X lower than the worst-case, 85 C number. It also lists a Vccaux power of 375 mW -- again typical silicon, 25 C. Is the 85 C, worst-case number 6X larger for that too, so the real leakage power dissipation is 6.2 W when you sum Vccint & Vccaux? Regards, Vaughn Altera v b e t z (at) altera.com [remove spaces and use proper @ to reach me]Article: 77403
Vaughn Betz a écrit : > Hi Nicolas, > > The FLEX 10K family only has one register in each IO cell. That means that > with a bidirectional IO like you have, where both the dataout signal and the > OE signal come from registers, only one register can be implemented in the > IO cell itself. This won't affect functionality, but will increase your Tco > for whatever signal doesn't go into the IO cell. Yes, I know all this (already got stung by this single IO register that did not show in the datasheet 6 years ago) What I don't understand is why Quartus refuses to put the output register in the IO when I ask it to do so (and put the input & tristate regs somewhere else) > Stratix, Cyclone & beyond all have more registers in the IO cell, so you > won't run into this issue with them. I'm stuck with a Flex10K on this project -- ____ _ __ ___ | _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le - | | | | | (_| |_| | Invalid return address: remove the - |_| |_|_|\__|\___/Article: 77404
Thanks Etem Tezcan, I am looking for some reference code of AHB. Can some one please give some reference where i can find it. Thanks and regards PraveenArticle: 77405
HI all,
I wanted to know about how refersh rate is calculated.Average
Refresh rate for 256Mb is 7.8u & for 128 Mb it is 15 us.I read in a
doc that its 64ms/No.of rows.I read in a document that 8 auto-refresh
commands can be posted to SDRAM to improve scheduling of tasks.
There are two timing parameters
1.Refresh to refresh command interval
2.Average periodic refresh interval.
How are they related.
Please somebody clear my doubt..
Thanks in advance,
Raghavnedra.S
Article: 77406Hi Klaus, Klaus Schleisiek wrote: > Can anybody give me hard facts on the power consumption ramifications > for the following two design styles: > > a) Fully synchronous design with appropriate clock enable signals for > "slower" clock domain areas of the design. > > b) Asynchronous design generating slower gated clock signals for those > slow clock domain areas of the design. > > In a), each flip-flop has to load the clock input capacitors on each > clock transition, even if the clock enable signal is false and that will > consume energy. But how much? > > In b), we are sure to conserve energy, but at the cost of a dramatic > increase in design complexity, because we have to use signal > synchronisation contraptions whenever we go from one clock domain to > another clock domain. > > Is the added complexity of approach b) really worth the power savings I > get out of it? > > :) > > Klaus Schleisiek > > kschleisiek AT XYfreenet.de > If you want to send me an e-mail, use above address and remove XY You might also want to do some "what-if" analysis using XPower. BrendanArticle: 77407
HI, I made the same mistake in miss-calculaiton when I moved to New York from Sweden. Life in the US is far more expensive that you think. Gas, electricity, tolls, federal, state, local, socialsecurity taxes adds up to a level very close to the ones in Europe, but the benefits are much less. Check out what you want, look for a house similar to the one you have, check the utility bills and compare it to what you have as well as how much extra you need to add to your insurnce, they all adds up at the end. BR, /FA On 5 Jan 2005 20:55:01 -0800, vbishtei@hotmail.com (vadim) wrote: >I have received a job offer from a company >in San Jose, California. The position title is: Test Development >Engineering. The salary offered is 67k/year with Relocation Assistance >and a Benefits package. I already have a 60k/year job in Toronto, >Canada as Applications Engineer. > >The San Jose job is closer to circuit-design which is an area I would >like to get into. > >I was told that the housing prices of Bay Area will make this salary >into a 50k equivalent of Toronto. So practically my "buying power" is >reduced. > >I have a dillema whether: >-Professional advantages of this position, closer to ciruit design. >-Working in Silicon Valley, the Mecca of HighTech. > >outweigh the offered salary ? > >Thanks in advance.Article: 77408
Jeff Cunningham wrote: > stockton wrote: > > Do anyone know of a rough percentage of the the FPGA resources that > > can be expected to be utilised before issues arise in trying to route > > the design? > > > > I have head that it is as low as 60% but am hoping that this is not > > the case. > > Big things like BRAMs and DLLs easily do 100% utilization. The critical > thing will be LUT utilization which, in my experience (xilinx) goes up > to 60% until you use the "disable register ordering" switch then you can > get over 90% at a slight speed hit. I agree with Jeff that with modern parts (V2Pro and newer) and latest tools, many designs should be able to achieve 90% LUT utilization. It does depend somewhat on the design (clock rate, number of clock domains, number of levels of logic, and how efficiently the logic gets placed) though, so if logic estimates show much over 80%, I'd make sure to run it all the way through the tools for a final confirmation. Lastly, my experience has been that that FF count is a poor indicator of projected device utilization. LUT utilization is nearly always higher, and often, considerably higher (I've seen ~25% in a few cases). Have fun, MarcArticle: 77409
In the old days, refresh just had to be completed to all banks in the overall refresh period, typically 64 milliseconds. With DDR SDRAM, there is a new requirement that comes from the use of the refresh command to enable correction in the internal delay-locked loops. Resetting the loops only during reset simplifies the job of reducing jitter or phase noise on the DQS pins during memory access. The two new requirements come from the two uses of refresh commands. 1. command interval is dictated by delay-lock loop characteristics. This is why you can only burst 8 refreshes at a time, whereas in older DRAM you could burst all 8K once every 64 milliseconds and still work. From a Micron datasheet explaining the JEDEC refresh interval requirement: "This maximum absolute interval is to allow future support for DLL updates internal to the DDR SDRAM to be restricted to AUTO REFRESH cycles, without allowing excessive drift in tAC between updates." 2. average refresh interval comes from the refresh requirement to make sure any bank waits no longer than 64 milliseconds between refreshes. This is the old requirement of 64 milliseconds / #banks. Regards, GaborArticle: 77410
hi there, i have been designing a pci target using spartan3 for some time. i m a new comer to this field and i have got some queries regarding the fpga configuration and its voltage requirements - the motherboard that i m going to use, has 5V connector for sure. so i suppose the i/o s are 5V. now the spartan3 specifies its VCCO as 3.3Vmax. can this configuration of 5V pci and 3V spartan3, work reliably? are there any added precautions to be observed? in the pci pinout, jtag pins are seperately specified. can i use these pins for configuration of the fpga? if so, can somebody suggest me a method/algorigthm/source code/software/link for this? has somebody used this before? in general, how can one address the jtag pins of pci target in windows or linux? what throughput can i expect from the data acquisition system that i m going to put on the pci target card? i will be simultaneously using a modem, sound card, ethernet card. will the operating system that i m going to use (windows or linux) have any bearing on the throughput? if yes, then if i program the card with its own operating system that is configured to work only with the acquisition card(i.e. if other pci cards are virtually rendered dead temperorily), will it improve the results? TIA, Shreyas KulkarniArticle: 77411
Shreyas Kulkarni wrote: > hi there, > > i have been designing a pci target using spartan3 for some time. > i m a new comer to this field and i have got some queries regarding > the fpga configuration and its voltage requirements - > > the motherboard that i m going to use, has 5V connector for sure. > so i suppose the i/o s are 5V. now the spartan3 specifies its > VCCO as 3.3Vmax. can this configuration of 5V pci and 3V spartan3, > work reliably? are there any added precautions to be observed? > There are plenty of references at xilinx.com about this. You will not like what you find out. > in the pci pinout, jtag pins are seperately specified. can i use > these pins for configuration of the fpga? if so, can somebody > suggest me a method/algorigthm/source code/software/link for this? > has somebody used this before? > in general, how can one address the jtag pins of pci target in > windows or linux? > The PC motherboard market being what it is (very very price sensitive)I will be surprised if you find any motherboard that connects these pins to anything. > what throughput can i expect from the data acquisition system that > i m going to put on the pci target card? i will be simultaneously > using a modem, sound card, ethernet card. As a target only you might get 20MBytes/sec if you are very lucky. > > will the operating system that i m going to use (windows or linux) > have any bearing on the throughput? if yes, then if i program the > card with its own operating system that is configured to work only > with the acquisition card(i.e. if other pci cards are virtually > rendered dead temperorily), will it improve the results? > TIA, > Shreyas KulkarniArticle: 77412
Hi > i have been designing a pci target using spartan3 for some time. > i m a new comer to this field and i have got some queries regarding > the fpga configuration and its voltage requirements - > the motherboard that i m going to use, has 5V connector for sure. > so i suppose the i/o s are 5V. now the spartan3 specifies its > VCCO as 3.3Vmax. can this configuration of 5V pci and 3V spartan3, > work reliably? are there any added precautions to be observed? You can't connect the spartan 3 pin directly to 5v. I've a board that works fine on all motherboards i've tried and that uses TI SN74CBTD16211 between all the pci lines and spartan 3 pins http://focus.ti.com/docs/prod/folders/print/sn74cbtd16211.html It basically "clamp down" the mother board 5V signal to 3.3v level. 3.3v level generated by the spartan3 are not raised to 5v but it's ok. For eg : you just tie the OE# to ground, VCC to 5V, and then uses A side for PCI and the B side for Spartan 3 (check the specs). > in the pci pinout, jtag pins are seperately specified. can i use > these pins for configuration of the fpga? if so, can somebody > suggest me a method/algorigthm/source code/software/link for this? > has somebody used this before? > in general, how can one address the jtag pins of pci target in > windows or linux? I don't think so. So far I've never seen theses accessible but they may be ... I would recommand another mechanism, more compatible with xilinx tools or xc3sprog ( // cable programmer for linux ) > what throughput can i expect from the data acquisition system that > i m going to put on the pci target card? i will be simultaneously > using a modem, sound card, ethernet card. Depends of a lot of thing ... First the usage all theses devices (or other devices on the PCI that you don't see because hidden in the chipset or on the motherboard) do on the PCI Bus. With the FPGA you can try to measure the "busy state" of the bus. Then it also depends on how your PCI target core works (how many cycle did he waste in pauses, does it support burst or force the master into retries, ... ) It will also depends on the way the master access the PCI bus, with single read/write, bursts, ... Finally it probably depends on others thing I don't think of now. > will the operating system that i m going to use (windows or linux) > have any bearing on the throughput? One would guess so ... But if both operating system support your hardware well, the os difference should not be much. BUT it will certainly depends on the way the driver for your card is written ... If you do a loosy job programming it then it will perform poorly. Basically, ensure what you do results in bursts ! > if yes, then if i program the > card with its own operating system that is configured to work only > with the acquisition card(i.e. if other pci cards are virtually > rendered dead temperorily), will it improve the results? Of course, if you don't do any other activity on the bus that will perform better but just not using thoses devices of disabling them would be enough, no need to write your OS ! It's a FPGA so if you already have the hardware (or any FPGA board with a PCI interface), you can do tests, see for yourself. For eg, count how many clock cycles the DEVSEL line is asserted during a fixed time (or clock cycle) and display it on some I/O, that should give a (rough ...) busy percentage of the bus. SylvainArticle: 77413
stockton wrote: > Dear All, > > I hope that you can help. > > I am looking at trying to fit a number of IP cores into a single > Xilinx FPGA, I have heard that it is not possible to completly utilise > all the FPGA resources (RAM, Logic Cells, DCMs etc ... ) because of > routing problems. > > Do anyone know of a rough percentage of the the FPGA resources that > can be expected to be utilised before issues arise in trying to route > the design? > > I have head that it is as low as 60% but am hoping that this is not > the case. > > I understand that it really does depend on what you put into the FPGA > but to only be able to utilise 60% on average seams a little poor to > me. > > Kind Regards > > Simon We test all of our IP Cores on a few Xilinx Development boards we have in house and are stuck with device sizes. We always have a small SoC that we attach our "Core to be tested" to. I have seen utilization of 98%++ specially when we make heavy use of ChipScope. As long as you stick with EDK based SoC and their 100MHz bus speed limitation, you are usually ok up 98% utilization. Best Regards, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and SynthesisArticle: 77414
Paul, Wow. 50 hardcopies. In a whole year (or two). Thanks for admitting the "non-starter" status of this. (We get > 50 design-ins per month with our FPGA's). And, "seamless risk free" is just a plain an outright misrepresentation. I know of a customer that had a serious issue, and was unable to meet their production ship dates (fact). Only reason we know is that they had to continue buying the FPGA (ours). Have fun in this business! Good luck! One less competitor for real FPGAs. Austin Paul Hollingworth wrote: > In the light of recent comments on this site relating to > Structured-ASICs in general and Altera and HardCopy in particular, I > would like to correct a few factual inaccuracies which may have crept > in. > > Our competition is apparently basing its decision not to follow our > lead into this market on its experience with a failed product from > years gone by. I would say two things about this. Firstly, technology > has moved on. In the 1990s, it was not possible to base the heart of a > complex system on an FPGA - they were too small. This has obviously > changed, such that a single FPGA can now cover over 80% of all ASIC > starts. Secondly, the increasing costs of ASIC NREs now represent a > considerable barrier to the use of ASICs - this was not the case in > the '90s, as NREs were typically less than $200K at that point. > Deciding not to do a Structured-ASIC product today on the basis of > experience from 10 years ago is a bit like a camera company deciding > not to produce a digital camera today because they tried it when > resolution was 300K pixels and nobody bought them! The financial > community is certainly not of the opinion that this is a > "non-starter". > > We have now completed over 50 HardCopy tapeouts and are running at a > rate of over 1 per week. We believe that this means that HardCopy is > currently leading the Structured-ASIC market in terms of tapeouts. The > rate of designs being booked is increasing, and our backlog indicates > that 2005 will see revenue tripling based on the designs that were > booked in 2004. The current version of HardCopy has been shipping for > exactly one year now, and its combination of seamless, risk-free > migration together with the ability to reduce power and increase > performance over the FPGA is unique in the industry. Clearly the > Structured-ASIC industry is new and relatively small at present. > However, like many of the significant players in the ASIC market, > Altera believes that it will grow strongly over the next few years, and > our design bookings confirm this. We are very happy to be alone in this > market. > > Paul Hollingworth > Altera Marketing >Article: 77415
Hello,
i know this is a rather stupid question, but i'm somewhat irritated.
I'm triing to send some data per Uartlite. For normal
characters/strings everything works fine, but if i try to send some
integers or long integers they aren't displayed.
(Short) example:
...
/* global definitions, no pointers */
Xuint32 interrupt_count = 0;
volatile Xuint32 jiffies = 0;
...
/* values incrementd during pit-isr, pit works, pit running at 100HZ
*/
void pit_timer_int_handler(void * baseaddr_p)
{
jiffies++;
interrupt_count++;
XTime_TSRClearStatusBits(XREG_TSR_PIT_INTERRUPT_STATUS);
}
...
main(){
/* string displayed correctly */
xil_printf("\r\nRunning Mainloop");
while(1){
sleep(2);
xil_printf("\nLoop");
/* here the values aren't displayed,but the "a"s and "b"s are displayd
*/
xil_printf("\n %l a", i_interrupt_count);
xil_printf("\n %l b", l_interrupt_count);
/* giving the arguments as pointers won't help either */
xil_printf("\n %l a", &i_interrupt_count);
xil_printf("\n %l b", &l_interrupt_count);
}
}
i have tried different compinations with "%d","%D","%l","%ul" or "%c"
as format-strings and different datatypes for the two variables
(unisgned, int, long, unsigned long).
i was looking at the xil_printf sources, too, to see what characters
after "%" are supported.
I'm using an uartlite at 9600 baud, 8 databits, no parity.
So, does someone might have an idea or hint what my mistake is?
Regards
Patrick
Article: 77416
Hi all
I have implemented a very easy memory with a few registers, where i can
store and also read values for and from my ALU:
I have got 2 questions:
1) The conv_integer procedure does not work here, I always get the
errormessage: no feasable subprogram entry for conv_integer. Any ideas whats
wrong here?
2) Finally this memory should be synthizeable for a Xilinx ML300 board. What
do I have to change that this will be alright?
Is there a documention available? I wasnt able to find one online, which
says me in a detailed way what constructs I can use!
Thanks for any useful hints
SD
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity memory is
generic (width : integer := 32);
port (clk : in std_ulogic;
rst : in std_ulogic;
inp : in std_ulogic_vector((2*width-1) downto 0);
addr: in std_ulogic_vector(3 downto 0);
wr : in std_ulogic;
rd : in std_ulogic;
outp: out std_ulogic_vector((2*width-1) downto 0)
);
end memory;
architecture rtl of memory is
type reg_type is array (0 to 3) of std_ulogic_vector((2*width-1) downto
0);
signal reg_file : reg_type;
begin
write : process(clk,rst,inp,addr,wr)
variable x_int : integer;
begin
if rst = '1' then
reg_file(0) <= (others => '0');
else
if clk'event and clk = '1' then
if wr = '1' then
reg_file(conv_integer(addr)) <= inp;
end if;
end if;
end if;
end process;
read : process(clk,rst,addr,rd)
begin
if rst = '1' then
outp <= (others => '0');
else
if clk'event and clk = '1' then
if rd = '1' then
outp <= reg_file(conv_integer(addr));
end if;
end if;
end if;
end process;
end rtl;
Article: 77417On Wed, 05 Jan 2005 12:06:48 -0700, Bret Wade <bret.wade@xilinx.com> wrote: >Daniel wrote: >> @Bret Thanks for the suggestion. Didnt know that its possible to fix the routing also within RPM macros. >> >> Are RPM macros usefull for design modules as large as my one (376 CLB Slices (752 FlipFlops, 260FG's), 8BRAMs and 1GlobalBuffer) or does this lead to problems with performance or even unstable workflows? I am working with larger RPMs than this, with some degree of success (cautiously expressed; the design is not yet complete) There *may* be problems with BRAMs and multipliers in RPMs. >Yes, large RPM macros can be used effectively. Multiple small RPMs can >be assembled with offsets defined by hierarchical RLOCs to assemble a >large RPM. Automatic placement of large RPMs can be a challenge so it >may be necessary to locate the macro. I believe that Ray Andraka has >posted on the subject of large RPMs in the past. You may want to Google >for that. There are problems using the floorplanner to create RPMs from smaller ones, mostly associated with tools issues (the floorplanner alone has two mutually incompatible understandings of RLOC_ORIGIN, the mapper moves the origin left by 1 location under some (apparently undefined) circumstances, the placer reports errors on some correct RLOC_ORIGIN constraints and silently deletes others altogether, and so on. http://www.shapes.demon.co.uk/files/crashme.zip contains a test case for a few of the problems, where only one of eight RPMs is placed correctly. There are other problems too, including floorplanner swapping BELs within a CLB, and crashing when writing RPM UCF files. Maybe FPGA editor is a more stable tool for floorplanning? I would try it but only have WebPack in current software. But if you can identify and work round the tools limitations, it looks tantalisingly close to workable, with RPMs considerably larger than yours above, and composed hierarchically of RPMs several levels deep. One of the (undocumented? - at least I haven't found it anywhere) workarounds seems to be to keep a component in the lower left hand corner of the smallest bounding box that can surround the RPM, which should site this corner at RLOC=X0Y0 - a condition violated deliberately in the test case above (and accidentally in several of my RPMs!) Another is to "replace all with placement" (or "constrain from" as appropriate) which corrects randomly swapped BEL elements, should they occur. I would love to see some others, or an App Note on this process... And I'm hoping some of these floorplanner bugs can be fixed. >> How fix is the routing "fixed" with directed routing in the later PAR of the whole design? Is it possible that the router changes anything? >Since you mentioned that a large macro is involved, I should point out >that Directed Routing is not recommended for use with large numbers of >signals on the order of hundreds. Guide should be used instead. That >recommendation depends on the nature of the routing involved and the >level of congestion around the locked routing. Guide is interesting, both because I don't have FPGA editor, and apparently directed routing isn't intended for large RPMs. Can you point me in the direction of a flow that would use guided routing for a top level module composed of several pre-routed RPM modules? Preferably where at least one of the RPMs has itself been created in this way? I am currently finding it difficult to maintain timings achieved on lower level modules when they are combined together, and scope for routing congestion obviously increases. - BrianArticle: 77418
I want to do post place and route timing simulation on a Virtex2 part using the Xilinx Modelsim starter simulator, how can I set the temperature point to 70 celcius? Thank you for your repliesArticle: 77419
<weddick> schrieb im Newsbeitrag news:ee8aefa.-1@webx.sUN8CHnE... > In my state machine I would like to add a counter which is used to increment and address each time through a certain state. Whats the best way to implement this? I've tried defining a signal but not sure where to initialize it. Do I add and init state to the state machine? or is there another way? You can add an (a)synchronus reset to the state machine. But why not simply trying? If the clock frequency ist too high, many differetn ways will work. Regards FalkArticle: 77420
"Peter Alfke" <alfke@sbcglobal.net> schrieb im Newsbeitrag news:1104984327.572531.186360@c13g2000cwb.googlegroups.com... > room is a good thing to have. 15 years ago, some cried when a few LUTs > went unused: "Such a waste !". Now they say: "Nice to have some room > for future changes." Yes, but it would be nice to leave some (more) control to the user. Some time ago, I started a thread about the s****d XST or mapper, who adds insanely much route thru LUTs in a design (1200 LUTs for logic, +350 route thru), that runs at a slow 36 MHz clock. The case could't be solved also by the help of our Xilinx FAEs. I konw, synthesis and mapping are complex processes, and we have to accept a certain amount of unexplained "black magic", but sometimes its just too much. Regards FalkArticle: 77421
"gja" <geeja@hotmail.com> schrieb im Newsbeitrag news:SQdDd.3214$yK7.3065@fe11.lga... > I want to do post place and route timing simulation on a Virtex2 part using > the Xilinx Modelsim starter simulator, how can I set the temperature point > to 70 celcius? Add temperature=70C; to your UCF Regards FalkArticle: 77422
Just wondering if the smaller xilinx products are fast enough to do processing of video signals. ( i know they can handle the complexity ) What i want to do is take RGBI from older computers ( like Atari, commodore, etc ) and convert them into VGA for a PC monitor.. Ive seen some projects in discrete hardware for a single type of machine, but never one for several types of machines, and none in FPGA ( goign this route for size and simplicity ) Since we aren't talking drastic resolutions here, i figured they would be fast enough?Article: 77423
Hi > Since we aren't talking drastic resolutions here, i figured they would > be fast enough? I would guess so too ... 640x480 is < 30Mhz pixel clock, easily achievable. Of course that also depends on the treatment but it sounds like all you need is a timing adaptator ... SylvainArticle: 77424
"Austin Lesea" wrote > And, "seamless risk free" is just a plain an outright misrepresentation. > > I know of a customer that had a serious issue, and was unable to meet their > production ship dates (fact). Only reason we know is that they had to > continue buying the FPGA...... Without taking sides on the underlying debate, is there a possibility that problems and design practices masked by the slower FPGA speeds come and bite at ASIC speed? Not everyone has read and followed the stuff on crossing clock domains and so on. I'm just wondering how come fully debugged (!) designs can go all bad.
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