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"Falk Brunner" <Falk.Brunner@gmx.de> wrote in news:34ql38F4dnulvU1@individual.net: > "Enzo B." <enzo_br@virgilio.it> schrieb im Newsbeitrag > news:ZQTFd.406761$b5.19667001@news3.tin.it... > >> Good morning, >> >> I'm a beginner with FPGA. >> I've found an 8051 IP core here : http://oregano.at/ip/ip01.htm , and >> want to put it in a Spartan 3 FPGA like XC3S50 or XC3S200 (they have >> impressive number of LUT, and I suppose it's possible). >> Now, how I can do this ??? > > Just do it. Setup a new project, add the files, compile. > But if you want a powerfull uC in a Xilinx FPGA, you better go for the > famous KCPSM (xapp213). Its a very nice thing, much faster than any > 8051 clone and MUCH smaller!!! > > Regards > Falk No, you can't just do it with this 8051 core. It has some internal/external RAM/ROM modules that you will have to replace with BlockRAMs. Not hard to do, but you do say you are a beginner. Also, this 8051 requires more LUTs than the XC3S200 has. You will need at least an XC3S400 unless you want to devote some time to optimization and floorplanning. As suggested, using the Xilinx PicoBlaze is a better solution. But if you are truly just beginning with FPGAs, then I suggest you also take a look at http://www.xess.com/appnotes/webpack-6_3-xsa.pdf. -- ---------------------------------------------------------------- Dave Van den Bout XESS Corp. PO Box 33091 Raleigh NC 27636 Phn: (919) 363-4695 Fax: (801) 749-6501 devb@xess.com http://www.xess.comArticle: 77701
Top port signals represent wires. Synthesis requires a process that uses port and process values to update process variables and port signals at each rising_edge(clk). Such a process might at some point read a port slice: my_upper_byte_v := my_in_port(7 downto 0); And perhaps drive a wide port: my_out_port <= my_uout_byte_v & my_lout_byte_v ; -- Mike TreselerArticle: 77702
In article <PcvFd.107$9P5.106@newsfe3-gui.ntli.net>, Kryten <kryten_droid_obfusticator@ntlworld.com> wrote: >FPGAs are not designed with such anti-hacking measures (AFAIK). >By nature, their structure is fairly regular. >There is no dedicated micro to do encrypted loading, and if there were it >would need a few K of ROM to hold the software. And there would still be a >decrypted bitstream somewhere that could be probed. >I hear that FPGA makers are trying to add some crypto on some devices, but I >don't know how effective it will be. Security is not a trivial matter to do >right. Both Xilinx and Altera have a pretty sophisticated mechanism in their more expensive parts. Basically both have a small encryption engine which can decrypt a bitfile as it is loaded. The key for this encryption is specified by the programming customer and stored either as Flash (Altera) or battery-backed SRAM cells (Xilinx). Both are possibly succeptible to sidechannel or fault injection attacks (I'd bet probably), and the altera parts can always be delidded and probed to get the key (this is harder on the Xilinx because of the need to not disturb SRAM state until you can probe the bits). Both use high quality block cyphers, with the first-gen using 3DES and the current gen using AES. I would comfortably keep a $10k secret in the Xilinx parts, and uncomfortably keep a $100k secret if I could also play with the packaging (eg, route the battery through a series of wire coils throughout the packaging, to add to physical tamper resistance). -- Nicholas C. Weaver. to reply email to "nweaver" at the domain icsi.berkeley.eduArticle: 77703
Hello, I'm trying to do a glue-less TFT controller for LVDS panels with a spartan 3. I can't just output the data using standard registers since the output data frequency is about 455 Mhz, so I was thinking to use the DDR registers to output these data so my internal clock is 232Mhz which fits into the Spartan 3 capability. The problem is that I never used differential standards before. Looking at the manual I saw the OBUFDS macro that seems to be exactly what I wanted. But I can't connect the Q port of the OFDDRCPE macro to the input of OBUFDS, it doesn't work : ERROR:LIT - OBUF symbol "OFDDRCPE_inst/OBUF1" (output signal=lcd_d1_int) can only drive IBUF, but it is driving pin I of OBUFDS symbol "OBUFDS_inst" (output signal=lcd_d1). Errors found during logical drc. I've seen some xilinx app note about SDI that uses the same "trick" and the block diagram shows a DDR Flip/Flops + Mux followed by differential output buffer but no code was provided ... Thanks. Sylvain PS: If you give code, I prefer VHDL but If you only have verilog, I'll try to translate it myself.Article: 77704
Nicholas, The latest V4 has 256 bit AES, as opposed to S2's 128 bit AES. Both are considered unbreakable by a brute force attack (today). The BB RAM key storage in V4, V2P, and V2 is a bit tougher to break (pun intended) than the e-fuse (which can be viewed optically and read out as to their state). The government routinely uses a spring loaded contact to remove the back up battery to 'zeroize' the keys. This extra level of physical security in the packaging of the product makes cracking safe enough for the homeland security types. Of course, before they had BB RAM, they used thermite charges to destroy the device if it was tampered with, so packaging options were also used effectively to 'zeroize' the whole danged thing! Hard to get UL listing when your product contains an explosize incendiary device.... At this time, we have sent our 'logic vault' encryption/decryption eval platform to a number of intersted parties, who have promised us to do their best to crack them. The good news is that so far, there is no news. Since there is no such thing as a secret (obscurity never lasts forever), we assume that any method used to crack will become known. Once known, we have to be able to find a way to make that attack inneffective. I highly recommend reading up on safe-cracking, as that is a field that is quite mature, and has many lessons for what is acceptable, or not acceptable security. For example, a safe's hardness is rated in minutes to penetration by a determined and skilled attacker, with a bank vault being only perhaps 30 to 40 minutes harder to break than a wall safe. Since there is no 'security in obscurity' we are interested in any real attack that might be used, so we can only do better next time. Austin Nicholas Weaver wrote: > In article <PcvFd.107$9P5.106@newsfe3-gui.ntli.net>, > Kryten <kryten_droid_obfusticator@ntlworld.com> wrote: > > >>FPGAs are not designed with such anti-hacking measures (AFAIK). >>By nature, their structure is fairly regular. >>There is no dedicated micro to do encrypted loading, and if there were it >>would need a few K of ROM to hold the software. And there would still be a >>decrypted bitstream somewhere that could be probed. > > >>I hear that FPGA makers are trying to add some crypto on some devices, but I >>don't know how effective it will be. Security is not a trivial matter to do >>right. > > > Both Xilinx and Altera have a pretty sophisticated mechanism in their > more expensive parts. > > Basically both have a small encryption engine which can decrypt a > bitfile as it is loaded. The key for this encryption is specified by > the programming customer and stored either as Flash (Altera) or > battery-backed SRAM cells (Xilinx). > > Both are possibly succeptible to sidechannel or fault injection > attacks (I'd bet probably), and the altera parts can always be > delidded and probed to get the key (this is harder on the Xilinx > because of the need to not disturb SRAM state until you can probe the > bits). > > Both use high quality block cyphers, with the first-gen using 3DES and > the current gen using AES. > > I would comfortably keep a $10k secret in the Xilinx parts, and > uncomfortably keep a $100k secret if I could also play with the > packaging (eg, route the battery through a series of wire coils > throughout the packaging, to add to physical tamper resistance).Article: 77705
In article <1vsdu01dfl4or8dqmc6p2p7o5faqikol10@4ax.com>, Nick <char-DONTBUGME-les@YY.iiedotcnam.france> wrote: >On Thu, 13 Jan 2005 09:31:09 GMT, Ben Twijnstra <btwijnstra@gmail.com> >wrote: > >>I suggest you read the following article: >> >>http://www.altera.com/literature/wp/wp_m2dsgn.pdf > >Thank you very much Ben, this white paper is very interesting. It will >provide a fairly good level of reliability for our design. >I shall contact you in a few days. > >Thank you again, you relieve me of a great pressure. Frankly, don't bother. This app note is CRAP. 100% pure bovine extract. Altera should be ashamed of putting it on their web site. You might as well ask clunkerbell, the magic anti-piracy fairy to protect your design. This style of protection would stop only a very poor amature. The attacker can take the device and the bitfile, and either extract the DES key from the FPGA rather than the MAX2 part (the key is not just in the MAX2 part, but in plaintext in the FPGA), or even more straightforward, trace the connections from the MAX2 part to the FPGA in the FPGA's configuration, trace the enable line in the bitfile, and edit the bitfile to tie this line high. Don't bother wasting the board space or design space on this. If you actually are paranoid enough that the threat of a $1M-100M lawsuit against someone who pirates your design is insufficient security, use a Cyclone II, Virtex II/IIPro, or Virtex 4, with their encrypted bitfile loading options. -- Nicholas C. Weaver. to reply email to "nweaver" at the domain icsi.berkeley.eduArticle: 77706
I'm new to FPGAs & PLDs, but hoping you can help me with the following: I need to build a data concentrator that would take 8 to 16 I2C channels and concentrate them into one high speed SPI or 8-bit parallel channel. The I2C channels would be masters, each with usually no more than one slave, with the slave transmitting as it requires - at intervals as short as about 1ms. The channels may be at different clock rates depending on their length to accomodate long lines that need a low clock rate. The concentrator would receive all this data, keeping up with the rate, combine it, tagged by port and device number, and relay it to a microcontroller. Also the microcontroller could direct commands through the concentrator to selected I2C channels & device numbers. The microcontroller would also be able to download configuration information to the concentrator to set clock rates, etc. Does this sound like a good job for an FPGA or PLD? How large an device in terms of number of gates, etc am I likely to need? Any recommendations for a chip or manufacturer? Thanks! - Chris GrahamArticle: 77707
Correction. See below. - Chris "Chris Graham" <chrisgr@shaw.ca> wrote in message news:GRXFd.79497$6l.29090@pd7tw2no... > I'm new to FPGAs & PLDs, but hoping you can help me with the following: > > I need to build a data concentrator that would take 8 to 16 I2C channels > and concentrate them into one high speed SPI or 8-bit parallel channel. > The I2C channels would be masters, each with usually no more than one > slave, I2C channels on the concentrator would be configured as slaves since I want the connected devices to be able to initiate transations. > with the slave transmitting as it requires - at intervals as short as > about 1ms. The channels may be at different clock rates depending on > their length to accomodate long lines that need a low clock rate. > > The concentrator would receive all this data, keeping up with the rate, > combine it, tagged by port and device number, and relay it to a > microcontroller. Also the microcontroller could direct commands through > the concentrator to selected I2C channels & device numbers. > > The microcontroller would also be able to download configuration > information to the concentrator to set clock rates, etc. > > Does this sound like a good job for an FPGA or PLD? How large an device > in terms of number of gates, etc am I likely to need? > > Any recommendations for a chip or manufacturer? > > Thanks! > > - Chris Graham >Article: 77708
> I've seen some xilinx app note about SDI that uses the same "trick" and > the block > diagram shows a DDR Flip/Flops + Mux followed by differential output > buffer but > no code was provided ... Ah, finally found one with code example. Changing the OFDDRCPE to FDDRCPE did the trick ... I should have known that the preceding "O" was to include the output buffer ... SylvainArticle: 77709
Michael Schuster wrote: > Uwe Bonnes wrote: > > >>Ise works quite a long way. Calling >>XST from ISE is dead slow, due to a Linux kernel bug. However you can't >>use the programming tools talking to the hardware. > > I tried to install the ise 6.3 with wine, but it didn't work. Do you have > some hints? (Using SuSE 9.2 prof) > > Michael The key to doing this is to install the vc6 support package on wine - see my page <shameless plug> http://www.danbbs.dk/~kibria/xilinx.html </shameless plug> for details. I'm currently running a 6.3 webpack with no problems (other than configuration as usual) using wine. On SuSE 9.1 I did this (very simple): 1) Install the binary dec. 1 distribution from www.winehq.com 2) Install the support package as described on my page (no need to manually override the windows version for the newest wine). 3) Install the webpack using the self-extracting archive And it has been working ever since. -- Brian Dam Pedersen M.Sc.EEArticle: 77710
> > I need to build a data concentrator that would take 8 to 16 I2C
channels
> > and concentrate them into one high speed SPI or 8-bit parallel channel.
> > The I2C channels would be masters, each with usually no more than one
> > slave,
>
> I2C channels on the concentrator would be configured as slaves since I
want
> the connected devices to be able to initiate transations.
>
> > with the slave transmitting as it requires - at intervals as short as
> > about 1ms. The channels may be at different clock rates depending on
> > their length to accomodate long lines that need a low clock rate.
> >
> > The concentrator would receive all this data, keeping up with the rate,
> > combine it, tagged by port and device number, and relay it to a
> > microcontroller. Also the microcontroller could direct commands
through
> > the concentrator to selected I2C channels & device numbers.
> >
> > The microcontroller would also be able to download configuration
> > information to the concentrator to set clock rates, etc.
> >
> > Does this sound like a good job for an FPGA or PLD? How large an device
> > in terms of number of gates, etc am I likely to need?
> >
> > Any recommendations for a chip or manufacturer?
> >
The AT94K05/10/40 FPSLIC contains
* a 25 MHz AVR RISC processor
* 5/10/40 k gate FPGA.
* A single large SRAM accessible by the FPGA and the AVR
* Multiple small 32 x 4 DPRAM configurable as 32 x 8 DPRAMs
usable as receive FIFOs.
On the 05 you have 12 usable DPRAMs or 6 FIFOs
On the 10 You have 2 x so 12 FIFOs would fit.
If you can live with a 32 x 4 FIFO, then you would definitely have
enough
for 16 channels.
If the FPSLIC AVR core is sufficient as the micro (20 MIPS)
then you will not need the SPI at all.
All processing is done internally.
There is a coverification environment, so you can simulate both the
AVR and the I2C slave macro.
Why use I2C?
At 400 kbps it is pretty slow.
If your datasource is a micro, then I would use a JTAG look alike interface.
Signals = TDI,TDO,TMS,TCLK.
This controls two shift registers in the FPGA.
First shift register is the address of the DPRAM
Second shift register is the data word
TMS is used to select the first, the second, and when both are filled
the data word is written to the address pointed out by the address shift
register.
Very simple reliable logic inside the FPGA, ans should have much higher
transfer rate than I2C which is limited to 400 kbps.
You should be able to run the TCLK at 6 MHz
--
Best Regards,
Ulf Samuelsson.
Ulf at atmel dot com
These comments are intended to be my own opinion and they
may, or may not be shared by my employer, Atmel Nordic AB.
Article: 77711"Chris Graham" <chrisgr@shaw.ca> wrote in news:CWXFd.79093$Xk.59972@pd7tw3no: > Correction. See below. > > - Chris > > "Chris Graham" <chrisgr@shaw.ca> wrote in message > news:GRXFd.79497$6l.29090@pd7tw2no... >> I'm new to FPGAs & PLDs, but hoping you can help me with the >> following: >> >> I need to build a data concentrator that would take 8 to 16 I2C >> channels and concentrate them into one high speed SPI or 8-bit >> parallel channel. The I2C channels would be masters, each with >> usually no more than one slave, > > I2C channels on the concentrator would be configured as slaves since I > want the connected devices to be able to initiate transations. > >> with the slave transmitting as it requires - at intervals as short as >> about 1ms. The channels may be at different clock rates depending on >> their length to accomodate long lines that need a low clock rate. >> >> The concentrator would receive all this data, keeping up with the >> rate, combine it, tagged by port and device number, and relay it to a >> microcontroller. Also the microcontroller could direct commands >> through the concentrator to selected I2C channels & device numbers. >> >> The microcontroller would also be able to download configuration >> information to the concentrator to set clock rates, etc. >> >> Does this sound like a good job for an FPGA or PLD? How large an >> device in terms of number of gates, etc am I likely to need? >> >> Any recommendations for a chip or manufacturer? >> >> Thanks! >> >> - Chris Graham >> > > This should be fairly straightforward with a small FPGA. We have been working with the Altera Cyclone EP1C3 which is the smallest FPGA that Altera sells. It would be more than adequate. A PLD design would take lots of macrocells. You probably should avoid this approach since a very large PLD is a lot more expensive than a small FPGA. -- Al Clark Danville Signal Processing, Inc. -------------------------------------------------------------------- Purveyors of Fine DSP Hardware and other Cool Stuff Available at http://www.danvillesignal.comArticle: 77712
Hi, I am needing about 30 GAL22v10's for a small project I'm working on. I've looked on most UK suppliers sites (RS, Farnell, etc.) but they want to charge the earth (round £3 to £5) each for them. So I was wondering if anyone knows of a cheaper uk source. I'm looking to pay around £1 each for them at the most. But all suggestions are welcomed. Yours, LaesQArticle: 77713
Chris Graham wrote: >> >>Does this sound like a good job for an FPGA or PLD? How large an device >>in terms of number of gates, etc am I likely to need? >> >>Any recommendations for a chip or manufacturer? Some options: a) Use tiny uC as i2c-spi bridges, and chain them. Advantage is easy to add more channels, & testing is very simple. b) For CPLDs you are likely to hit RAM issues : if you want 16 remote-readable i2c slaves, then they will need dual port ram - and RAM is expensive in CPLDs [RAM is the most glaring omission on the MAX-II ] So that puts you into the smaller FPGA area - and there, neither speed nor logic are likely to be an issue. You can time-share dual port ram, to make it appear more-ported. Do you need instant-on ? What is MAX i2c speed ? -jgArticle: 77714
I'm working with ISE 6.2i on a project, and I'm trying to organize the source into libraries. In fact, I'm using a couple Opencores cores for this task as well. The libraries are in the format that Icarus Verilog handles just fine. That is, the library is a directory of verilog files, with each file named after the module it contains. I cannot for the life of me figure out how to get XST to do the same thing. I can list all the files in a file list, but I really just want to point it at the library directory and be done with it. I can see that the -vlgincdir flag to the run subcommand works for includes, but what (if anything) does the job for modules? And also, I cannot find anything that looks like a "-Dmacro=value" switch. Some of these library cores are configured by defines, and I would rather include those defines on the command line, or in the file list as I can with Icarus Verilog and the +define+macro=value statement. -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep."Article: 77715
Gregory Burd wrote:
> Hal Murray wrote:
>> You might consider taking a 1-day intro class or find a friend
>> who has the tools installed and will help you get started.
>>
>
> Hal,
>
> Good advise. Part of my goal is to somehow make it possible for
> those using Mac OS/X to do FPGA development. Seems like a rich untapped
> market.
Icarus Verilog works swimingly in Mac OS X. The 0.8 source compiles
out of the box, or you can use Fink; although currently the version
from Fink is a bit old. (Charles Lepple is looking for testers of
a 0.8 Fink package, if you want to contribute there.)
<http://www.icarus.com/eda/verilog>
As pointed out, you cannot quite do the back-end stuff, the
map and par, on Mac OS X, but you can do all the rest.
--
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
Article: 77716"Austin Lesea" <austin@xilinx.com> wrote in message news:cs9f5l$mnq1@cliff.xsj.xilinx.com... > The latest V4 has 256 bit AES, as opposed to S2's 128 bit AES. Interesting. Since cryptographic processing is becoming increasingly useful in applications, is the crypto hardware available for use after loading? I suspect it isn't something that the chip makers thought of at the time, but I'd guess it would not be a huge job to multiplex the signals to the rest of the FPGA and say "finished using this for loading, now available to the FPGA application" NCypher in Cambridge UK use FPGA for their web security hardware accelerators, for instance. It might make them more efficient to use the custom-made loading crypto hardware instead of using general-purpose FPGA logic for it. > The government routinely uses a spring loaded contact to remove the back > up battery to 'zeroize' the keys. This extra level of physical security > in the packaging of the product makes cracking safe enough for the > homeland security types. If you dissected one unit could you find out the construction and circumvent springs etc on others? > thermite charges to destroy the device Maybe they could make some of the silicon microporous instead. :-) > At this time, we have sent our 'logic vault' encryption/decryption eval > platform to a number of interested parties, who have promised us to do > their best to crack them. > > The good news is that so far, there is no news. Surprising. I recall specialist labs being able to crack most smartcard keys in about 15 minutes, and they were impressed if they had to take over an hour. Howe expert were the interested parties? I hear it costs several million dollars to get smart card software tested and approved to the top banking security levels (named IPSEC6 or similar, IIRC). > For example, a safe's hardness is rated in minutes to penetration by a > determined and skilled attacker, with a bank vault being only perhaps 30 > to 40 minutes harder to break than a wall safe. I guess with FPGA chips, one just needs to protect them for their commercial lives (which may just be a few years these days). > Since there is no 'security in obscurity' we are interested in any real > attack that might be used, so we can only do better next time. Indeed, security should lie in the key not the method. Everyone can read how Chubb locks work but this won't tell you the key pattern.Article: 77717
Hi Eric, The Quartus simulator does not support general VHDL test benches, and can't automatically convert them to waveform files. You should use a 3rd party simulator if you want to use a VHDL testbench. If you bought the full version of Quartus, there will be an OEM version of ModelSim included with it that can read your VHDL test bench. If you are using Quartus web edition and don't want to buy a 3rd party simulator, you will have to make a stimulus file in a format the Quartus simulator can read (e.g. .vwf or .vec). Vaughn Altera [v b e t z (at) altera.com] "Eric" <ericjohnholland@hotmail.com> wrote in message news:1105500512.665365.197750@z14g2000cwz.googlegroups.com... > Hello, > > I'm trying to use Quartus II to functionally simulate my code. > > I have a VHDL test bench *.vht file. How do I convert it to a *.vwf > file so Quartus will allow me to simulate it? > > Or is there a setting that I need to adjust to get the vht file to > work. > > Thanks, > > Eric >Article: 77718
On Fri, 14 Jan 2005 22:38:14 +0000 (UTC), nweaver@soda.csua.berkeley.edu (Nicholas Weaver) wrote: >Don't bother wasting the board space or design space on this. If you >actually are paranoid enough that the threat of a $1M-100M lawsuit >against someone who pirates your design is insufficient security, use >a Cyclone II, Virtex II/IIPro, or Virtex 4, with their encrypted >bitfile loading options. I just need to sell a fair security to my boss. The copyright is the best protection IMHO, but he wants something more. Well, that's something more and it sounds strong enough for me. The cost is minimal compared to switching to a new device. NickArticle: 77719
Unless you have some real burning need for a micro in a fpga then i dont see the point of putting something like a 8052 into a fpga where you can buy off the shelf parts which run at 100Mhz and have inbuilt spi,i2c,ports etc. I can see a point if the 8052 core is redesigned to run as a single clock per instruction or uses some custom instruction set or some such . I have implemented a very simple 8052 core with some added such as a dedicated modulo arithmetic unit and 5 stage instruction pipeline, but it wasnt a beginers project.Article: 77720
Hello, ZSP IP core doesnot contain TDM. Can some one tell how can i include TDM to it, i like you need to have a master AHB bridge and a slave AHB bridge and connect TDM to master AHB bridge. So if anyone has any information about it, please share it with me. Thanks and regards PraveenArticle: 77721
Thanks for your replies. I've (recently) seen there isn't possible to compile the Oregano System's 8051 core with the ISE because it is written for another compiler. I think it's possible to use it on Xilinx devices, but not without modification. And I don't know how modify it. As I've read, the PicoBlaze is a soft core written purposely for Xilinx FPGA devices : requires much lower resources and is faster if compared with another core. But how I can start to use it? In particular, what software tools I need? Exists a small evaluation kit (or similar)? Another question : I've searched an 8051-compatible core because I have experience with 8051 & derivates, a C compiler, some routines, etc. and maybe (?) I can use this as a starting point. I haven't idea of how much can be hard to put an entire 8051 on a FPGA, but if this is more over my possibilities, can I start by putting only the cpu (with registers but without program ROM and data RAM) and adding an external program rom to the FPGA? Is this more simple? Thank you for any suggestion. Enzo ~ ~ ~ > >> Good morning, > >> > >> I'm a beginner with FPGA. > >> I've found an 8051 IP core here : http://oregano.at/ip/ip01.htm , and > >> want to put it in a Spartan 3 FPGA like XC3S50 or XC3S200 (they have > >> impressive number of LUT, and I suppose it's possible). > >> Now, how I can do this ??? > > > > Just do it. Setup a new project, add the files, compile. > > But if you want a powerfull uC in a Xilinx FPGA, you better go for the > > famous KCPSM (xapp213). Its a very nice thing, much faster than any > > 8051 clone and MUCH smaller!!! > > > > Regards > > Falk > > No, you can't just do it with this 8051 core. It has some > internal/external RAM/ROM modules that you will have to replace with > BlockRAMs. Not hard to do, but you do say you are a beginner. > > Also, this 8051 requires more LUTs than the XC3S200 has. You will need > at least an XC3S400 unless you want to devote some time to optimization > and floorplanning. > > As suggested, using the Xilinx PicoBlaze is a better solution. But if > you are truly just beginning with FPGAs, then I suggest you also take a > look at http://www.xess.com/appnotes/webpack-6_3-xsa.pdf. > > > -- > ---------------------------------------------------------------- > Dave Van den Bout > XESS Corp. > PO Box 33091 > Raleigh NC 27636 > Phn: (919) 363-4695 > Fax: (801) 749-6501 > devb@xess.com > http://www.xess.com >Article: 77722
I haven't needs to do this, I would like to implement a microcontroller in a FPGA, for understanding the capabilities of these devices. I know the fast 8052 derivates from Silicon labs : they are very fast and includes various peripherals, but if you need a very large number of I/O or a particular function (an IDE hdd interface port), a practical way to do this is to add a PLD or similar device to the microcontroller. Currently I haven't to do this, I only want to... play a little. p.s. I suppose you have written your fast 8052 core in VHDL, right? Do you know a book (for beginners!!) about this language? Thank you. Enzo "Jezwold" <edad3000@yahoo.co.uk> ha scritto nel messaggio news:1105785817.466744.309450@z14g2000cwz.googlegroups.com... > Unless you have some real burning need for a micro in a fpga then i > dont see the point of putting something like a 8052 into a fpga where > you can buy off the shelf parts which run at 100Mhz and have inbuilt > spi,i2c,ports etc. I can see a point if the 8052 core is redesigned to > run as a single clock per instruction or uses some custom instruction > set or some such . > I have implemented a very simple 8052 core with some added such as a > dedicated modulo arithmetic unit and 5 stage instruction pipeline, but > it wasnt a beginers project. >Article: 77723
The Hamburg VHDL archive has several useful resources. http://tech-www.informatik.uni-hamburg.de/vhdl/Article: 77724
You could go to a dustributor such as Arrow but I dont know how they deal with one off orders.They might have some instore they would sell you.
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