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Antti, >> you misunderstood me. I was asking about programming it FROM the FPGA. You > know this >> ASMI stuff. >> >> Martin > > sorry I am bit off today catched some cold, hope it doesnt cathc over > newsgroups.. > > I bet you get no replies regarding the ASMI stuff. I looked into a little a > long time but havent actually done anything - from simple reason I still > dont have any of your nice cyclone boards on my desk :) The acex board I > have, I would like to give it away.. This wouldn't help, as these boards are configured with parallel Flash and a PLD. I'm just thinking about a new board for JOP and how to minimize part count. I have to beat the S3 Starter Kit in the price... > > It should be possible but you might have to dig into library sources, etc. > etc.. > If you want to solve this issue with a Cyclone I can give you one board. However, you have to modify it - attache the serial Flash to the FPGA pins in 'some' way and change MSEL0 to 0 for AS. Martin ---------------------------------------------- JOP - a Java Processor core for FPGAs: http://www.jopdesign.com/Article: 78751
Rick, >> Has someone managed to program these devices from the FPGA withou using NIOS? > > Just use it as normal SPI periphal and use the cyclone_asmiblock for it... > > Have you allready done it? A small code snippet would be nice. Martin ---------------------------------------------- JOP - a Java Processor core for FPGAs: http://www.jopdesign.com/Article: 78752
The data sheet says there are 16 BlockRAMs in the XC3S400. Go for 16! "design" <vasus_ss@yahoo.co.in> wrote in message news:1107590479.459500.312620@f14g2000cwb.googlegroups.com... > When i synthesize my design in a SPARTAN3 XCS400 FPGA the synthesis > report says that there are 8 blockRAMs available in Spartan3 FPGA . > But after place and route and everything it says there are 16 blockRAMs > available. > So which one is actually correct. > Does it also mean like if we used 9 blockRAMs then we are still under > the limit of BLOCK RAMS or have we exceeded the design resources as the > synthesis tool says. > > Thanks in advance >Article: 78753
Martin Schoeberl wrote: > Rick, > > >>>Has someone managed to program these devices from the FPGA withou using NIOS? >> >>Just use it as normal SPI periphal and use the cyclone_asmiblock for it... >> >> > > Have you allready done it? A small code snippet would be nice. http://www.fpga.ch/forum/viewtopic.php?t=3 enjoy (o; rickArticle: 78754
hi everyone, simple question... IMPACT doesn't recognize my xilinx parallel cable IV when downloading projects to the board. I have read in some articles that a power supply is necessary to power up the cable, but there is no power supply or adapter in the box where the cable came. Do I have to buy a separate adapter or is there any other way of powering the cable?? What kind of adapter do I need?? Thanks in advance.Article: 78755
"adrian" <adrian.mora@terra.es> schrieb im Newsbeitrag news:FpNNd.200108$A7.292999@telenews.teleline.es... > hi everyone, > > simple question... > IMPACT doesn't recognize my xilinx parallel cable IV when downloading > projects to the board. > I have read in some articles that a power supply is necessary to power up > the cable, but there is no power supply or adapter in the box where the > cable came. > Do I have to buy a separate adapter or is there any other way of powering > the cable?? > What kind of adapter do I need?? then you got a not complete package! as delivered there is small adapter that plugs in inbetween keyboard and PC and delivers 5V to the Cable IV you can probably find some other method to supply power anttiArticle: 78756
Antti Lukats wrote: >>Whops :) Hey we all do silly things.. >> >>But.. since you DID send it to the list.. care to elaborate on this SOC >>you are working on? ( if you can that is.. ) > > > ah, since I already OOPSED, then here it goes: it should really be "Xilinx > all you dreamed of.." type of thing - a very small single supply powered > module ready to load different hardware and different OS from smallest > availabe removable media or from onboard large flash. Board is stuffed with > pretty much latest stuff in smallest packages, BGA QFN CSP only. Base conf > would be uClinux MicroBlaze but other options will be offered as well. > > Hm I have a rule of 10 (a design unit with more than 10 IC should be > redesigned...) the modue is OK by that rule - so just take less than 10 > latest "nice" parts you would like to see on such a module, and if you have > done your homework then you should have about the list of whats actually on > :) > > I think that above all I can say at the moment. > > Antti > > Sounds like a more current C-1 board.. It Also sounds cool.Article: 78757
My Parallel cable IV came with a splitter that plugs into the PC keyboard connector, and the keyboard plugs into the other split end. Hhhmm, sounds like a bad hair day ;,) -Newman "adrian" <adrian.mora@terra.es> wrote in message news:FpNNd.200108$A7.292999@telenews.teleline.es... > hi everyone, > > simple question... > IMPACT doesn't recognize my xilinx parallel cable IV when downloading > projects to the board. > I have read in some articles that a power supply is necessary to power up > the cable, but there is no power supply or adapter in the box where the > cable came. > Do I have to buy a separate adapter or is there any other way of powering > the cable?? > What kind of adapter do I need?? > > Thanks in advance. >Article: 78758
OK, no problem. Do you known if the following download cable schematics works with the XC9572XL and Webpack ISE 6.3i (it looks quite old regarding to the date on the sheet)? I'm a hobbyist and I would like to build my own download cable not to buy one. http://www.xilinx.com/support/programr/files/0380507.pdf "Peter Alfke" <alfke@sbcglobal.net> schrieb im Newsbeitrag news:1107741003.684759.188640@f14g2000cwb.googlegroups.com... > Yes, they are. But you should not rely on this. It's your job to > minimize the resistance and inductance. > Peter Alfke >Article: 78759
MicroBlaze has trace signals that exists on the entity. If they are not connected, they don't have any loads. This warning is used about this and it can be ignored. Göran Jack wrote: > dear all > > I encountered tremendous of warning messages (2 types). First type is > > ------------------------------------------------------------------------------ > WARNING:NgdBuild:454 - logical net 'microblaze_0/Trace_Instr_EX<30>' > has no load > ------------------------------------------------------------------------------ > > In xilnx answer browser, > > ------------------------------------------------------------------------------ > This warning indicates that the signal referenced in the warning has no > load and will be removed during implementation. > ------------------------------------------------------------------------------- > > What does this mean? In case the signal is removed, what heppens? How > can we avoid this warning? > > Second type is > > ------------------------------------------------------------------------------ > WARNING:DesignRules:331 - Blockcheck: Dangling G output. G of comp > microblaze_0/microblaze_0/Data_Flow_I/Register_File_I/Register_File_Bit_I15/R > egFile_X2/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I/Register_File > _Bit_I15/RegFile_X2/SP.G is configured, but output is not used. > ------------------------------------------------------------------------------ > > I could not find the answer browser, but similar answer browser, > > ----------------------------------------------------------------------------- > To check for this, search for these components in FPGA Editor, and see > if they are configured > ----------------------------------------------------------------------------- > > If this is a problem, how can we configure in FPGA editor? >Article: 78760
"Ziggy" <Ziggy@TheCentre.com> schrieb im Newsbeitrag news:bvNNd.24610$C24.2729@attbi_s52... > Antti Lukats wrote: > >>Whops :) Hey we all do silly things.. [snip] > Sounds like a more current C-1 board.. It Also sounds cool. HAHA! I do have a C-1 !! Was one of the first one to buy and get it LOOONG time ago. It's still collecting dust. I did something with it, but its full of design mistakes and it was too-old (component wise) before it was announced. C1, ah well the girl who designed it possible found more interest (more $$$) doing "STICK things" like designing the C64 in JOY-stick (ASIC!) or something else. Whatever, the C1 project did not work out as initially planned, the board manufacturer I think lost a bit of money. AnttiArticle: 78761
Paul Leventis (at home) wrote: (non-constructive criticism snipped) >>Altera changed the LUT structure significantly, and I can believe that >>this makes certain applications faster, if they can tolerate shared >>inputs. But Altera made no systems-oriented functional changes, added >>no new functions or structures. > Shared inputs do not need to be "tolerated" -- they are an available but not > necessary feature. Ignoring all other aspects of the ALM, a 6-input LUT can > do a lot more than a 4-LUT, reducing the depth of the critical path and > hence increasing its speed. The reason where straight 6-LUTs lose out to > 4-LUTs is in area (or silicon cost) -- that's where all the other > innovations in the ALM come in, including shared inputs. For example, the > ALM can split into two (fully indepedent) 4-LUTs. Or you can share some > inputs and/or LUT mask bits and create two larger functions. With the ALM, > you get the speed when you need it and good area when you do not. I do wonder if the optimal LUT size has changed over the years. Is there work showing the optimal LUT size as a function of silicon resources needed to implement such LUTs? -- glenArticle: 78762
Hello I have one modul which is written in Verilog, which I wanna add to my IP core written in VHDL. The simulation works fine, but when I want to synthesize it, XST tells me that it doesnt find the verilog file... Can somebody please tell me how to handle this problem? my .pao file looks like this lib fsl_ff3_v1_00_n constants lib fsl_ff3_v1_00_n memory lib fsl_ff3_v1_00_n controller lib fsl_ff3_v1_00_n coprocessor lib fsl_ff3_v1_00_n ff3_alu lib fsl_ff3_v1_00_n add lib fsl_ff3_v1_00_n sub lib fsl_ff3_v1_00_n gf3.v lib fsl_ff3_v1_00_n ff3 lib fsl_ff3_v1_00_n multiplexer And I always get the error message that it cant find gf3.v.vhd. So how can I tell EDK that this time I have a verilog and not a vhdl file? Thanks for your help PhilippArticle: 78763
Hi,
You are using printf in your threads. printf requires a big stack. There
is likely a stack overflow in the thread. You should increase the stack
size allocated for threads, or allocate a custom large while creating
the thread with pthread_create.
Since there is no memory protection, these kind of errors can usually
bring the kernel (and any standalone program for that matter) down to
its knees.
thanks,
Vasanth
Stef wrote:
> Hi,
>
> Can anybody shed some light onto a problem that I am having getting
> the xilkernel to behave! Essentially, I compile my simple program and
> the kernel keeps creating new instances of itself at run time. The
> prog_main() is set up as a static thread instance PARAMETER
> static_pthread_table = ((prog_main,1)) in the MSS file. See the ouput
> below (with verbose debug to true)
>
> source
> ------
>
> #include "xmk.h"
>
> #include <stdio.h>
>
> void *prog_main(void *arg);
>
> int main ()
> {
> xilkernel_main ();
> }
>
>
> void *prog_main(void *arg)
> {
> static Index = 0;
> printf("prog_main(%d) called\n\r", Index++);
>
> while(1)
> {
> printf("In main - Data%d Index:%d\n\r", Data++, Index);
> sleep(500);
> }
> }
>
>
> output
> ------
>
>
> In main - Data18 Index:6
>
> In main - Data19 Index:6
> Idle Task
> XMK: Start
> XMK: Initializing Hardware...
> XMK: Initializing interrupt controller
> XMK: Connecting timer interrupt
> XMK: Starting the interrupt controller
> XMK: Initializing PIT device.
> XMK: System initialization...
> XMK: Enabling interrupts and starting system...
>
> prog_main(6) called
>
> In main - Data20 Index:7
> Idle Task
> XMK: Start
> XMK: Initializing Hardware...
> XMK: Initializing interrupt controller
> XMK: Connecting timer interrupt
> XMK: Starting the interrupt controller
> XMK: Initializing PIT device.
> XMK: System initialization...
> XMK: Enabling interrupts and starting system...
>
> prog_main(7) called
>
> In main - Data21 Index:8
> Idle Task
>
> In main - Data22 Index:8
>
> In main - Data23 Index:8
>
> In main - Data24 Index:8
>
> In main - Data25 Index:
> In main - Data1099 Index:407
>
> In main - Data1100 Index:407
> XMK: Start
> XMK: Initializing Hardware...
> XMK: Initializing interrupt controller
> XMK: Connecting timer interrupt
> XMK: Starting the interrupt controller
> XMK: Initializing PIT device.
> XMK: System initialization...
> XMK: Enabling interrupts and starting system...
>
> prog_main(407) called
>
> In main - Data1101 Index:408
> Idle Task
>
> In main - Data1102 Index:408
> XMK: Start
> XMK: Initializing Hardware...
> XMK: Initializing interrupt controller
> XMK: Connecting timer interrupt
> XMK: Starting the interrupt controller
> XMK: Initializing PIT device.
> XMK: System initialization...
> XMK: Enabling interrupts and starting system...
>
> prog_main(408) called
>
> In main - Data1103 Index:409
> Idle Task
>
> etc!!!!
Article: 78764Who made the starter kit spartan 3?? because I bought a digilent board 2 month ago and it seems to be the same board except the package (software and manual) given by xilinx "nospam" <nospam@nospam.invalid> a écrit dans le message de news: 1io1111375su6lmpdecfcht3msgqs7j92m@4ax.com... > "fpgawizz" <bhaskarstays@yahoo.com> wrote: > >>I am trying to understand the working of the multiplexed seven seg. >>displays on the xilinx spartan 3 board. > > I think everyone who gets the starter kit must end up writing their own > driver for the 7 segment display. > > Shame there isn't a bit more simple 'IP' provided with the kit. > > Apart from the Xilinx examples I didn't find much in the way of resources > for the starter kit on the web. > > Would there be interest in a Yahoo group or something to share Spartan 3 > starter kit related files? > > >Article: 78765
Antti Lukats wrote: > "Peter Alfke" <alfke@sbcglobal.net> schrieb im Newsbeitrag > news:1107733371.888845.5080@l41g2000cwc.googlegroups.com... > >>Jim, I like your idea, but it is not all that straightforward. >>I mentioned in the seminar that there is a loadable synchronous counter >>inside every DSP Slice, and it runs at 500 MHz, no ifs, no buts. >>Now, I will build a 5 GHz counter using the MGT. Is that allowed? >>DDS obviously runs at 500 MHz in the DSP slice, but I will run a >>virtual 8 GHz DDS either by using 16 accumulators, or by doing some > > > Hi Peter > > I have already done that! its reletivly simple to use MGT as DDS with > virtual 10GHz clock for every user clock 40 accu samples are calculated > > and I also am using MGT as 3GS/S logic analyzer with ChipScope > > I wish it would make sense for me to publish all that work > > Antti Hi Antti -- just an idea -- how about Xilinx keep you supplied with FPGA Eval Boards, & Tools, on 'long loan', and you supply Xilinx with source codes... ? Peter? -jgArticle: 78766
Hello,am student as a part of my master thesis Iam trying to generate BSP`s for ml310_pci_linux, but unfortunately I get stuck at this point ...could any of you have suggestion please drop it. am using ISE, EDK tools version 6.2i, with EDK service pack 2. problem:ERROR:MDT - ERROR FROM TCL:- cp: `C:/edk_projects/ml310/ml310_pci_design/ppc405_0/libsrc/linux_mvl31_v1_00_a/linux/arch/ppc/platforms/xilinx_ocp/xparameters_ml300.h.exe' and `c:/linux_pci/arch/ppc/platforms/xilinx_ocp/xparameters_ml300.h' are the same file while executing "exec bash -c "cp -Rfp $cur_dir/linux/* $value"" (procedure "post_generate" line 166) invoked from within "post_generate 1864928" ERROR:MDT - Error while running "post_generate" for processor ppc405_0... make: *** [ppc405_0/lib/libxil.a] Error 2 Thanks a lot in advance.....Article: 78767
Update: Did try to configure other FPGAs (XC2S100 and XC3S200) and it is working ok (any JTAG command and subsequent JTAG commands). So both WindowsXP+ISE6.1i03 (plus download cable) are working well and healthy. This lefts only the XC2S200E as guilty. It is the only common component in two different designs currently not responding to JTAG commands (and damaging communications with the XCF02S present in one chain). Curious observation is, in one design have a microcontroller+flash doing the configuration in slave serial mode and FPGAs is working well under this mode. I am going to give lot number for Xilinx guys in the hope to have any concerns about this silicon. So, I believe no answers from you will come and hope this case may help someone in some other design with this FPGA. Thanks,Article: 78768
Gabor wrote: > I've seen a few threads recently about warnings in XST > so I thought I'd put in my 2 cents. > > I've got a design where I instantiate the IOB flip-flops > that drive the output enables. There are three sections > with 5, 8 and 59 IOB's respectively that have equivalent > IOB output enable timing. I still want all these flip- > flops because they need to push into the IOB's to meet > the clock-to-out timing requirements. > > Now XST decides to warn me that the flip-flops in each > group are equivalent to eachother. That isn't too bad > because I can ignore the warnings and it builds what I > asked. Here's the fun part. In each group the number > of warnings I get is 5 times the number of combinations > of N things taken 2 at a time, where N is the number of > equivalent flip-flops. So for the case of the 59 flops > I get 8,555 warnings. Displaying these warnings takes > the bulk of the synthesis time for the design. > > I can see that the synthesizer may be too dumb to whittle > down the warnings to one per flop, but why are there 5 > times the number necessary to pair each flop with each > equivalent flop? > > It would be really nice to have a way to tell the synthesis > not to produce this particular type of warning (or other > types you've already seen and don't want to see again on the > next build). Gabor, Hiding specific messages is a feature that exists in XST 6.Xi and will be enhanced in 7.1i. This feature was added to reduce runtime as well as log file size and clutter. In the 6.Xi tools, use the XIL_XST_HIDEMESSAGES environment variable to filter all messages that fall into two categories. The set of messages filtered are fixed, but #382 is one of the low level messages. Consult chapter 9 of the XST User Guide for the lists of messages and details about how to enable this feature. The message filtering was implemented in this way to be a stepping stone for the functionality planned for 7.1i. In ISE 7.1i (due out in a few weeks), there is a message manager that will allow the user to filter out not only specific messages by number, but also specific instances of specific messages. This feature will extend filtering beyond just XST; most of the implementation tools will take advantage of this feature. As for the messages in the first place, have you tried inferring these registers? XST will pack output and output enable flops in the IOBs, and will replicate the output enable flops if necessary. thanks, David Dye Xilinx Technical MarketingArticle: 78769
David Dye wrote: > Gabor, > > Hiding specific messages is a feature that exists in XST 6.Xi and will > be enhanced in 7.1i. This feature was added to reduce runtime as well > as log file size and clutter. > > In the 6.Xi tools, use the XIL_XST_HIDEMESSAGES environment variable to > filter all messages that fall into two categories. The set of messages > filtered are fixed, but #382 is one of the low level messages. Consult > chapter 9 of the XST User Guide for the lists of messages and details > about how to enable this feature. The message filtering was implemented > in this way to be a stepping stone for the functionality planned for 7.1i. > Thanks for the tip, this really reduces my build time! > In ISE 7.1i (due out in a few weeks), there is a message manager that > will allow the user to filter out not only specific messages by number, > but also specific instances of specific messages. This feature will > extend filtering beyond just XST; most of the implementation tools will > take advantage of this feature. > So does this mean I'll be able to "mark" warnings in a report file viewer somehow so it doesn't appear on the next build? i.e. can I effectively see only new messages on each successive build? > As for the messages in the first place, have you tried inferring these > registers? XST will pack output and output enable flops in the IOBs, > and will replicate the output enable flops if necessary. I didn't try inferring the registers, because I took this part of the design from a Xilinx reference design (XAPP 608) so I had this problem from the beginning. Also in this case the warnings were not hard to ignore because they were together in one long section of the report file. Really just the build time was the headache. > thanks, > David Dye > Xilinx Technical MarketingArticle: 78770
Antti Lukats wrote: > "Ziggy" <Ziggy@TheCentre.com> schrieb im Newsbeitrag > news:bvNNd.24610$C24.2729@attbi_s52... > >>Antti Lukats wrote: >> >>>>Whops :) Hey we all do silly things.. > > [snip] > >>Sounds like a more current C-1 board.. It Also sounds cool. > > > HAHA! I do have a C-1 !! Was one of the first one to buy and get it LOOONG > time ago. It's still collecting dust. I did something with it, but its full > of design mistakes and it was too-old (component wise) before it was > announced. C1, ah well the girl who designed it possible found more interest > (more $$$) doing "STICK things" like designing the C64 in JOY-stick (ASIC!) > or something else. Whatever, the C1 project did not work out as initially > planned, the board manufacturer I think lost a bit of money. > > Antti > > I have not gotten a C-1 yet, as the price is still a bit steep for being 'in development' ( for me at least.. being a working guy with limited play money these days i have to choose carefully ). I still want to get one at some point anyway, but I agree it will loose ground due to its 'age' and hurt its future long term... More then likely ill end up with a digilient board ( or that foundation thingy ) before I get a C-1, out of practicality. Still holding off to see if the rumor of a 1M S3 digilient board comes true.. 400k is good, but more is always better, when you are experimenting... I hadn't heard of design issues on the C=1.. care to elaborate a bit? The C=1 stick project made quite a bit of money for Jeri, which is good as she's gotta eat too. They are still selling the older C=1 boards, and has a active group still. I watch the list, even though I don't have one, though I do have one of the joysticks.. going to gut it and add C64 peripherals to it.Article: 78771
Hi, I will send 16 bit/pixel video data from PC to a FPGA board through USB 2.0 interface. Data should be continuous and stable for accurate frame timing. I would like to ask questions to people who have used USB 2.0 at High Speed (480 Mbit/sec) Can an ordinary (cheap) PC with USB 2.0 supported motherboard send data continously and stable? Windows or Linux are not realtime OSs Can they send data at 480Mbit/sec through USB ? Without dealing with usb internal data structure, headers etc, is it possible to send pure video signal from PC to module? I mean no other information than video.. So easy to handle...(i think..) To get this data Do i need to implement usb or utmi specifications at FPGA? I think Trenz electronic's Micromodule is suitable for this. It has a USB physical interface ic GT3200. Has anybody used it for this kind of job? (By the way when i said video i mean sequence of BMP files, no compression) Thanks, yusufArticle: 78772
In my case, the application does not behave as expected. So I am thinking that the WARNING:DesignRules:331 message might be a problem...Article: 78773
With QII 4.0, all assignments were consolidated into a single file the qsf, instead of being stored in several different files (csf, psf, ssf, fsf) etc. Also as part of QII 4.0, default values of assignments were no longer stored in the qsf file. In the past all defaults were stored in the csf file. Instead defaults for converted projects were stored in the qdf file in the project directory, with the name being <project_name>_assignment_defaults.qdf. Therefore projects which have been converted from older (i.e before Quartus II 4.0)will have a qdf file in their project directory. When assignments are resolved the default values specified in <project_name>_assignment_defaults.qdf have a higher priority than those specified in quartus\bin\assignment_defaults.qdf. Therefore when you removed the <project_name>_assignment_defaults.qdf file some of the values of your default settings would have changed, and this explains the change in results. If you look at the file quartus\bin\assignment_defaults.qdf you will find a history of the default changes between releases from 4.1 onwards. An example of the comments in the QII 4.2 assignmnet_defaults.qdf file is: # Default value changes # # In 4.2, the default value of assignment DO_MIN_ANALYSIS has changed to "OFF" # In 4.1, the default value of assignment FITTER_EFFORT has changed to "Auto Fit" Hope this helps, Subroto Datta Altera Corp. Martin Schoeberl wrote: > I have a project which started with MP2 w. Leonardo and was converted by > several versions of Quartus (including several new file types). With Quartus 4.2 > I thought the project merely consists of proj.qpf and proj.qsf. Having all the assignments > in the .qsf file. > However, when I compiled the project with the other 'old' project files removed it resulted > in a different solution (fmax was 95MHz instead of 100MHz). > Adding the proj_assignment_defaults.qpf back to the project I got the original result. > So the question is: What's this xxx_as._def.qpf for? > > Martin > ---------------------------------------------- > JOP - a Java Processor core for FPGAs: > http://www.jopdesign.com/Article: 78774
Hello I'm planning to do a microblaze design using external DDR memory using the opb_ddr core. However I'd like to know if there is any constraints on how to connect (which banks/pins ...) the DDR chip. Here I only have 1 point to point connection of a 16 bits wide DDR. I was planning on using two banks for all the DQS/DQM/DQ then another bank for the control & address signals. I haven't seen much info about that in the opb_ddr doc. But on DDR interface appnotes, some have specific constrainst so I prefer to ask before making the board ;) Sylvain
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