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In article <cu0k6t$22j$1@gnus01.u.washington.edu>, glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote: >I am way behind in following the newer chips. > >How automated is the generation of the different family members? > >I was trying to imagine a design where at the mask level one >could insert a multiplier, RAM, or CLB array where all the >signals would line up. That is, each block could be separately >routed and then an array of such blocks assembled. >Still, I am sure that the costs are high, even for just >cataloging and inventorying a new device without considering the >mask costs. I believe, though, as devices get bigger more >intermediate family members will be needed. Except heres the gotcha: Assume the magic design fairy hands you a taped-out-and-compete design. Generating the masks ALONE costs $1M or so Thus a family approach (such as V4) is going to chose a few points and just produce those, and "close enough" ends up being cheaper than "just right" because of the costs of setup. -- Nicholas C. Weaver. to reply email to "nweaver" at the domain icsi.berkeley.eduArticle: 78651
Try "vsim -c" in a DOS box or Cygwin shell and see if you get any error messages. Use the "lmutil lmdiag" and "set" command to see if your license file is OK and your LM_LICENSE_FILE variable is pointing to your license file. Also make sure you don't have any expired features/increment lines in your file. Hans www.ht-lab.com "kcl" <kclo4@free.fr> wrote in message news:420222d6$0$19406$8fcfb975@news.wanadoo.fr... | Hi | | when i launch ModelSim 5.8c XE, the windows with the logo of modelsim( a | rhinoceros) open and after a few seconds it close and nothing else happen | there no process of modelsim running in the process list of winXP | I don't understand because last week It always run correctly. | I tried to reinstall Modelsim and it don't change | | Does anyone know this problem?? | | Thank you | | Alexis | | |Article: 78652
Hi! I have a big problem with connecting multiple masters to the OPB. I connected the Microblaze-Processor and a VGA-Controller to the bus. In the beginning everything works fine, but after maybe one second the whole system freezes. Even the FPGA seems to loose its configuration data. The voltage at the Done-Pin for example suddenly drops (not to 0V) and the video-timing generation fails (it only depends on the internal clock signal and has nothing to do with the bus). The code of the Microblaze is stored in the same SRAM the VGA-Controller uses for video data. When the code is stored in the internal memory I don't have any problems. The problems disappear when the VGA-Controller doesn't access the RAM. Thanks a lot, Matthias AllesArticle: 78653
hi after compilation of microblaze C code the log file says ---------------------------------------------- mb-size MB0/executable.elf text data bss dec hex filename 2780 657 4 3441 d71 MB0/executable.elf ---------------------------------------------- My first question is - Is it mean that "memory size = 2780 + 3441 = 6221 = bytes? " Function of C code is that add 300 integers using array declaration. The execution stops after adding 250 integers. This is undesirable. I think this problem is comming from limited BRAM size. Second question is - How can we maximally utilize memory (BRAM) so that we can perform more powerful operations ?Article: 78654
Jack wrote: > hi > > after compilation of microblaze C code > the log file says > > ---------------------------------------------- > mb-size MB0/executable.elf > text data bss dec hex filename > 2780 657 4 3441 d71 MB0/executable.elf > ---------------------------------------------- > > My first question is > > - Is it mean that "memory size = 2780 + 3441 = 6221 = bytes? " No, 2780 + 657 + 4 = 3441 bytes total in decimal, or D71 bytes total in hex. > > Function of C code is that add 300 integers using array declaration. > The execution stops after adding 250 integers. This is undesirable. I > think this problem is comming from limited BRAM size. > > Second question is > - How can we maximally utilize memory (BRAM) so that we can perform > more powerful operations ? Regards, John McCaskillArticle: 78655
Nicholas Weaver wrote: (snip regarding a variety of different FPGAs with different numbers of RAMs and multipliers) > Except heres the gotcha: > Assume the magic design fairy hands you a taped-out-and-compete > design. Generating the masks ALONE costs $1M or so > Thus a family approach (such as V4) is going to chose a few points and > just produce those, and "close enough" ends up being cheaper than > "just right" because of the costs of setup. Yes, a magic mask fairy would also be nice to have. I could wonder about putting more than one type of chip on a single mask, though that complicates the testing and packaging. (Making sure that the right labels end up on each one.) -- glenArticle: 78656
Virtex-4 has 17 family members in 3 sub-families ( 8 in LX, 3 in SX, and 6 in FX) covering a complexity range from about 12,000 to about 130,000 LUTs and flip-flops, which is a bit more than a 10 : 1 range. (You can use the 2- or 3- digit number in the part designator, multiply it by 1000 to get roughly the number of LUTs or Logic Cells. Let's not quibble about small inflation factors.) That converts to around 30 device-package ombinations, times 3 speed grades, times 2 or 3 temperature ranges. This calls for smart planning, especially since the chip-manufacturing cycle is significantly longer than the ordering lead-time we get from our customers... Peter AlfkeArticle: 78657
Does anybody know where I can download/source Orcad Capture (schematic ) and Layout ( footprints ) library parts for Xilinx Spartan 3 FPGA's, particularly XC3S400 in PQ208 package from the net? I'd prefer a freebie source but am will to use a 3rd party vendor other than Cadence. Thanks for any leads/advice. -pncArticle: 78658
Yeah, the 39% seems cooked to me, especially with no way to check it for the interested public. Where is that Altera guy hiding ? -Che > > Correct, but benchmarks are not all about speed, they are about > a defined set of designs, so you can exercise a device and get > mA/MHz, or LUT, or MHz or ns, or whatever parameter matters to you > most. A vendors claim of 39% is of little use to anyone. > Another use is they can show you how to get more of something, for more > effort, in the optimised benchmark category. > Of course, the optimised category is not a level playing field, that is > the whole point. > > -jgArticle: 78659
I recommend starting with the EDK tutorials and the simple Base System Builder (BSB) to get a simple "Hello World" to the uart working. The BSB will set-up the buses, connect the peripherals to them and even set-up the UCF file. If you want to simulate the design, I recommend avoiding the DDR memory and just use the on-chip BRAM's. Furthermore, make sure you read the section in the EDK guide(s) regarding how to configure ModelSim to work with EDK. That's an important section. In summary, there are no real shortcuts--you'll need to quality time with tools as there is much to ramp-up to. Good luck! nn On Fri, 4 Feb 2005, MM wrote: > I am about to start a similar excercise, but haven't done much yet. I think > you should begin with getting the EDK and perhaps one of the cheaper eval > boards, e.g. V2Pro LC by Memec Design. Together with the board you will get > access to several complete sample projects including C source code on the > Memec web site. I am not sure about the simulation. I believe this sort of > simulation will be extremely slow. > > > /Mikhail > > > <jjohnson@cs.ucf.edu> wrote in message > news:1107543066.103030.262780@c13g2000cwb.googlegroups.com... > > > > Anyone who has used the Power PC cores on Xilinx FPGAs has undoubtedly > > paid some dues... I selfishly ask if anyone has compiled a quick set of > > recipes, lessons-learned, or other guides for *quickly* getting up to > > speed on using these. > > > > There is no shortage of documentation available, especially from > > Xilinx. The problem (in classic Xilinx style) is that I don't have all > > year to read it. Thus, any pointers to the most-recommended, > > quickly-effective reading material would be appreciated. > > > > Specific scenario and questions: > > > > 1) I will soon have a board (with V2P30) on it. I wasn't originally > > planning to use the PPC, so no buses were routed for external memory. > > Hope to use on-chip memory only, now that I have a use for the PPC... > > > > 2) My tool set includes Mentor ModelSim, Synplicity (Synplify Pro), and > > Xilinx ISE. Do I need other $non-free$ tools in order to use the PPC? > > (i.e., Xilinx EDK, etc...) > > > > 3a) I first want to instantiate one PPC, load some instructions in > > memory via ModelSim, tie the PPC core to the rest of the FPGA fabric, > > and simulate enough instructions to make sure the flow works. > > > > 3b) Next, I'd like to create some real short test programs, compile > > them with gcc (no RTOS required, but if easy to configure and use, > > that's a bonus), load the memory image (via ModelSim) and simulate. > > > > 4) Load the PPC memory instruction via the bitfile when I power up the > > real hardware, have the PPC boot and start running my code when I > > toggle an input, so I can watch some outputs toggle on a scope. > > (Eventually this board will serve as a stimulus/waveform generator for > > another board.) > > > > 5) Where might I find an appropriately configured copy of gcc and > > libraries? > > > > That's it in a nutshell. I don't expect this to be a one-weekend > > project, but I don't have all year either. C code, VHDL code, > > Synplicity scripts, etc... for getting up to speed fast would be ideal. > > > > Thanks very much for *any* help you can provide. > > > > mj > > > > >Article: 78660
http://www.fpga-faq.com/FAQ_Pages/0027_Creating_PCB_symbols_for_FPGAs_using_ORCAD.htm "pnc" <mail2pnc@gmail.com> wrote in message news:1107558246.051981.296420@l41g2000cwc.googlegroups.com... > Does anybody know where I can download/source Orcad Capture (schematic > ) > and Layout ( footprints ) library parts for Xilinx Spartan 3 > FPGA's, particularly XC3S400 in PQ208 package from the net? > I'd prefer a freebie source but am will to use a 3rd party vendor > other than Cadence. > > Thanks for any leads/advice. > > -pnc >Article: 78661
Roel <electronics_designer@hotmail.com> wrote: >Has someone good or bad experience with >the RoseRT + ThreadX + Microblaze flow? I could be wrong, but I'd guess the count of "someones" having experience with that combo to be a pretty low number. I have had positive experiences with the last two of the three, but no experience with those two together. I would think that ThreadX and MicroBlaze get along quite nicely together. -- Dan HenryArticle: 78662
Yep, this is the simplest technique (that I know of). The "ctrl-insert" trick is undocumented by Cadence/Orcad, but it works (in Version 9.XX, at least). You can whip-out a symbol for even the big packages (FF1152 is my largest, so far) in under an hour. I believe that Altera offers a free service to create any schematic symbol for any device and for any schematic capture package. Xilinx should do the same for us dedicated, and semi-honest, Xilinx customers. :-| Bob "Symon" <symon_brewer@hotmail.com> wrote in message news:36iimjF5220pnU1@individual.net... > http://www.fpga-faq.com/FAQ_Pages/0027_Creating_PCB_symbols_for_FPGAs_using_ ORCAD.htm > > "pnc" <mail2pnc@gmail.com> wrote in message > news:1107558246.051981.296420@l41g2000cwc.googlegroups.com... > > Does anybody know where I can download/source Orcad Capture (schematic > > ) > > and Layout ( footprints ) library parts for Xilinx Spartan 3 > > FPGA's, particularly XC3S400 in PQ208 package from the net? > > I'd prefer a freebie source but am will to use a 3rd party vendor > > other than Cadence. > > > > Thanks for any leads/advice. > > > > -pnc > > > >Article: 78663
Hi Nicolas, If the wrapper is really inserting logic between a bidirectional IO bus of the IP and the user pins then the IO bus will be converted to multiplexer logic (as we can't implement tristate buses internally on the chip). It is not clear that this is happening, because the 'en' signal in the design is driven from the lower-level component. If you send me a qar (Project->Archive) of your design, it will be easy for us to tell you what is happening. Please email the qar file to the email address for this post. Subroto Datta, Altera Corp. "Nicolas Matringe" <matringe.nicolas@numeri-cable.fr> wrote in message news:1107539574.135654@quito.magic.fr... > Hello > For some reasons I have an IP with bidirectionnal IOs that is instantiated > inside a higher level wrapper and that I can't modify. The proble is that > the wrapper inserts some logic between an IO bus of the IP and the actual > chip IOs. > It seems that QuartusII (4.2) produces garbage from my VHDL. How can I do? > > The problem is that int_bus is x"FF" when en = '1', instead of int_bus_in. > > Sample code : > > entity wrapper is > port ( > io_bus_1 : inout std_logic_vector(31 downto 0); > io_bus_2 : inout std_logic_vector(31 downto 0); > ... ); > end entity wrapper; > > architecture str of wrapper is > signal en : std_logic; > signal int_bus_in : std_logic_vector(7 downto 0); > signal int_bus_out : std_logic_vector(7 downto 0); > signal int_bus : std_logic_vector(7 downto 0); > > component ip is > port( > io_bus_1 : inout std_logic_vector(7 downto 0); > io_bus_2 : inout std_logic_vector(7 downto 0); > ctrl : out std_logic; > ... ); > end component ip; > > begin > > ip_inst : ip > port map ( > io_bus_1 => int_bus, > io_bus_2 => io_bus_2(7 downto 0), > ctrl => en, > ... ); > > int_bus_out <= int_bus; > int_bus <= int_bus_in when en = '1' else (others => 'Z'); > > > end str; > -- > ____ _ __ ___ > | _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le - > | | | | | (_| |_| | Invalid return address: remove the - > |_| |_|_|\__|\___/Article: 78664
Symon & Bob, Thank you gentlemen for the link and part creation estimate. Seems well worth spending an hour or two to try this out. I wish Xilinx had posted this on their online support database, but I guess that may take revenue away from some of their parasitic EDA vendors/collaborators. -PNCArticle: 78665
Alex wrote: > [ Apologies if this is a frequently asked question but I've > been googling for hours and haven't found much info. ] > > I'm looking to buy a Spartan-3 Starter Kit:- > http://www.xilinx.com/products/spartan3/s3boards.htm# > in the UK. > > The only supplier in the UK with a website is nuhorizons.com > and I've seen some warnings about using them. > > I'll give Xilinx UK a call tomorrow (or Monday) but I'm > wondering if anyone has any suggestions for suppliers I can > check with. > > Or how quick/expensive is it to order from the US and deliver > to the UK. Which suppliers would you recommend? > > Ta, > > -Alex We bought ours directly from the Xilinx website and apart from the additional shipping costs, there were no hidden or extra charges. I think in total we paid around £75.00. BenArticle: 78666
When i synthesize my design in a SPARTAN3 XCS400 FPGA the synthesis report says that there are 8 blockRAMs available in Spartan3 FPGA . But after place and route and everything it says there are 16 blockRAMs available. So which one is actually correct. Does it also mean like if we used 9 blockRAMs then we are still under the limit of BLOCK RAMS or have we exceeded the design resources as the synthesis tool says. Thanks in advanceArticle: 78667
A pcb designer told me that in the "What's new" of Orcad 10.3 says that now it supports part generation from Xilinx ISE 6.2i files. I cannot try now, I have still no access to that release. "pnc" <mail2pnc@gmail.com> ha scritto nel messaggio news:1107582669.525371.99060@l41g2000cwc.googlegroups.com... > Symon & Bob, > > Thank you gentlemen for the link and part creation estimate. > Seems well worth spending an hour or two to try this out. I wish > Xilinx had posted this on their online support database, but I > guess that may take revenue away from some of their parasitic > EDA vendors/collaborators. > > -PNC >Article: 78668
On Fri, 4 Feb 2005 19:16:23 +0000 (UTC), Alex <uksb@greenbank.org> wrote: >[ Apologies if this is a frequently asked question but I've > been googling for hours and haven't found much info. ] > >I'm looking to buy a Spartan-3 Starter Kit:- > http://www.xilinx.com/products/spartan3/s3boards.htm# >in the UK. > >The only supplier in the UK with a website is nuhorizons.com >and I've seen some warnings about using them. > >I'll give Xilinx UK a call tomorrow (or Monday) but I'm >wondering if anyone has any suggestions for suppliers I can >check with. > >Or how quick/expensive is it to order from the US and deliver >to the UK. Which suppliers would you recommend? > >Ta, > >-Alex I ordered one recently off the xilinx website - only took a few days to arrive ISTR recently (probably here) seeing a well-hidden link on the xilinx site offering the S3 and CPLD devkits together for $99 (i.e. same as the S3 kit alone)Article: 78669
Alex <uksb@greenbank.org> wrote: [ SNIP original request ] Thank you for all of the replies. I've ordered directly from Xilinx and I'm looking forward to my new toy arriving. Ta, -AlexArticle: 78670
Hi John Williams has released a new autoconf uclinux BSP build for Xilinx EDK, but there are some troubles using the new hardware as well as rebuilding the kernel. The older microblaze-uclinux versions mbvanilla+older kernel tree did work very well, so the new stuff is braking something :( for the MicroBlaze uclinux BSP build there are fixes that allow XPS to build the autoconf file for the Kernel build but with the kernel build we hare still having trouble http://wiki.openchip.org/index.php/MicroBlaze_uCLinux_autoconf_6_30_a there are quick fixes to get the autoconf 6.30.a from John Williams website to actually work (or at least to to not produce fatal errors with EDK build), I think partially those fixes are actually fixing EDK minor bugs or version update issues. If some has succeeded to use the autoconf build hardare with recently updated kernel tree I would like to know (specially if there was some hacking involved to get the kernel to compile) AnttiArticle: 78671
Joerg wrote: > > Hello Spehro, > > >>It might not always pan out that way. I am just transitioning to a > >>European CAD program so the green flows in the other direction. They > >>didn't outsource it and still had the best pricing. > >> > >> > >Do you know that for a fact? A while ago I was talking to some > >developers who worked with their company's "European" team on a large > >software project- in St. Petersburg Russia. > > > > > > Sure, as a customer thousands of miles away you may not know for sure. > But there is one telltale sign that pops up when you have a tough > question. That will often require the original programmer or designer to > answer. Accents are really hard to hide. Like with a graphics card > manufacturer in Canada. When I got answers such as 'that's aboot right' > or I heard 'Bonjour' I somehow knew it's got to be Canada ;-) > > Regards, Joerg > > http://www.analogconsultants.com France??Article: 78672
"Mike Harrison" <mike@whitewing.co.uk> schrieb im Newsbeitrag news:d49901h2b5o38knfjla4orvjk9tjiofkun@4ax.com... > On Fri, 4 Feb 2005 19:16:23 +0000 (UTC), Alex <uksb@greenbank.org> wrote: > > >[ Apologies if this is a frequently asked question but I've > > been googling for hours and haven't found much info. ] > > > >I'm looking to buy a Spartan-3 Starter Kit:- > > http://www.xilinx.com/products/spartan3/s3boards.htm# > >in the UK. > > > >The only supplier in the UK with a website is nuhorizons.com > >and I've seen some warnings about using them. > > > >I'll give Xilinx UK a call tomorrow (or Monday) but I'm > >wondering if anyone has any suggestions for suppliers I can > >check with. > > > >Or how quick/expensive is it to order from the US and deliver > >to the UK. Which suppliers would you recommend? > > > >Ta, > > > >-Alex > > I ordered one recently off the xilinx website - only took a few days to arrive > ISTR recently (probably here) seeing a well-hidden link on the xilinx site offering the S3 and CPLD > devkits together for $99 (i.e. same as the S3 kit alone) > I think it was for visitors of Electronica 2004, the link was open, but hidden.. well in any case that offer isnt valid any more. But maybe there is some other similar offer who knows AnttiArticle: 78673
On Sat, 05 Feb 2005 14:23:50 GMT, Robert Baer <robertbaer@earthlink.net> wrote: > > France?? No Canada, where ATI and Matrox hail from.Article: 78674
The 'Altera Max+plus II advanced synthesis' is svailable at:
https://www.altera.com/support/software/download/altera_design/mp2_adv_syn/dnl-mp2_adv_syn.jsp
It will be useful if you are using VHDL or Verilog files in your design.
Hope this helps,
Subroto Datta
Altera Corp.
"SeungHeun, Lee" <kis2kima@hitel.net> wrote in message
news:ctvcs6$t6n$1@ccsun2.sogang.ac.kr...
> I used FLEX8000 device and developed with MAX2+. For poor performance,
> altera produced advanced synthesis tool as I know.
> Synthesis tool name is 'Altera Max+plus II advanced synthesis'. It is
> download free, but you may feel hard to find it from altera web site. :-)
>
> Regards,
> S.H, Lee
>
> "Vincent Perron" <vincent.perron@usherbrooke.ca> wrote in message
> news:8290822c.0502021107.6689e006@posting.google.com...
>> Here's a question I know has already been asked but I was not
>> satisfied with the answer.
>>
>> How could I get Quartus II to support the FLEX 8000 devices?
>>
>> I've already got a couple of FLEX 8000 chips and a complete version of
>> Quartus II 4.1. All the FLEX family is supported (6000, 10K, 10KA and
>> 10KE) except for the 8000.
>>
>> Is there a way to add the FLEX 8000 to this list? I would really
>> prefer working with Quartus II than Max Plus II.
>>
>> thx,
>> Vincent
>
>
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