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I have a design that writes to BRAMs and I was wondering if there is a way of reading back the information stored in the chip. A program similar to data2bram, but would be bram2data. Regards JacquesArticle: 80301
Amontec, Larry wrote: > Antti Lukats wrote: > >> http://www.latticesemi.com/products/fpga/xp/index.cfm >> >> Lattice XP is announced, pretty much at same time as S3E >> :) >> >> Antti >> >> > Salut Antti, > > Do you know the price of these kind of XP FPGA ? > Aahh..the guy from amontec.com which never answers my emails (o; According to Lattice Finland last autumn it should be around EC + external SPI...so just few cents more (o; rickArticle: 80302
<comparchfpga@yahoo.com> schrieb im Newsbeitrag news:d8f1f7dc.0503030912.1d6d3932@posting.google.com... > Hi, > > there was a thread with the same topic here: > > http://groups.google.de/groups?hl=de&lr=&selm=885a4a4a.0412030423.4f6b7e7c%4 0posting.google.com > > In addition to this I would like to know if it is possible and > advisable to make an > FPGA hot by intentionally creating contention within the FPGA. > > I know that this it not possible with HDL but with JBits this should > be possible. Why making short cicuits? A hugh shift register clocked at a high frequency (maybe DLLed x2 or x4) does it nice an legally. Been there, done that. Regards FalkArticle: 80303
"Brian Davis" <brimdavis@aol.com> schrieb im Newsbeitrag news:1109859840.603636.294350@l41g2000cwc.googlegroups.com... > V4 SI: The package is thrilling, but the Cin is bleak > Looking at the output waveforms shown in figure 20, my first > reaction was that it clearly showed that Xilinx hasn't done > much to improve their I/O cell capacitance [1] since V2. > > And, from DS302, V4 Cin = 10 pF, identical to the V2 spec. > > Meanwhile, the marketeering data rate has gone from > "840 Mbps" for V2 to "1 Gbps" for V4. > > What I'd expect to see from those plots, if the Altera I/O > capacitance is really half that of the Xilinx part: I dont think that Xilinx does intentionally slow down its IOs by adding capacitance. I guess the control slew rate a little bit more clever (using intentionally slower transistors) Regrds FalkArticle: 80304
"genlock" <genlocks@gmail.com> schrieb im Newsbeitrag news:1109804455.898192.250940@g14g2000cwa.googlegroups.com... > Thanks.....What I am looking for is a PLL to get a clock for off chip > use.......I am actually using it for a video application where I am > trying to genlock. Please let me know if have any ideas abt this..... So all you can do inside the FPGA are the prescalers and the phase/frequency detector. Have a look at the datasheet of the good old 4046, there you find everything. The VC(X)O and the loop filter will still be classic analog parts. Regards FalkArticle: 80305
Brian, Good posting. A few comments, below, Austin Brian Davis wrote: > V4 SI: The package is thrilling, but the Cin is bleak There is more to Cin that you are aware of. I'll go into that below. > > Peter wrote: > >>Still no comments on the newsgroup. >> > > I didn't catch the webcast, but looked at that BGA paper > last night. It appears to be limited in scope to discussing > package related output switching effects, which is not the > whole story for high speed I/O. By all means, no it was not. It was just one small (but critically important) aspect that limits the system performance. > > Looking at the output waveforms shown in figure 20, my first > reaction was that it clearly showed that Xilinx hasn't done > much to improve their I/O cell capacitance [1] since V2. Why should we do that? What is it about the Cout that is such a big deal? Driving the pcb trace, and the load at the other end swamps the intrinsic C of the pin in almost all cases. > > And, from DS302, V4 Cin = 10 pF, identical to the V2 spec. To do what we do (which is more than the competitor), we need the silicon area. Silicon area = C. > > Meanwhile, the marketeering data rate has gone from > "840 Mbps" for V2 to "1 Gbps" for V4. Sure has. Works great. Eye diagrams look fantastic (on a real board). > > Perhaps Dr. Johnson could proffer his honest opinion of > a "1 Gbps" LVDS receiver with a Cin of 10 pF [2]. I am sure he wioll answer that if asked in a fair and impartial way. Perhaps he will also point out that there is a lot more to the IO performance than just C? > > While the reduced output slew rate due to capacitive loading > may be of marginal "benefit" for low speed I/O standards, Ho ho ho. That is funny. Take the problem of slew rate out of control, and try to case our C as BAD because it slows us down SO WE WORK? Ha ha ha. I am rolling on the floor. Be serious. The C is what it is. It does not limit performance in any way. the > disadvantages of high I/O capacitance far outweigh the advantages, > especially for parts whose I/O is marketed as 1 Gbps capable. Bull-feathers. We work great. Altera works great, too (on a few pins, without anything else switching). > > Since you have that spiffy board at hand, I'd love to see > plots of the following: > > A) X vs. A ICCO for the "Hammer Test" at several toggle rates > > B1) X vs. A waveforms for a high speed single ended standard (xSTL) > B2) X vs. A ICCO for a high speed single ended standard (xSTL) > > C1) X vs. A waveforms for 1 Gbps differential LVDS > C2) X vs. A ICCO for 1 Gbps differential LVDS > > D) X vs. A differential TDR input waveforms into a DT termination > at 100, 200, 500 ps input edge rates We can do that. I will ask Mark to get some measurements of the Icco for the "hammer" test between the two boards. But something tells me that with the dI/dt being DOUBLE in the S2, you might not be so happy to see the results (again simple pin C is NOT the whole story for total power). > > > What I'd expect to see from those plots, if the Altera I/O > capacitance is really half that of the Xilinx part: If all the power is in the pin C, perhaps you will see a 30% improvement. Again, we may be talking less than 6 milliwatts per pin. Big advantage when the S2 won't work in a system. Oh my, my 72 pin bus switching at 200 MHz with 2.5V has ~430 mW more power than an S2......but it WORKS! > > A) dynamic ICCO would increase faster with frequency for the > Xilinx output driver > > B) the output waveforms would look worse at higher speeds for > the Xilinx driver Excuse me, the waveforms look fine. Excessive rise and fall times don't buy you anything but misery. HJ just proved that. > > C) Differential output switching would mitigate the SSO package > effects somewhat as compared to single ended switching at > the same rate Yes, the C is half differentially. > > D) input reflections would be worse for the Xilinx part Yes. But, since our termination is internal, and the driver is terminated, it doesn't matter. Do the simulation, the eye the receiver sees is just fine. Reflected signal (small) is absorbed by the transmitter, and does not cause distortion in the receiver. > > The last time I pointed out the impacts of high I/O capacitance > in this forum [3], a certain overzealous Xilinx engineer flamed > the thread into oblivion. Hopefully this thread will suffer a > gentler fate, with rational technical discussion prevailing. With good reason. You are not correct in assuming bad SI always results from pin C. If you terminate externally, I would agree with you. > > Brian > a longtime (mostly) Xilinx user who wants to see better parts > > [1] While I like the flexibility of the Xilinx general-purpose > nearly-all-IOBs-have-LVDS capability, if Cin could be improved > by having having some I/O banks without DCI or certain of the > I/O standards, I'd still buy the parts. Great. One customer who will accept non-uniform IO. Thanks. We'll keep that in mind if we ever get to where we have to do this to meet all specs and standards. SO far, we do, so we don't have to (have different IO pins). > > > [2] I'd be happy to quote a Cdiff instead, if someone could tell > me where it is documented. > > Ideally, the differential input model would include both > the single ended shunt Cin values as well as a differential > across-the-pair Cdiff, so I could model both the differential > and common mode reflections. > > If Cdiff is negligible, and the input waveform is purely > differential, then Cdiff = 1/2 Cin, as Austin has argued before. Uh, last I looked at circuit theory, it is still C/2 for the diff pair. It also agrees with simulations (if you instantiate the V4 receiver, and compare it to a circuit model of the same thing).Article: 80306
I used to have this problem, but it went away after installing XP SP2. "kcl" <kclo4@free.fr> wrote in message news:420222d6$0$19406$8fcfb975@news.wanadoo.fr... > Hi > > when i launch ModelSim 5.8c XE, the windows with the logo of modelsim( a > rhinoceros) open and after a few seconds it close and nothing else happen > there no process of modelsim running in the process list of winXP > I don't understand because last week It always run correctly. > I tried to reinstall Modelsim and it don't change > > Does anyone know this problem?? > > Thank you > > Alexis > > >Article: 80307
You will generate the correct average frequency, but with a deterministic jitter of a 24 MHz clock period = 42 ns, which may be objectionable. BTW, your method is called Direct Digital Synthesis (DDS), and you can explain it as a phase accumulator. Peter Alfke, Xilinx ApplicationArticle: 80308
Has anyone encountered this problem using Xilinx ISE 6.x ? 1. Implement a design so that it meets all timing constraints. 2. Run Backannotate to lock the pins down in the ucf file. 3. Set the PAR'd ncd file as the guide file for MAP and PAR. 4. Reimplement the design and have the timings change enough that constraints are not met. No changes done other than running backannotate to add the pin locs to the ucf file.Article: 80309
<fpgavhdl@gmail.com> wrote in message news:1109866293.591542.6120@g14g2000cwa.googlegroups.com... > Thanx... > > The video module design is a black burst generator...which has two > modes of operation.....When no external input is connected it has to > run as a master free running black burst generator....whereas when an > extrenal input is conected the black burst generated has to lock to the > incoming video signal Is this NTSC? Are you locking at 858 x fh, 4 x fsc, or something else? Is your H jitter OK when free running and locked? Are you synthesizing the sc from H with a ratio counter? Is the sc OK when free running? What is your source? If you're using a ratio counter how big is it? Are you using integral plus proportional feedback from the demodulated burst to the accumulator seed? If so, how did you choose these values? > I am using an sync stripper and an external PLL which is locking the > hsync generated from the sync stripper....ouput clk from the PLL along > wth the Hsync is given to the FPGA....where I wanna lock the > subcarrier.....which works fine....I mean it locks but with some > jitter...which I guess is not acceptable... > > Hope the details are fine...if u need more....let me know > You might want to check out this paper: http://www.bbc.co.uk/rd/pubs/reports/1986-02.pdf It's stuff I did over 25 years ago, but most if it is still valid. FPGAs are a lot faster than 74S283s and 74S374s, so you won't need to do things like factor the sc accumulator.Article: 80310
Use the old method: Looong shift register with the input flip-flop toggling. Gives you nicely distributed power, no reliability concerns, and extremely fine control through the clock frequency. What more can you possibly want? Peter AlfkeArticle: 80311
That's kind of funny. I heard everything from service pack 1 to 3. An other strategy would be to use the last version with all service packs, which is roughly equivalent to your suggestion. I have to admit that I sometimes try out versions without service packs, to check for compatibilty and new features. They are not that bad. Chris Duane Clark wrote: > Christian Schneider wrote: > >> They already call it 7.1 :-) Calling it version 7.0 would just do it, >> but some people refuse to install .0 versions :-) They just play the >> numbers game. >> > > My policy is that it doesn't get installed until service pack 3 is > available ;) >Article: 80312
> > Hi Jesse, > > Thanks for the quick response. I will try your suggestion to get the .ptf > going. > > On that topic, is there an easy way to change the timing requirements for > the SRAM that is used on the eval board? I use equivalent devices on my > board, but may want to use slower versions once the design is complete. i.e. > I would like to keep my sysclk as high as possible, but have the option of > using slower SRAM. Do I have to create an interface to user defined logic to > use SRAM that is the same as the eval board, but slower? It would be nice if > I could change the timing requirements in a .ptf file like we have discussed > for the LAN91C111. > > Thanks in advance, > > sja Hi sja, Well the intent with the product is to have you create an interface via the Component Editor (new SOPC Builder 4.2 feature), or previously, the "Interface to User Logic". Both of these tools allow you to specify which signals you want to export to the outside world, which are shared if using a tri-state bus, setup/wait/hold timing, etc. However if you're the adventurous sort, then as you've seen modifying the source files is another option (the component editor/interface to user logic basically creates similar files for you). In the case of the SRAM components in the Nios II dev kit, the timing figures in the class.ptf file are actually over-written by a perl script (mk_sram.pl), same folder as the class.ptf for those components, which is run at system-generation time. The reason behind this is that it allowed us to fine-tune SRAM timing depending on your system's clock speed... the script source is pretty easy to follow. If you take this route, I would save your changes in a separate component folder with separate 'class' name in the class.ptf file & separate entries in the SOPC Builder GUI (also in the class.ptf), that way your custom SRAM will show up independent of the one for the dev. kit...again though, that is what the Component Editor is for. Jesse Kempa Altera Corp. jkempa at altera dot comArticle: 80313
Hi, I am presently working on a design involving a RocketIO in a Virtex II Pro. I am looking at reference clocks for the PLL of the RocketIO meeting among other things the jitter requirement related to the serial link frequency. I am wondering how to combine deterministic jitter and random jitter parameters of the oscillator. Is the total jitter the rms value of the two parameters or do I need to add the maximums of each parameter ? Doesn't the answer depend on the device receiving the clock and therefore the way it deals with jitter ? Thanks, JFArticle: 80314
On 3 Mar 2005 08:55:29 -0800, "papu" <prachar@gmail.com> wrote: >HI, > > I am using PCAD 2002 and use XC9572 64 pin VQFP package in my PCB >design. I haven't been able to locate the pattern in PCAD 2002 library. >I have also looked through Altium's website for the pattern, but no >luck. Could anyone suggest where I can obtain it? Thank you. > >Papu Just create it - making patterns in PCAD is a doddle. Hint - it help a lot of you set the grid to the pin pitchArticle: 80315
Hi what algorithm does xpower use to calculate the freqency of internal nodes in a netlist ? is it some kind of transition density propagation but that method requires activity factor for primary inputs and also probabilities of primary inputs. Also is the interconnect power dissipation taken into account ? Thanks for any help swamyArticle: 80316
For people that worry about the small frequency difference between the "24 Mhz/ 13" and the "PC std UART frequency" of 1.8432 MHz it might be of interest to know that the modern PC UART clock frequency is generated from 24 Mhz run through a divide by 13. Trying to get exactly 1,8432 Mhz will thus increase your error! -- Best Regards, Ulf Samuelsson ulf@a-t-m-e-l.com This message is intended to be my own personal view and it may or may not be shared by my employer Atmel Nordic ABArticle: 80317
Fernando Peral wrote: > I want to use ATMEL ATF750 with ABEL, but i cant find a tool. > żis there any way? > > thanks Should you not get Prochip Designer if you want to use Atmel CPLD? -- Best Regards, Ulf Samuelsson ulf@a-t-m-e-l.com This message is intended to be my own personal view and it may or may not be shared by my employer Atmel Nordic ABArticle: 80318
On Wed, 02 Mar 2005 20:05:54 +0100, Jens Baumann <annonce05_nospam@web.de> wrote: >Hi, >I'd like to buy the Spartan3 board from Digilent >https://www.digilentinc.com/Sales/Product.cfm?Prod=S3BOARD > >However, it seems not to be available in Europe, as previous discussions in >this group show. > >Another oprion would be Memec >http://www.memec.com/uploaded/Spartan3LC_4.pdf >although I'd prefer Digilent for several reasons (on board ram, recommended >by Xilinx). Jens .. reconsider the Digilent .... If you go there , select the starterkit , click add to chart you get opportunity to select/upgrade to the new 2 boards they have. Upgrade to a S3-400 for $20 Upgrade to a S3-1000 for $50 Wish the S3-1000 was there when i bought from Xilinx Ohh Btw: I payed $29 @ Xilinx for shipment , but no additionals/SalesTax (maybe i was just lucky it came via DHL i think) Rgds Carsten DenmarkArticle: 80319
Another research project in this arena is DVS. http://csdl.computer.org/comp/proceedings/pads/2003/1970/00/19700173abs.htm and http://www.cs.mcgill.ca/~carl/dvs.pdf And as mentioned the communications bottleneck is an issue. Maybe the IBM Cell Processor is what we've been waiting for? :-) http://www-1.ibm.com/press/PressServletForm.wss?MenuChoice=pressreleases&TemplateName=ShowPressReleaseTemplate&SelectString=t1.docunid=7502&TableName=DataheadApplicationClass&SESSIONKEY=any&WindowTitle=Press+Release&STATUS=publish /EdArticle: 80320
Falk, No, we do not intentionally slow them down by adding C, but we do take full advantage of the intrinsic C that is there, so we do not have to slow them down as much as we would have to otherwise. And we most definitely slow them down, as to not slow them down results in an SI nightmare (like the one HJ described for the 2S60 1020 package). Austin Falk Brunner wrote: > "Brian Davis" <brimdavis@aol.com> schrieb im Newsbeitrag > news:1109859840.603636.294350@l41g2000cwc.googlegroups.com... > > >>V4 SI: The package is thrilling, but the Cin is bleak >> Looking at the output waveforms shown in figure 20, my first >>reaction was that it clearly showed that Xilinx hasn't done >>much to improve their I/O cell capacitance [1] since V2. >> >> And, from DS302, V4 Cin = 10 pF, identical to the V2 spec. >> >> Meanwhile, the marketeering data rate has gone from >>"840 Mbps" for V2 to "1 Gbps" for V4. >> >>What I'd expect to see from those plots, if the Altera I/O >>capacitance is really half that of the Xilinx part: > > > > I dont think that Xilinx does intentionally slow down its IOs by adding > capacitance. I guess the control slew rate a little bit more clever (using > intentionally slower transistors) > > Regrds > Falk > > >Article: 80321
Fernando Peral wrote: > I want to use ATMEL ATF750 with ABEL, but i cant find a tool. > =BFis there any way? > > thanks If it HAS to be Abel, your only choice is Synario. See: http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3D2755 But if you want to use CUPL (a similar language) you can get Atmel-WinCUPL at: http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3D2759Article: 80322
Falk Brunner wrote: > "Richard Thompson" <nospam@nospam.com> schrieb im Newsbeitrag > news:sqva219fvdhe8j9omvmpknfl2kl7ijrvkl@4ax.com... > > > >After all, what is a RS-FF good for nowadays?? > > > > The same things that it has always been good for. For a cost of 2 > > gates, it gives you a memory. It doesn't need a clock. It remembers an > > event until you have time to deal with it. It's ideal for handshaking, > > and for communicating between different clock domains. Can you name > > any other digital circuit which is so versatile, at such a small cost? > > Even if you ignore the 'cost', as you might do in an FPGA > > implementation? > > Uhhh? COST??? C'mon. In a FPGA, a handfull of Flipflops is always free. So > why asking for trouble and doing stone age handshakes when there are proven > solutions using standard methods (here, D-FlipFlops)? I wouldnt waste a > nanosecond thinking of RS-FlipFlops made of gates. Speaking of cost, is a LUT less costly than a flip-flop? In Xilinx Virtex parts, a LUT can be 16 flip-flops sometimes. Besides if you want both gate outputs from your cross-coupled NAND gates you need 2 LUTs. Another thing to wonder about, is whether changing a single LUT input creates the same output transition as with the implemented gates. For example if the output is the same for both states of the switched input, a gate will never glitch, but will the LUT glitch? This may depend on the implementation of the output multiplexer. > > Regards > FalkArticle: 80323
Falk and Peter, the methods you are mentioned are described in the thread I referenced. I accept that these methods are the best way to go. I beg your pardon, but my question remains unanswered. What is the problem with internal contentions ? Thank you.Article: 80324
comparchfpga@yahoo.com wrote: >Falk and Peter, > >the methods you are mentioned are described in the thread I referenced. >I accept that these methods are the best way to go. > >I beg your pardon, but my question remains unanswered. >What is the problem with internal contentions ? > > Well, in some architectures it can destroy the device. It may do this within a couple of seconds in some architectures! Jon
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