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Does anyone know of a good software for drawing timing diagram under linux/X11? thanks, jzArticle: 80251
essay wrote: > > It appears as though the Altera model for the interface to the LAN91C111 is > incorrect. The data sheet for this device shows the timing when the > LAN91C111 is used in asynchronous mode, and although the nRD & nWR signals > meet the timing shown in the data sheet, the minimum cycle time appears to > be violated. > ... > > Read_Wait_States = "20ns"; > Write_Wait_States = "20ns"; > Setup_Time = "20ns"; > Hold_Time = "20ns"; ... > Now, this wouldn't be a huge problem for me, if I was able to change it, but > it doesn't seem to be vary if I change the class.ptf file so that each of > the above times are, say, 40nS. This is really the second part of my > question. Should it be possible to change the timing as defined in the > class.ptf file? I have tried changing it outside of the SOPC builder but it > compiles the same regardless. Perhaps there is a trick here? Hi sja, Thanks for noting this. You are correct and this has been filed as a bug in our tracking system to fix in a future Nios II release. I believe the reason you're seeing this fail is because when CPU accessing Ethernet, even in a tight-loop, is probably not violating the SMSC spec as the accesses are not continuous.. on the other hand DMA will attempt continuous access. I have done DMA work to/from our previous Ethernet MAC (CS8900) and with on-chip MACs, but oddly enough not this one. That said, as you note it is an easy fix to edit the .ptf file as you indicate you have tried. The secret to this, though, is that the .ptf settings are copied into your system .ptf file when the component is added to your system in SOPC Builder. To make the fix permanent, you should close SOPC Builder, edit the class.ptf file for the lan91c111 component, open SOPC Builder, delete any existing 91c111 components from your system, and then add it back, and re-generate. Please advise if the above doesn't correct the problem. Jesse Kempa Altera Corp. jkempa at altera dot comArticle: 80252
Christian Schneider wrote: > They already call it 7.1 :-) Calling it version 7.0 would just do it, > but some people refuse to install .0 versions :-) They just play the > numbers game. > My policy is that it doesn't get installed until service pack 3 is available ;) -- My real email is akamail.com@dclark (or something like that).Article: 80253
Sticker with "Windows only", and both a Windows CD and a Linux CD in the case. Phil Hays -- Phil Hays Phil-hays at posting domain (- .net + .com) should work for emailArticle: 80254
I am looking to fix a problem while implementing Genlock inside the FPGA. It is for Video applications. The black burst generated locks to the external reference but has some jitter. Please reply if u can think of a solution.Article: 80255
To those that are familiar with this board, I need about 50 or so digital io lines with a max bit rate of about 1Mb per second. I was considering using the PCI slot, but since I don't really want to build a full PCI compliant board, I was wondering whether if it is possible to comfigure as I want? Secondly are the data and address line directly connected to the FPGA, it seem to appear so the the block diagram but there seems to be a lot of passive components around the slots. -- Wing Wong. Webpage: http://wing.ucc.asn.auArticle: 80256
Phil Hays <Spampostmaster@comcast.net> wrote: > >Sticker with "Windows only", and both a Windows CD and a Linux CD in >the case. No ISE 6.3i eval with it then? Did you get ISE 6.3i with the starter kit?Article: 80257
Hi, All: I am quite new to ABEL HDL, I am debugging a digital design and come across following code. ... IACK PIN 13; INT5 NODE ISTYPE 'REG'; IVEC NODE; EQUATIONS INT5 := 0; INT5.LH = IVEC; INT5.RE = !IACK; ... So, is INT5 a gated S-R Latch? if not, what is it? what will be the truth table? Seems to me INT5 will remain 0 forever. Regards MarkArticle: 80258
<kempaj@yahoo.com> wrote in message news:1109811051.021571.155460@l41g2000cwc.googlegroups.com... > essay wrote: > > > > It appears as though the Altera model for the interface to the > LAN91C111 is > > incorrect. The data sheet for this device shows the timing when the > > LAN91C111 is used in asynchronous mode, and although the nRD & nWR > signals > > meet the timing shown in the data sheet, the minimum cycle time > appears to > > be violated. > > > ... > > > > Read_Wait_States = "20ns"; > > Write_Wait_States = "20ns"; > > Setup_Time = "20ns"; > > Hold_Time = "20ns"; > ... > > Now, this wouldn't be a huge problem for me, if I was able to change > it, but > > it doesn't seem to be vary if I change the class.ptf file so that > each of > > the above times are, say, 40nS. This is really the second part of my > > question. Should it be possible to change the timing as defined in > the > > class.ptf file? I have tried changing it outside of the SOPC builder > but it > > compiles the same regardless. Perhaps there is a trick here? > > Hi sja, > > Thanks for noting this. You are correct and this has been filed as a > bug in our tracking system to fix in a future Nios II release. I > believe the reason you're seeing this fail is because when CPU > accessing Ethernet, even in a tight-loop, is probably not violating the > SMSC spec as the accesses are not continuous.. on the other hand DMA > will attempt continuous access. I have done DMA work to/from our > previous Ethernet MAC (CS8900) and with on-chip MACs, but oddly enough > not this one. > > That said, as you note it is an easy fix to edit the .ptf file as you > indicate you have tried. The secret to this, though, is that the .ptf > settings are copied into your system .ptf file when the component is > added to your system in SOPC Builder. To make the fix permanent, you > should close SOPC Builder, edit the class.ptf file for the lan91c111 > component, open SOPC Builder, delete any existing 91c111 components > from your system, and then add it back, and re-generate. > > Please advise if the above doesn't correct the problem. > > Jesse Kempa > Altera Corp. > jkempa at altera dot com > Hi Jesse, Thanks for the quick response. I will try your suggestion to get the .ptf going. On that topic, is there an easy way to change the timing requirements for the SRAM that is used on the eval board? I use equivalent devices on my board, but may want to use slower versions once the design is complete. i.e. I would like to keep my sysclk as high as possible, but have the option of using slower SRAM. Do I have to create an interface to user defined logic to use SRAM that is the same as the eval board, but slower? It would be nice if I could change the timing requirements in a .ptf file like we have discussed for the LAN91C111. Thanks in advance, sjaArticle: 80259
On Thu, 03 Mar 2005 03:42:41 +0000, nospam <nospam@nospam.invalid> wrote: >Phil Hays <Spampostmaster@comcast.net> wrote: > >> >>Sticker with "Windows only", and both a Windows CD and a Linux CD in >>the case. > >No ISE 6.3i eval with it then? Did you get ISE 6.3i with the starter kit? > There was a 6.3i with the starter kit and another 6.3i eval with the EDK. -- Phil Hays Phil-hays at posting domain (- .net + .com) should work for emailArticle: 80260
Thanks all for your help and guidance. I do not have any particular application in mind as of now, but I am just trying to test the fault tolerance in general and the extent of reliability that can be brought in. I want to study and give some quantitative details after testing practically - (ofcourse in conjunction with a simulator to inject faults) After reading your comments I am of impression that TMR is enough atleast as of now, I mean NMR wouldnt actually be needed (especially if the Mars Rover doesent need it) I am trying to work towards fault tolerance of the overall system, and am begning to think that immunity to transient faults must be brought at component level, and immunity to permanent faults would be on the system level? I am not quite sure how Time Redundancy works, does it do all this with such a low overhead that it can be neglected.My concern is that, As you are all aware real time embedded systems may have stringent timing requirements, in that case can time redundancy meet the race like the hardware redundancy - or is it like this - since both are done within the chip, there is not going to be a huge difference, considering that communication is what consumes a lot of time.... Any views on permanent fault tolerance techniques? Thanks once again, and would greatly appreciate any more resources like Special thanks to Mr.Sam for that paper, and Mr.Austin for in-depth explaination - things got more clear now.Article: 80261
I want to use ATMEL ATF750 with ABEL, but i cant find a tool. ¿is there any way? thanksArticle: 80262
I am trying to synthesize this piece of code
entity Coin is
Port ( reset : in std_logic;
quarter : in std_logic;
dime : in std_logic;
nickel : in std_logic;
isselvalid : in std_logic;
d2 : out std_logic_vector(3 downto 0);
d3 : out std_logic_vector(3 downto 0);
coinval : out integer range 0 to 95);
end Coin;
architecture Behavioral of Coin is
signal temp : integer range 0 to 95;
begin
process(reset,quarter,dime,nickel,isselvalid)
begin
if reset = '1' then
d2 <= "0000";
d3 <= "0000";
temp <= 0;
elsif isselvalid = '1' then
if quarter'event and quarter = '1' then
temp <= temp + 25;
elsif dime'event and dime = '1' then
temp <= temp + 10;
elsif nickel'event and nickel = '1' then
temp <= temp + 5;
else
temp <= temp;
end if;
else
temp <= temp;
end if;
coinval <= temp;
case temp is
when 0 =>
d2 <= "0000";
d3 <= "0000";
when 5 =>
d2 <= "0101";
d3 <= "0000";
when 10 =>
d2 <= "0000";
d3 <= "0001";
when 15 =>
d2 <= "0101";
d3 <= "0001";
when 20 =>
d2 <= "0000";
d3 <= "0010";
when 25 =>
d2 <= "0101";
d3 <= "0010";
when 30 =>
d2 <= "0000";
d3 <= "0011";
when 35 =>
d2 <= "0101";
d3 <= "0011";
when 40 =>
d2 <= "0000";
d3 <= "0100";
when 45 =>
d2 <= "0101";
d3 <= "0100";
when 50 =>
d2 <= "0000";
d3 <= "0101";
when 55 =>
d2 <= "0101";
d3 <= "0101";
when 60 =>
d2 <= "0000";
d3 <= "0110";
when 65 =>
d2 <= "0101";
d3 <= "0110";
when 70 =>
d2 <= "0000";
d3 <= "0111";
when 75 =>
d2 <= "0101";
d3 <= "0111";
when 80 =>
d2 <= "0000";
d3 <= "1000";
when 85 =>
d2 <= "0101";
d3 <= "1000";
when 90 =>
d2 <= "0000";
d3 <= "1001";
when 95 =>
d2 <= "0101";
d3 <= "1001";
when others =>
d2 <= "1111";
d3 <= "1111";
end case;
end process;
end Behavioral;
Quarter,dime and Nickel are 3 buttons that when pressed generate pulse. I
want to add 25,10 or 5 when they are pressed and pass the value on to a
display using d2 and d3. I have this error where it says temp has bad
sysnchrounous desription. Any comments on hw i can fix this?
thanks
Article: 80263> One thing that amazes me is that in Xeons even with RTL simulation the performance > degrades very guickly. I guess with 4 processors Xeons degrade very badly. In > Opterons there was no degradation to be seen. Well, at my previous workplace, there was a dual Pentium3/S (1.26GHz, 512K cache) server. Running two *independent* memory-intensive jobs simultaneously basically incurred a 60% performance hit. Another way to put it is this; if job-A takes one 1 hour by itself, and job-B takes 1 hour by itself -- launching both A+B simultaneously causes the completion time to increase to 1.6 hours (for both jobs.) ACKK!!! (This was for NC-Verilog 4.0.) > For the gate level simulations the results are almost identical, altough the dataset > is 15-20x larger and simulation times for the same case are longer. Also if 64b mode > was used Opteron became faster and Xeon EMT was little slower (very small differences > compared to 32b mode tough). That's very interesting to know. At my current workplace, we have an 'unofficial' (i.e., unsanctioned by management -- we're a Solaris department!) Athlon/64 3200+. From my firsthand experience, Cadence's WarpRoute and Buildgates/PKS5 benefit tremendously from 64-bit x86_64 vs 32-bit IA32 mode, something like a +30% boost in throughput. (The job's RAM footprint increases a bit, as expected and noted in the product's documentation.) The main problem is that a lot of older CAD-tools just "don't work right" under the 64-bit Linux O/S. Ironically, our ancient "signalscan" waveform viewer still runs, while our tool-guy can't figure out why Tetramax U-2003.06-SP1 refuses to work... It's really funny when a manager comes along and asks why the engineers like the Athlon/64 so much, and the engineers tell him "because it runs a synthesis job up to 3x faster than our fastest Solaris boxes."Article: 80264
steven wrote: > Xilinx V4 doc says one can expect 40% speed improvement over > previous generation (and nearest competing FPGA as well? ;-)) > > Ok, but what kind of improvement may I get when upgrading from > a V2Pro-7 to a V4-10? and what about -11 or latest -12 speed grades? > any figure? Howdy Steven, We've been looking at exactly that for a few of our designs. The answer is that it depends. If you study the timing specs in the latest datasheets, (sometimes with the aid of 6.3.3i speedprint), here's what you'll find: The core of the V4 looks to be somewhat faster, but setup and hold times into some elements have increased slightly over V2Pro, and unregistered clock-to-out times from memories (LUT or BRAM) are _slower_ than the V2Pro-5. Call it the triple-oxide effect? If you can afford to register your BRAM outputs, you can get the blindingly fast access (which is what their marketing department advertises). Global clock nets have considerably more delay as well (unless you use a DCM) - if you need low prop delay clock lines without a DCM, you must use regional clocks (which are a piece of cake now, although it sure seems like there are fewer total local clock resources now). I would highly recommend studying your top couple critical paths and compare the timing changes between the families to verify these differences won't adversely affect you. Or better yet, retarget the design to V4 and get the complete picture. Have fun, MarcArticle: 80265
fpgawizz wrote: > I am trying to synthesize this piece of code > entity Coin is > Port ( reset : in std_logic; > quarter : in std_logic; > dime : in std_logic; > nickel : in std_logic; > isselvalid : in std_logic; > d2 : out std_logic_vector(3 downto 0); > d3 : out std_logic_vector(3 downto 0); > coinval : out integer range 0 to 95); > end Coin; > > architecture Behavioral of Coin is > signal temp : integer range 0 to 95; > begin > > process(reset,quarter,dime,nickel,isselvalid) > begin > if reset = '1' then > d2 <= "0000"; > d3 <= "0000"; > temp <= 0; > elsif isselvalid = '1' then > if quarter'event and quarter = '1' then > temp <= temp + 25; > elsif dime'event and dime = '1' then > temp <= temp + 10; > elsif nickel'event and nickel = '1' then > temp <= temp + 5; > else > temp <= temp; > end if; > else > temp <= temp; > end if; [...] > Quarter,dime and Nickel are 3 buttons that when pressed generate pulse. I > want to add 25,10 or 5 when they are pressed and pass the value on to a > display using d2 and d3. I have this error where it says temp has bad > sysnchrounous desription. Any comments on hw i can fix this? Howdy, uhhh...wizz, First off, you're looking for comp.lang.vhdl, not comp.arch.fpga. But since you're here... I'll assume for the moment that you wrote the above code and your prof didn't give it to you and say "what is wrong with this code?" Try to draw the above circuit on paper - notice a problem with the nested FF's? So now your job is to figure out how to write the process such that it uses one clock (hopefully you have a free-running one), yet is able to handle all three token types. Again, draw the schematic on paper first... then find the HDL to describe the circuit. Have fun, MarcArticle: 80266
"KCL" <kclo4_NO_SPAM_@free.fr> wrote in message news:422642ed$0$25040$8fcfb975@news.wanadoo.fr... > For simulation probleme you could put a value to your signal when you > declare it > like: > > signal temp : std_logic :='0'; > like that it will have an initial value different from X at start but will > not be synthetized Perhaps that works easily with VHDL, but many Verilog synthesis tools may reject the equivalent: reg q; initial q = 1'b0; // for simulation-only! .... (or for a more modern Verilog-2001 tool) reg q = 1'b0;Article: 80267
Hi, john.deepu@gmail.com wrote: > reduce the area of the design , I have replaced many of the internal > registers ,with FFs without a RESET pin. [..] > I want to ask you people , whether this method of reducing area will > cause any problems(in the design flow) considering the total system. If you insert these FF in a scan chain, you could not reset them. I was told that this will be not acceptable for the ASIC vendor. Maybe you should check the needs of your vendor. bye Thomas -- Emailantworten bitte an thomas[at]obige_domain. Usenet_10 ist für Viren und Spam reserviertArticle: 80268
Prad wrote: > I am trying to work towards fault tolerance of the overall system, and > am begning to think that immunity to transient faults must be brought > at component level, and immunity to permanent faults would be on the > system level? You could gain immunity to transient faults by changing the design and/or by choosing a proper component (e.g Actel has Hi-Rel fpgas with build-in TMR). Further there are some transient faults (e.g Latchup) that seems to me only manageable by choosing a proper device. You could get a immunity to some permament errors by choosing a proper device, other permanent errors could only be overcome by changing the system. BTW The first point to fault tolerance (maybe the least investigated) is a robust design that overcomes _any_ faulty input. bye Thomas -- Emailantworten bitte an thomas[at]obige_domain. Usenet_10 ist für Viren und Spam reserviertArticle: 80269
<fpgavhdl@gmail.com> wrote in message news:1109816558.777802.49500@l41g2000cwc.googlegroups.com... >I am looking to fix a problem while implementing Genlock inside the > FPGA. It is for Video applications. The black burst generated locks to > the external reference but has some jitter. Please reply if u can think > of a solution. > We need a bit more information. Are you locking H to H? Are you generating the s/c from H with a ratio counter. Are you then pulling the s/c according tothe burst? Give us a few lines of detailed description, and we might be able to help.Article: 80270
In article <1109430337.324162.241140@l41g2000cwc.googlegroups.com>, <manan.kathuria@gmail.com> wrote: >hi everybody , i have a few questions regarding setup and hold timing >1. what is the reason a hold time / setup time is needed....i tend to >think its down at the transistor level but i cant exactly put my finger >on it ...something to do with the prop delay? When I first started out in digital design, an old-time engineer told me a few basic rules. The first was this: "There is no such thing as digital." In the realizable devices that engineers actually work with, there are only analog circuits approximating digital behavior. The component wires and transistors creating a flop, a gate, any digital circuit, all have finite capacitances and resistances. The power supply can only deliver a finite current. Thus, any logic circuit node, to go from a logical 0 to a logical 1, will have a finite slew rate passing through the voltages in between those that define the logic levels. A flop is designed so that the output should only change during a window of time near the clock edge. Get there too late, and you can't slew the output all the way before the window in time ends. Change the input too soon and the output capacitor(s) may only get charged up part way to the new logic level. Either way, end up too close to the threshold, and your flop is no longer approximating a digital circuit. The people writing the data sheet call this a set-up or a hold-time violation (which saves them from having to fully document every gate and flop as an actual analog circuit). Why can't one avoid this problem by defining any voltage as either a logical 1 or logical 0 so that there is no "in-between"? Old-timer electrical engineering rule #2: "There is no such thing as ground." Given any noise, as well as circuit variation, etc., a signal near the threshold is statistically undefined. Logic circuits need some margin to be reliable. >2. would a level triggered , i.e. non master slave type flip flop have >a setup time or just a hold time?.....since there is no intermediate >now... You still have both a setup and a hold time, since the gap in between is what defines a window in time relative to the clock signal. Whether one of either the setup time or the hold time is negative depends on the relative delays of the clock and the input. >3. what happens if the hold/setup time is not met....does the output >not change or does it become unpredictable? You have an analog circuit. What happens next depends on the exact logic family and circuit design, ground noise, thermal noise, crosstalk, capacitive coupling, both positive and negative feedback paths, etc. etc. This, of course, is just a brief sketch of the subject. Lot's of IEEE papers on the subject were published from the 70's onward. IMHO. YMMV. -- Ron Nicholson rhn AT nicholson DOT com http://www.nicholson.com/rhn/ Applications Engineering - Leopard Logic, Inc. #include <canonical.disclaimer> // only my own opinions, etc.Article: 80271
Instantiating IBUFG as a component shows up in ISE with a ? next to it in the navigator since there is no HDL source file for the declared primitive. Why is this? The design maps/translates and works fine on the card.Article: 80272
You have to find out if leaving c1 unconnected dosent affect the functionality of the design.Article: 80273
“Design and Implementation of a CFAR Processor for Target Detection”, César Torres-Huitzil, Rene Cumplido-Parra, Santos López-Estrada, 14th International Conference on Field Programmable Logic, FPL04. Antwerp, , August 2004. Lectures Notes on Cumputer Science Vol. 3203, pp. 943-947. ISBN 3540229892. “On the Implementation of an efficient FPGA-based CFAR Processor for Target Detection”, Rene Cumplido, César Torres, Santos López. 1st International Conference on electrical and Electronics Engineering, Acapulco, México. September 2004. IEEE Catalog number: 04EX865C, ISBN: 0-7803-8532-2.Article: 80274
Hi everyone. This i my first post in this forum. I saw it several days ago and i found interesting things to read. Here is my problem. I designed a SLAVE peripheral connected to plb_ipif in a PPC system for V2Pro. But due to performance issues now i want to add some more functions and make it MASTER + the capability of using the DMA controller in the plb_ipif. I am planning to use simple DMA without ScatterGather. My design has to transfer data to the memory using the DMA function. But ... I read the plb_ipif and DMA/SG spec and i still don't get it. Which signals of the PLB IPIF user interface I should use? How this thing works in general? .. and so on. Who will set up the DMA .. the PPC or my design. And if it is my design how will it know the destination Memmory address that should be used to set up the DMA? Any help is appreciated. I have a lot of other questions .. but I hope I can answer them all by myself. Thank you in advance.
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Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z