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Messages from 79925

Article: 79925
Subject: Re: Maximum Current utilized by Spartan-3
From: "Peter Alfke" <peter@xilinx.com>
Date: 25 Feb 2005 16:44:02 -0800
Links: << >>  << T >>  << A >>
The easiest for you would be to "play" with an existing evaluation
board, where you can easily find out the power consumption of different
designs. Implement a long shift register with a toggling first
flip-flop ( relatively high power) or a counter  ( less power per bit).
You should be able to do a lot of logic with 2.5 A and 50 MHz...
Peter Alfke


Article: 79926
Subject: Re: SVF file
From: Neil Glenn Jacobson <n.e.i.l.j.a.c.o.b.s.o.n.a.t.x.i.l.i.n.x.c.o.m.>
Date: Fri, 25 Feb 2005 16:49:01 -0800
Links: << >>  << T >>  << A >>
What you want to do is use the "iMPACT" application to generate SVF 
files.  If you open that up and choose  "Generate Programming File" from 
the wizard, you should be able to figure it out.


AL wrote:
> Hi,
> 
> I want to create an SVF file. I have read this documentation and it said that I need to open a shell and invoke "jtagprog", I did that but didn't work. I have also tried to find the graphical user interface tool in Project Navigator, but no luck. Does anyone know why? Thanks, AL


Article: 79927
Subject: Re: Maximum Current utilized by Spartan-3
From: Jake Janovetz <jakespambox@yahoo.com>
Date: Fri, 25 Feb 2005 21:42:46 -0600
Links: << >>  << T >>  << A >>
Yaju N wrote:
> I am using a Spartan 3 the PQ 208 package. The maximum input current
> available to the board is going to be 2.5A. I am just concerned whether
> that will be good enough. I am planning on using a 50Mhz oscillator on
> the board, similar to the one one the Spartan 3 demo board.
> 
> I am not sure what my application is going to be. I am currently
> developing the board as a part of my Master's research. So I will be
> experiementing with different designs on the board. I just wanted to
> finalise the board so that the FPGA would be a ready to go product,
> without having to worry about the power and current.
> 
> The online estimation tool requires some very specific information
> about the prospective design or application which I may not be able to
> accurately predict at this point. But I guess I will give it a try.
> 
> I guess what I would be looking for if I have missed an "CRITICAL"
> current or power specs, which might render my board useless if I
> implement some amazingly futuristic design or application.
> 
> Is power and current specification a very important issue at all, as I
> feel I might be speding too much time on something trivial? I am
> planning on just throwing in the new TPS7xxx buck regulator hoping it
> will work fine. Other than that I guess my advisor suggests sticking to
> the Linear Dropout Regulators as used in those Demo Board, since they
> have been in use for a while and hopefully they work fine.
> 
> Yaju
> y a j u at b y u edu
> 


If this is just a one-off or very low volume device that doesn't require 
  a high-efficiency power source, why wouldn't you use an LDO?  They're 
easy!  Although switchers, etc, are getting easier and more reliable, 
they're more complicated -- just in component count alone.

Also-- what's wrong with off-the-shelf eval boards?

    Jake


Article: 79928
Subject: Re: Digilent D2SB FPGA Boards
From: hmurray@suespammers.org (Hal Murray)
Date: Sat, 26 Feb 2005 00:55:22 -0600
Links: << >>  << T >>  << A >>

>I've singled out the Digilent "D2SB" product with the "DIO4"
>daughterboard, but I'm wondering if anyone here can share their
>experience with this particular board (is it reliable?) or this
>manufacturer in general (are they reputable?). Is there another board I
>should be looking at? I was attracted to the D2SB due to the price and
>the wide range of addons available. The board is available at
>http://www.digilentinc.com

Why did you pick the D2SB over their Spartan 3 board?  Same price
but more IO stuff on the main board.  I think it includes most of
what you get on the DIO4 board.

Their boards are fine.  Xilinx likes them enough to use them for
the Spartan 3 starter kit.

Documentation is reasonable.  (I found some pin swap screwups on
connectors.  I think that was on the AIO1 board.  Otherwise I'd
say great.)

One thing to beware of.  Their IO connectors are very thin on
ground pins.  Don't be surprised by troubles at high speeds.


-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 79929
Subject: Re: embedded 2005 in Nuernburg
From: "Antti Lukats" <antti@openchip.org>
Date: Sat, 26 Feb 2005 08:41:08 +0100
Links: << >>  << T >>  << A >>

"Kenneth Land" <kland_not_this@neuralog_not_this.com> schrieb im Newsbeitrag
news:111v1edrpm6nj18@news.supernews.com...
>
> "Antti Lukats" <antti@openchip.org> wrote in message
> news:cvioa6$n6q$03$1@news.t-online.com...
> > Hi
> >
> > just a few FPGA related news
- snip -
>
> Antti,
>
> Did you check out the ERIC5 core from Entner Electronics?  How did it
look?
> I'm pretty sure they had a booth there.
>
> Thanks,
> Ken
>
>

Hi Ken,

yes Eric5 was there!
and haha first time when I did see Actel ProAsic+ development board being
useful  - as booth demo for Eric5
there where some other fpga boards from other manufacturers also running
Eric5 demo

Antti



Article: 79930
Subject: pci x core on virtex II
From: sandeep.karkera05@gmail.com (Sandy)
Date: 25 Feb 2005 23:50:42 -0800
Links: << >>  << T >>  << A >>
Hello everyone,

i want to design pci x bridge on virtex II but i need to select the
device before i start the deign.
can any experianced help me to select the device.

thanks everyone

sandy

Article: 79931
Subject: EDK IPIF FIFO Problems
From: digitreaco@yahoo-dot-de.no-spam.invalid (digi)
Date: Sat, 26 Feb 2005 02:04:35 -0600
Links: << >>  << T >>  << A >>
Hallo to all

Description:

With help of EDK6.3i CreatWizard and IPIF a have make a ReadFIFO, 4
depth and 32Bit lenght. In Vhdl Code I implement a routine: When I
push a Button then the Fifo get 4 Data f.e. 0x2,0x4,0x8,0xA.
At another Site a want read Data from Fifo with my ppc405. I load
Programm that do somethink and i absorve my memory!
When I push the Button my fifo get this data 0x2,0x4,0x8,0xA and the
Status register get 0x00000003, its all ok! But when i go 1 Step with
the Debuger further the Statusregister get 0 and the Data from my Fifo
disappear :-(

What is there a problem?

thanks!


Article: 79932
Subject: re:Problems with a 4-MicroBlaze Multiprocessor Architecture
From: sergio.tota@polito-dot-it.no-spam.invalid (sergio.tota)
Date: Sat, 26 Feb 2005 02:04:35 -0600
Links: << >>  << T >>  << A >>
Dear Goran,

you told me that not uploading the firmware does not mean that
MicroBlaze doesn't "work".

Do you mean that even if with no code to execute they make access to
the OPB bus?
If so, why?

And, there is a way to keep a MicroBlaze processor "live" without
making it access to the OPB bus?

I think that I'll use FSL, but in the next months.

Cheers.

Sergio


Article: 79933
Subject: Interfacing virtex 2 pro to flash memory
From: stud_lang_jap@yahoo.com (williams)
Date: 26 Feb 2005 02:40:59 -0800
Links: << >>  << T >>  << A >>
Hello guys,

I wanted to know how can i interface virtex 2 PRO FPGA to flash
memory. I think you need a PLD for address counting. Can some please
provide more information about it? what is the logic i have to
implement in the PLD.

Thanks and regards
williams

Article: 79934
Subject: spartan 3 vs virtex 2
From: "Benjamin Menküc" <benjamin@menkuec.de>
Date: Sat, 26 Feb 2005 12:48:35 +0100
Links: << >>  << T >>  << A >>
Hi,

what are the main differences between these two fpga's. I havent found a 
clear statement about that on the xilinx website.

regards,
Benjamin 



Article: 79935
Subject: Re: spartan 3 vs virtex 2
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: Sat, 26 Feb 2005 11:59:40 +0000 (UTC)
Links: << >>  << T >>  << A >>
"Benjamin Menk?c" <benjamin@menkuec.de> wrote:
> Hi,

> what are the main differences between these two fpga's. I havent found a 
> clear statement about that on the xilinx website.

Did you have a look at the datasheets?

-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 79936
Subject: lwip on spartan3
From: adrian <adrian.mora@terra.es>
Date: Sat, 26 Feb 2005 12:58:32 GMT
Links: << >>  << T >>  << A >>
Hi there,

I am trying to design a network application on a Spartan 3 Starter Board 
with an ethernet module incorporated using lwIP.
In the past I have managed to run network applications on Virtex II Pro 
boards based on xilinx application note xapp663.pdf "TCP/IP on Virtex-II 
Pro Devices Using lwIP".
I would like to ask if anybody has succesfully used lwIP on a Spartan 3 
    board and if there is any application note from xilinx on this 
respect or any information that could be of any interest.

Thankyou,

Adrian.

Article: 79937
Subject: Re: spartan 3 vs virtex 2
From: "Benjamin Menküc" <benjamin@menkuec.de>
Date: Sat, 26 Feb 2005 14:57:45 +0100
Links: << >>  << T >>  << A >>
Hi,

I have seen that the spartan-3 has no power pc core and only upto 5M Gates 
and less onchip RAM.

Are these the main differences?

What is the disadvantage of a software implemented processor in comparison 
to the virtex-2 power pc?

What are the main advanteges of the virtex-II compared to the Spartan-3?

regards,
Benjamin 



Article: 79938
Subject: Re: spartan 3 vs virtex 2
From: "Benjamin Menküc" <benjamin@menkuec.de>
Date: Sat, 26 Feb 2005 15:22:25 +0100
Links: << >>  << T >>  << A >>
The Virtex Family can also run on a higher clock rate.

I want to play a little bit around with digital communication applications, 
like spread spectrum. Should I start with a virtex or a spartan-3?

regards,
Benjamin 



Article: 79939
Subject: Re: NiosII Vs MicroBlaze
From: "Kenneth Land" <kland_not_this@neuralog_not_this.com>
Date: Sat, 26 Feb 2005 08:23:20 -0600
Links: << >>  << T >>  << A >>

"Antti Lukats" <antti@openchip.org> wrote in message 
news:cvn4ua$qm4$05$1@news.t-online.com...
> ...
> the difference is in the way the IP cores are delivered.
>
> SOPC ip cores are written in Perl and use special package "Europa"
> to generate either VHDL or Verilog, so thats why it is possible to
> choose either verilog or VHDL in SOPC
>
>...
> Antti

I'd like to add that SOPC IP cores can be written in *at least* vhdl, 
verilog, or bdf.  You do not have to write your cores in Perl!

There is a wizard that imports your hdl/bdf and even generates a parameter 
wizard for your core if needed!

You can also just create a custom interface to a core by setting up the 
signals in a simple wizard then connecting them to the core in Quartus. 
That core then appears as a memory mapped peripheral.  Very simple.

We have cores integrated into our NiosII system using a mix of these 
methods.

Ken


>
>
>
>
>
>
> 



Article: 79940
Subject: livedesign or ise
From: "Benjamin Menküc" <benjamin@menkuec.de>
Date: Sat, 26 Feb 2005 15:39:38 +0100
Links: << >>  << T >>  << A >>
Hi,

I am planning to start fpga designing. I am not sure wheather I should start 
with the livedesign kit from Altium or just with ISE? I want do develop a 
spread spectrum system. I am not sure yet wheather I want to use an embedded 
processor or not, but most likely I will.

Can somebody give me some hints?

regards,
Benjamin 



Article: 79941
Subject: setup-hold time problems
From: manan.kathuria@gmail.com
Date: 26 Feb 2005 07:05:37 -0800
Links: << >>  << T >>  << A >>
hi everybody , i have a few questions regarding setup and hold timing
1. what is the reason a hold time / setup time is needed....i tend to
think its down at the transistor level but i cant exactly put my finger
on it ...something to do with the prop delay?

2. would a level triggered , i.e. non master slave type flip flop have
a setup time or just a hold time?.....since there is no intermediate
now...

3. what happens if the hold/setup time is not met....does the output
not change or does it become unpredictable?

I'd love answers to these questions.....a few links thrown in would be
awesome!

Thanks a lot

Manan


Article: 79942
Subject: programming 2 pulses using VHDL
From: "fpgawizz" <bhaskarstays@yahoo.com>
Date: Sat, 26 Feb 2005 10:25:04 -0500
Links: << >>  << T >>  << A >>
I am trying to program 2 pulses - basically a 0-1-0-1-0 transitions. I have
a clock inout to my module. I am not sure how to use this clock and get 2
pulses and just stop after that., These 2 pulses are used to light an LED.
So it goes on and off and on again.

Any thoughts?



Article: 79943
Subject: Re: spartan 3 vs virtex 2
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: Sat, 26 Feb 2005 15:42:47 +0000 (UTC)
Links: << >>  << T >>  << A >>
"Benjamin Menk?c" <benjamin@menkuec.de> wrote:
> Hi,

> I have seen that the spartan-3 has no power pc core and only upto 5M Gates 
> and less onchip RAM.

> Are these the main differences?

Mostly

> What is the disadvantage of a software implemented processor in comparison 
> to the virtex-2 power pc?

Speed, power and LUT usage

> What are the main advanteges of the virtex-II compared to the Spartan-3?

You have listed them above.

The main disadvantages are:
- higher price
- No TQFP package abailable

Bye
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 79944
Subject: Re: spartan 3 vs virtex 2
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: Sat, 26 Feb 2005 15:45:53 +0000 (UTC)
Links: << >>  << T >>  << A >>
"Benjamin Menk?c" <benjamin@menkuec.de> wrote:
> The Virtex Family can also run on a higher clock rate.

> I want to play a little bit around with digital communication applications, 
> like spread spectrum. Should I start with a virtex or a spartan-3?

Look at the available evaluation boards, their prices and their capabilities
and compare with the capabilities you expect and the price you are willing
to pay.

Bye
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 79945
Subject: Re: programming 2 pulses using VHDL
From: Lukasz Salwinski <lukasz@ucla.edu>
Date: Sat, 26 Feb 2005 08:01:15 -0800
Links: << >>  << T >>  << A >>
fpgawizz wrote:
> I am trying to program 2 pulses - basically a 0-1-0-1-0 transitions. I have
> a clock inout to my module. I am not sure how to use this clock and get 2
> pulses and just stop after that., These 2 pulses are used to light an LED.
> So it goes on and off and on again.
> 
> Any thoughts?
> 
> 
say a counter that starts to count down from, say, 4 down to 0
when triggered. and a pulse output that is set to high at
the apropriate moments ?

l

Article: 79946
Subject: Re: spartan 3 vs virtex 2
From: "Peter Alfke" <alfke@sbcglobal.net>
Date: 26 Feb 2005 08:29:21 -0800
Links: << >>  << T >>  << A >>
Let me explain from a Xilinx perspective:
Virtex wants to bring you the highest performnce, most features, up
tothe  largest size, at a reasonable price.
Spartan wants to bring you the lowest possible price, with reasonable
performanc and feature set and size.
Or to put it another way:
Virtex is faster, has more features and extends to larger chips, but is
more expensive.
Spartan is cheaper, but lacks some speed, features, and does not extend
that far.

That said, there are lots of simularities, especially between Virtex-II
and Spartan3.
Peter Alfke, Xilinx Applications.


Article: 79947
Subject: Re: setup-hold time problems
From: "Peter Alfke" <alfke@sbcglobal.net>
Date: 26 Feb 2005 08:44:23 -0800
Links: << >>  << T >>  << A >>
Let me give you an analogy:
If you want to fly somewhere, the airline tells you to be at their
counter (say) one hour before departure time. That's the set-up time.
They guarantee you that you will be let on the airplne if you appear on
time.
If you violate the set-up time, you take a chance. You may, or may not,
get on the plane.
Hold time is the ugly result of a design mistake inside the flip-flop,
when the internal clock delay is longer than the internal data delay.
For the past 40 years, IC designers have known how to avoid this
problem inside the flip-flop. But it can pop up as a system problem,
when clocks have too much delay.

What you call level-triggered flip-flop, I would call a latch, and it
is half of a flip-flop. You need both the master and the latch, to
prevent race conditions.
Another analogy: A flip-flop behaves like the rotating hotel door.
People (data) can get through, but the wind cannot blow through...
Read some good text books!
Peter Alfke


Article: 79948
Subject: block adder for Altera!
From: "cecilia annovi" <shaula82@tiscali.it>
Date: Sat, 26 Feb 2005 18:51:12 +0100
Links: << >>  << T >>  << A >>
hi
my name is Cecilia and I'm a student in engineering at the university of 
Modena & Reggio Emilia. For my disseration I must work with Altera's FPGA. 
I must analize signals from an EEG with multipliers and adders. the signal's 
type is real, (float precision) so I'm working, to get my pourpuse, with 
floating point. Well, I found the multiplier for floating point in the mega 
wizard plug in manager (altfpmult) and it works well, but I can't find an 
adder/subtracter for floating point! I' ve tried to built one with VHDL, but 
I'm far from the target (it's not so easy..).
So I ask you if you can find me an adder subctracter (obviously free...! the 
univesity wouldn't spend any money for my project!!)and can explain me the 
way to use it (I don't have the complete knowledge of the Quartus!)
I'm using the Quartus II SJ web edition version 4.2 Built
156.I'll develop my project on a Cyclone II technology. Thank you....! 
Cecilia


NB. I've alredy searched in the IP megastore but their cores are too much 
expensive! 



Article: 79949
Subject: Re: setup-hold time problems
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Sat, 26 Feb 2005 18:51:35 +0100
Links: << >>  << T >>  << A >>
"Peter Alfke" <alfke@sbcglobal.net> schrieb im Newsbeitrag
news:1109436263.847581.49590@f14g2000cwb.googlegroups.com...

You analogies are just great. And cute ;-))

Regards
Falk








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