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Igor, We did that too. As I already posted, the difference was about 2:1 better with the new V4 packages. Even our previous packages were not all that bad. But, they could be improved upon, so we did for this generation. For a first order comparison, look at the di/dt for V2P (about the same as V4), and the ball pattern. Count the average IO per power/ground pin ratio and examine placement to compare the two. Ultimately, we have the SSO table to reflect the package capabilities, so if you are within those guidelines, there is no performance penalty expected. We also consider other factors in the tables (like system jitter, not just Vil(max)), so designers have succesful boards, and we do not get cases. Austin IgI wrote: > Hi! > > I really enjoyed the presentation. I didn't realize how fast the time passed > and before I was able to write down all my questions it was all over. So > next time reserve at least 1/2 hour for QA session. Besides the comparison > between Virtex-4 and Stratix-2 I was hoping to see comparison between > Virtex-II/Pro and Virtex-4. > > Regards, > Igor Bizjak > > "Peter Alfke" <peter@xilinx.com> wrote in message > news:1109786492.673401.81320@f14g2000cwb.googlegroups.com... > >>Still no comments on the newsgroup. >>Those of you who want to (re)visit Howard Johnson's presentation can do >>this by clicking on >> >>http://www.xilinx.com/products/virtex4/pdfs/BGA_Crosstalk.pdf >> >>Peter Alfke, Xilinx Applications >> > > >Article: 80226
For transient faults, yes TMR is the most reliable method. If you are using Xilinx FPGA there is an entire application note dedicated to the different configurations of implementing TMR. Redundacy is required for making a system fault tolerant. The reliability of the system depends on how much redundancy you are willing to introduce in the system. For example if you want to tolerate double faults use NMR (N >5, N is odd) system.Article: 80227
KCL wrote: > Personnaly I have bought digilent board spartan to a french distributor would you tell the distributor's name? I don't want to order from th US, because I have no idea about customs fees. > But You should wait to see the price of the next starter kit spartan3e > that have more stuff on it , but for the price it's actually unknow :on > board > :S3e 500 -4, 32MByte SDRAM, usb2,ethernet phy , 2 lines LCD display.... > sound great any reference? JensArticle: 80228
"Dave Colson" <dscolson@rcn.com> writes: > I was told that the benefit of two CPUs is that you can run another > application while simulating and not have your computer slow down > because the other application will run from the other CPU. I would rather have two single CPU systems. In some cases it's cheaper. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 80229
So, is there real black magic behing the socket of my athlon 1.8GHZ processor???Article: 80230
On 1 Mar 2005 00:12:06 -0800, reachranbir@gmail.com wrote: >Hi, >I am Ranbir from eQURA Consulting. >Guys, my client, which is a San Diego based wireless telecom giant. >They were the original inventors of CDMA technology. > ******* First off why the heck are you dancing around but not saying that the company is Qualcomm! Anyone associated with the cell phone industry knows that CDMA/CDMA2000 is a Qualcomm protocol. >They have recently set up a next gen design centre here in Bangalore, >India. >We are looking at various profiles, starting from frontend, backend to >verification managers. > >If interested do contact me on +91 09845365740 >ranbir@equra.com ********** No thanks. I care not to relocate from Florida to India. jamesArticle: 80231
"B. Joshua Rosen" <bjrosen@polybus.com> writes: > Parallel simulators are apparently a much harder problem then you > might suspect. A number of years ago I was discussing this issue I find this quite surprising as well. It has been discussed a few times in comp.lang.verilog (like in http://tinyurl.com/6z9jv). > IKOS (since bought by Mentor). To me it seemed that simulation > should be a highly parallel problem but he claimed that there had be > a number of attempts at parallel software simulators (as opposed to > hardware acceleration engines) and that no one had succeeded. With I think many of the EDA vendors are expecting linear speedup so they can apply a linear pricing policy. If the license cost was flat, e.g. they viewed a cluster as a single fast machine I would be happy to accept less than linear speedup and just throw sub-1k$ PC's at my simulation to increase its performance. I'm also surprised that there aren't many parallel synthesis tools and place & route tools (Xilinx par support a very coarse grain parallelism) out there either. Must be a great opportunity for MPI programmers with EDA knowledge... Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 80232
On 1 Mar 2005 21:57:32 -0800, big_in_russia@yahoo.com wrote: >Hi Ranbir! > >So, are you looking for Americans to move to India? It's so great that >India is finally going to take care of all the engineers here who lost >their jobs due to outsourcing. > ***** Oh don't touch that subject, outsourcing. I still have not calmed down from the last battle I had over that. That was two years ago. They get hi tech jobs and we get to work at Home Depot. Not an admirable trade off. >Will I be able to afford a Qualcomm-chipset based phone with the pay I >get? > ****** Probably not! >Thanks in advance! > >reachranbir@gmail.com wrote in message news:<1109664726.181045.112170@z14g2000cwz.googlegroups.com>... >> Hi, >> I am Ranbir from eQURA Consulting. >> Guys, my client, which is a San Diego based wireless telecom giant. >> They were the original inventors of CDMA technology. >> >> They have recently set up a next gen design centre here in Bangalore, >> India. >> We are looking at various profiles, starting from frontend, backend to >> verification managers. >> >> If interested do contact me on +91 09845365740 >> ranbir@equra.comArticle: 80233
Jason Zheng <xin.zheng@jpl.nasa.gov> writes: > Place-n-route can already be done in pseudo-parallel fashion with > xilinx's modular design. You can simply run two processes that each Actually the Xilinx par tool has supported a coarse grained parallelism for many years (using the -m option, on Solaris that is). I remember having my par job running on half a dozen or so dual and quad sparc systems. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 80234
"Leon Heller" <leon_heller@hotmail.com> writes: > If you want to see what Qt looks like, the Pulsonix PCB software I Or check http://www.trolltech.no Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 80235
Petter Gustad <newsmailcomp6@gustad.com> writes: > I want to simulate the GT_CUSTOM swift model under VCS. According to > Xilinx the following VCS versions are qualified under Linux (ISE 6.3i) > > Linux (redhat 7.3 / 8.0) = VCS 7.0 2002.12.r16(scirocco) > Linux Enterprise Edition V3.0 = VCS_MX7.1.R22 Does anybody know which version of VCS which is qualified under ISE 7.1. Is it a release version of VCS (and not some in-house version)? Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 80236
john.deepu@gmail.com wrote: > Hi all, > I am currently implementing a module which has large number of > registers(the datapath is heavily pipelined and lotsa registers). To > reduce the area of the design , I have replaced many of the internal > registers ,with FFs without a RESET pin. > So now all the internal register dont get cleared (reset) while > applying an external reset. they just keep on shifting unknown value, > until the actual data fills in the pipeline. this is perfectly > acceptable for me except for the initial X's I see in waveform, till > the actual data reaches to the point. > > I save around 10-15% area by this way. (in a total size of ~90K). > My module is part of a ~1.5Mgates asic. > > I want to ask you people , whether this method of reducing area will > cause any problems(in the design flow) considering the total system. > > please giveme ur valuable suggestions. > > thanks a lot > Deepu John > One problem can occur with back annotated gate sims. It is possible to create logic that works but cannot be simulated unless you have a way to initialize registers to a known value. (Anything but X). But as you noticed it can be costly to put a reset on every flop in the design. Not only is there an area cost but you have to route that reset around the entire chip and meet setup/hold timing on every flop. I like the idea of multicycle resets where you are required to hold a reset for X number of cycles. Then as long as you can reset everything by cycle X then everything will work. John EatonArticle: 80237
Hello ALL, I am having hard time designing the schematic to interface conventional SDRAM chip to Virtex-4 FPGA. As a SDRAM we have selected Micron 256Mbit part with 32 bit wide data bus. Both packages a BGA, Virtex-4 is FF-672 type, SDRAM is FBGA-90. Our chips is planned to be located about 5-10mm (0.2-0.4 inches) from each other and the longest trace is suppose to be about 2.0-2.5 inches. We are also planning to have data bus traces to be as short as possible. First approximation gives about 1.3-1.5 inches data bus traces. The trace impedance is planned to be about 53-55Ohms. The interface is planned to run at 125MHz. The memory we are going to use has conventional 3.3V interface. We are planning to use DCI for all outputs in our design, i.e. control signals, address bus, clock and clock enable signals. Doing simulation we found that DCI does pretty good job for all these lines - there is no overshot/undershot problems at all on all these lines. The only problem is the data bus. Than signal originates from Virtex-4 FPGA everything goes fine, because DCI still active for this direction, everything becomes bad when signal originates from SDRAM. There is significant overshot and undershot around every edge of the signal. Its value goes as high as 4.2V for overshot and to -900mV for undershot. This extreme condition lasts for 200-300 picoseconds according to our simulation. For simulation we are using Virtex-4 and SDRAM Ibis models from manufacturers. The relatively simple solution is to terminate each line in data bus, but it requires relatively lots of space on the PCB and can not be done reliably :( As soon as Micron driver gets terminated properly the line becomes less than suitable for Virtex-4 driver, something in between is not very good for both of them. The funniest thing that I saw several existing and reliably working designs, using average trace length about 2.5 inches with similar components working with close frequencies and DOES NOT using any series termination on data lines with default FPGA drivers. So, what part are we missing? Should we believe in simulation or it is not as accurate as expected? With best regards, Vladimir S. MirgorodskyArticle: 80238
Hello Steven. Thanks for your reply. Steven K. Knapp wrote: > We recommend the direct programming approach for SPI Flash PROMs as it is > the simplest and fastest. As you pointed out though, it is not the only > method. There is a forthcoming application note that provides additional > SPI programming options. The real problem is PCB estate and device programming. It is going to be much cheaper to use a single interface for product configuration and testing. > The direct programming approach is also useful with some third-party SPI > Flash programmers that support in-system programming using a socket adapter > (example: Needam's Electronics). The idea is to exactly avoid that. ;) > We already have a similar, documented approach for programming attached > parallel NOR Flash via JTAG as part of the MicroBlaze EDK software. See the > following link. > http://www.xilinx.com/ise/embedded/est_rm.pdf I am aware of that solution. However I was looking for something more simple and integrated with Xilinx configuration solutions (as Antti already pointed out). > One advantage of Spartan-3E FPGAs is that _all_ of the configurations pins > can be reclaimed as full-featured user-I/O after configuration. This means > that you can easily access external SPI or parallel NOR Flash. This means > that you can program the attached memory from the FPGA. Yes, this is really nice and what triggered my inquiry. I was expecting that Xilinx tools were going to exploit that feature out of the box. > Stay tuned for details. I will :D Thanks again. Regards. -- /"The three most dangerous things in the world are PabloBleyerKocik / a programmer with a soldering iron, a hardware pbleyer / type with a program patch and a user with an idea." @embedded.cl / -- Rick Cook, The Wizardry CompiledArticle: 80239
Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> writes: >> I'm trying to choose between gtk and QT - QT does seem to be more >> portable. Your 7.1 posting makes me think that ISE 6.3 isn't using QT, >> though - any idea what it does use? > > WindU, requiring a per seat license, reason why there is no Webpack for Linux. Though the ISE 7.1i announcement reiterates what Xilinx employees have said on this newsgroup before, which is that there will be a Linux version of WebPACK 7.1i. As I recall, it was said that they were switching from Wind/U to a different toolkit.Article: 80240
Jim George <jimgeorge_@_gmail.com> writes: > I guess the only downside to ISE 7 is that we bought ISE 6.3 > just a few weeks back :-( Won't you get 7.1i then as part of your year of support?Article: 80241
On Wed, 02 Mar 2005 22:40:04 +0100, Petter Gustad wrote: > "B. Joshua Rosen" <bjrosen@polybus.com> writes: > >> Parallel simulators are apparently a much harder problem then you >> might suspect. A number of years ago I was discussing this issue > > I find this quite surprising as well. It has been discussed a few > times in comp.lang.verilog (like in http://tinyurl.com/6z9jv). > >> IKOS (since bought by Mentor). To me it seemed that simulation >> should be a highly parallel problem but he claimed that there had be >> a number of attempts at parallel software simulators (as opposed to >> hardware acceleration engines) and that no one had succeeded. With > > I think many of the EDA vendors are expecting linear speedup so they > can apply a linear pricing policy. If the license cost was flat, e.g. > they viewed a cluster as a single fast machine I would be happy to > accept less than linear speedup and just throw sub-1k$ PC's at my > simulation to increase its performance. > > I'm also surprised that there aren't many parallel synthesis tools and > place & route tools (Xilinx par support a very coarse grain > parallelism) out there either. Must be a great opportunity for MPI > programmers with EDA knowledge... > > Petter Part of the problem might be that past attempts at parallelism were trying to use large numbers of processors. Speedups of 2x, which is the absolute maximum that you can get a dual processor system, aren't all that interesting, you certainly wouldn't have bought a special machine just to get a 2X speedup. You might have bought a 32 processor server if you could get a 20x speedup on it, but trying to break up a simulation over that many processors isn't very doable. With the introduction of dual cores the equation changes. Soon every midlevel and higher PC is going to come with two processors, and the workstation class machines will all have a pair of dual core processors. Getting a simulator to take advantage of two to four very tightly coupled processors should be a lot easier then getting it to scale to 32 or 64 loosely coupled cpus. Also the potential market is larger because everyone will have at least two processors in their systems.Article: 80242
Sam, Go to the IRoC website: http://www.iroctech.com/ They describe redundancy in space (like TMR), redundancy in time (like process the problem three times, each after a scrub or reloading of the configuration, and vote on the results), or parallel state and data path error checking (ie calculate a parity or CRC for all state machines and data paths, and pass that, and check that at each stage. These are three common techniques used for highly reliable designs (like space control systems, aircraft, robots, etc.) We see these techniques (or a mixture of them) now being used in FPGAs due to the concerns with soft errors, as well as due to errors caused by other means (signal integrity, jitter, etc.) having nothing to do with FPGAs. For example, a packet processing system has an entering CRC, and an exiting CRC. They should be the same if the packet did not change. If they are different, through the packet out (do not acknowledge receipt) -- it will be resent to you. The Mars Rovers use scrubbing (reprogramming at an interval) to assure that the FPGA has no upset bits (to an acceptable rate). They did not have to use TMR to meet their goals. Given their goals are pretty tough to meet, why do you think you need TMR? Generally speaking, not all of any design is critical, so not all of the design needs to be triplicated. Only the critical parts. Most designs have startup logic, test logic, and performance monitoring logic that has nothing to do with the critical function. We have seen ratios of 2:1 up to 8:1 for logic that is not critical compared to logic that is critical. A careful study of your application may show that you need to triplicate (or duplicate if all you need to know is that there was an error, fixing it requires three copies) much less than the entire design. Austin sam wrote: > For transient faults, yes TMR is the most reliable method. If you are > using Xilinx FPGA there is an entire application note dedicated to the > different configurations of implementing TMR. Redundacy is required > for making a system fault tolerant. The reliability of the system > depends on how much redundancy you are willing to introduce in the > system. For example if you want to tolerate double faults use NMR (N > >>5, N is odd) system. > >Article: 80243
"Jens Baumann" <annonce05_nospam@web.de> a écrit dans le message de news: 42262b9e$0$29283$14726298@news.sunsite.dk... > KCL wrote: > >> Personnaly I have bought digilent board spartan to a french distributor > would you tell the distributor's name? > > I don't want to order from th US, because I have no idea about customs > fees. the french distributor is lextronic http://www.lextronic.fr/digilent/PP.htm but I should have pay 160? for the board+supply+fee but try avnet/silica the reference of board is DO-SPAR3-DK I was in touch with them for the xilinx starter kit if you want the commercial contact form avnet france ask me for the @ >> But You should wait to see the price of the next starter kit spartan3e >> that have more stuff on it , but for the price it's actually unknow :on >> board >> :S3e 500 -4, 32MByte SDRAM, usb2,ethernet phy , 2 lines LCD display.... >> sound great > > any reference? > actually not it is just described on the xilinx website but as spartan3e 500 is not yet released, the board may be not, marketing guy sold the product before technie do it.... If you are not hurry to get it , you should wait and seeArticle: 80244
For simulation probleme you could put a value to your signal when you declare it like: signal temp : std_logic :='0'; like that it will have an initial value different from X at start but will not be synthetized Alexis "J o h n _ E a t o n (at) hp . com (no spaces)" <"J o h n _ E a t o n (at) hp . com (no spaces)"> a écrit dans le message de news: 42263428$1@usenet01.boi.hp.com... > john.deepu@gmail.com wrote: >> Hi all, >> I am currently implementing a module which has large number of >> registers(the datapath is heavily pipelined and lotsa registers). To >> reduce the area of the design , I have replaced many of the internal >> registers ,with FFs without a RESET pin. >> So now all the internal register dont get cleared (reset) while >> applying an external reset. they just keep on shifting unknown value, >> until the actual data fills in the pipeline. this is perfectly >> acceptable for me except for the initial X's I see in waveform, till >> the actual data reaches to the point. >> >> I save around 10-15% area by this way. (in a total size of ~90K). >> My module is part of a ~1.5Mgates asic. >> >> I want to ask you people , whether this method of reducing area will >> cause any problems(in the design flow) considering the total system. >> >> please giveme ur valuable suggestions. >> >> thanks a lot >> Deepu John >> > > One problem can occur with back annotated gate sims. It is possible to > create logic that works but cannot be simulated unless you have a way > to initialize registers to a known value. (Anything but X). > > But as you noticed it can be costly to put a reset on every flop in the > design. Not only is there an area cost but you have to route that reset > around the entire chip and meet setup/hold timing on every flop. > > I like the idea of multicycle resets where you are required to hold a > reset > for X number of cycles. Then as long as you can reset everything by cycle > X then everything will work. > > John Eaton > > > > > > >Article: 80245
Thanks.....What I am looking for is a PLL to get a clock for off chip use.......I am actually using it for a video application where I am trying to genlock. Please let me know if have any ideas abt this.....Article: 80246
Austin, I too agree that the entire design in not susceptible to SEUs. ( I have an entire paper on that http://klabs.org/richcontent/MAPLDCon03/papers/c/c1_samudrala_p.pdf). But we also found that there is a loss of SEU immunity with decreasing redundancy. Time redundancy is good but cant be used for real time data as detecting and correcting takes a lot of time. The inputs have to be stored on the memory on in the FPGA which is risky unless they are rad-hard. Scrubbing is a great feature, but can be a problem when there is a SEFI. And again scrubbing at regular interval needs an uncorrupted source of data that has to be stored separately in a rad hard memory chip. So, my view is that for 100% immunity(against single bit errors) TMR is the best way.Article: 80247
Hi All I found a document on the Xilinx-Website that explained how to do that (Xilinx Synopsys Interface) Unfortunatly I can't find the required files in my installation of the Xilinx-Webedition (synopsys/libraries/dw/src) Are those files only provided with the full ISE ? Greetings AndiArticle: 80248
Way Cool Al! "Al Clark" <dsp@danvillesignal.com> wrote in message news:Xns960D8FBD5DE97aclarkdanvillesignal@66.133.129.71... > Analog Devices, Altera and Danville Signal joined forces to create the > ADDS-21261/Cyclone DSP & FPGA Evaluation Package featuring Danville's new > dspstak 21261zx DSP Engine and dspstak c96k46 I/O Module. >Article: 80249
The simple designs are working fine on the evaluation board, and not big power consumers. What if I want to use all the logic that is available to me on the Spartan -3 FPGA (PQ 208). For now, I have a 50Mhz oscillator on board, so the application would run at a maximum of 50Mhz. The FPGA board derives its power from another board, which can provide upto a maximum of 2.5A. I am basically looking for the worst case power or current requirements for the FPGA. As this is part of my research, I would be creating designs which put the FPGA to its limit, basically using as much as the FPGA can offer. It would not be impressive, if I my board burns up because of the high power application I implement on the FPGA. Its interesting that I have been unable to find any documentation on this topic online. Thanks for any help, Yaju N y a j u attherate b Y u eD u Peter Alfke wrote: > The easiest for you would be to "play" with an existing evaluation > board, where you can easily find out the power consumption of different > designs. Implement a long shift register with a toggling first > flip-flop ( relatively high power) or a counter ( less power per bit). > You should be able to do a lot of logic with 2.5 A and 50 MHz... > Peter Alfke
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Compare FPGA features and resources
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